[llvm] [Mips] Optimize instr `slti+mfc1+cvt.s.d` to `slti+mfhc1` (PR #187463)

[via llvm-commits]

https://github.com/yingopq created https://github.com/llvm/llvm-project/pull/187463

Fix #171262.

>From d67887863a3ea8e33072aa778a0162bf81896045 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Thu, 19 Mar 2026 17:28:36 +0800
Subject: [PATCH] [Mips] Optimize instr `slti+mfc1+cvt.s.d` to `slti+mfhc1`

Fix #171262.
---
 llvm/lib/Target/Mips/MipsInstrFPU.td    |  4 ++++
 llvm/test/CodeGen/Mips/slti-mfc1-cvt.ll | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 llvm/test/CodeGen/Mips/slti-mfc1-cvt.ll

diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 942faf6ea223d..b6bd862794d70 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -1011,6 +1011,10 @@ def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
       FGR_64;
 
+def : Pat<(setlt (i32 (bitconvert (f32 (fpround AFGR64Opnd:$src)))), 0),
+          (SLTi (MFHC1_D32 AFGR64Opnd:$src), 0)>,
+          ISA_MIPS32R2, FGR_32;
+
 def : MipsPat<(f64 (any_sint_to_fp GPR32Opnd:$src)), 
               (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
 def : MipsPat<(f32 (any_sint_to_fp GPR64Opnd:$src)),
diff --git a/llvm/test/CodeGen/Mips/slti-mfc1-cvt.ll b/llvm/test/CodeGen/Mips/slti-mfc1-cvt.ll
new file mode 100644
index 0000000000000..9ed8cccc04870
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/slti-mfc1-cvt.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=MIPS32
+
+define i32 @test_sign_bit(double %a) nounwind {
+; MIPS32-LABEL: test_sign_bit:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mfhc1	$1, $f12
+; MIPS32-NEXT:    slti $1, $1, 0
+; MIPS32-NEXT:    addiu	$2, $zero, -4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    or $2, $1, $2
+
+entry:
+  %conv = fptrunc double %a to float
+  %i_val = bitcast float %conv to i32
+  %1 = icmp slt i32 %i_val, 0
+  %2 = select i1 %1, i32 -3, i32 -4
+  ret i32 %2
+}