[llvm] [X86] Improve handling of i512 SHL(-1, Amt) + SRL(-1, Amt) "mask shifts" (PR #186806)

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 17 05:35:07 PDT 2026

Previous message: [llvm] [X86] Improve handling of i512 SHL(-1, Amt) + SRL(-1, Amt) "mask shifts" (PR #186806)
Next message: [clang] [llvm] [AArch64] Add 9.7 data processing intrinsics (PR #186807)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/186806

Previous message: [llvm] [X86] Improve handling of i512 SHL(-1, Amt) + SRL(-1, Amt) "mask shifts" (PR #186806)
Next message: [clang] [llvm] [AArch64] Add 9.7 data processing intrinsics (PR #186807)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list