[llvm] [RISCV] Relax out of range Zibi conditional branches (PR #186965)

[Pengcheng Wang via llvm-commits]

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@@ -310,14 +314,15 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   MCRegister SrcReg1 = MI.getOperand(0).getReg();
-  MCRegister SrcReg2 = MI.getOperand(1).getReg();
+  MCOperand Src2 = MI.getOperand(1);
   MCOperand SrcSymbol = MI.getOperand(2);
   unsigned Opcode = MI.getOpcode();
   bool IsEqTest =
       Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
 
   bool UseCompressedBr = false;
   if (IsEqTest && STI.hasFeature(RISCV::FeatureStdExtZca)) {
+    MCRegister SrcReg2 = Src2.getReg();
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wangpc-pp wrote:

`IsEqTest` indicates that `Src2` is a register.

https://github.com/llvm/llvm-project/pull/186965