[llvm] AMDGPU: Delay value replacement in PromoteAlloca (PR #186944)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-promote-alloca < %s | FileCheck %s
+
+define amdgpu_ps void @_amdgpu_ps_main() {
+; CHECK-LABEL: define amdgpu_ps void @_amdgpu_ps_main() {
+; CHECK-NEXT:  [[_ENTRY:.*:]]
+; CHECK-NEXT:    [[HIT_ORDERED:%.*]] = freeze <16 x float> poison
+; CHECK-NEXT:    [[HIT_INDEX:%.*]] = freeze <16 x i32> poison
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <16 x i32> [[HIT_INDEX]], i32 0, i32 0
+; CHECK-NEXT:    br [[DOTLR_PH5:label %.*]]
+; CHECK:       [[_LR_PH5:.*:]]
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <16 x i32> [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <16 x float> [[HIT_ORDERED]], float 0.000000e+00, i32 [[TMP1]]
+; CHECK-NEXT:    ret void
+;
+.entry:
+  %hit_ordered = alloca [16 x float], align 4, addrspace(5)
+  %hit_index = alloca [16 x i32], align 4, addrspace(5)
+  store i32 0, ptr addrspace(5) %hit_index, align 4
+  br label %.lr.ph5
+
+  ; The separate block is needed to avoid constant-folding on
+  ; the load from %hit_index.
+.lr.ph5:                                          ; preds = %.entry
+  %0 = load i32, ptr addrspace(5) %hit_index, align 4
+  %1 = getelementptr float, ptr addrspace(5) %hit_ordered, i32 %0
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jmmartinez wrote:

Can you name the unnamed registers?

https://github.com/llvm/llvm-project/pull/186944