[llvm] [RISCV] Relax out of range Zibi conditional branches (PR #186965)

[Pengcheng Wang via llvm-commits]

================
@@ -309,15 +313,17 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
                                           SmallVectorImpl<char> &CB,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
-  MCRegister SrcReg1 = MI.getOperand(0).getReg();
-  MCRegister SrcReg2 = MI.getOperand(1).getReg();
+  MCOperand Src1 = MI.getOperand(0);
+  MCRegister SrcReg1 = Src1.getReg();
----------------
wangpc-pp wrote:

Well, I just want to make the code symmetric. :-)


https://github.com/llvm/llvm-project/pull/186965