[llvm] [AArch64][GISel] length aware BITCAST between different-element-width fixed vectors (PR #179123)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,38 @@
+; REQUIRES: aarch64-registered-target
+; RUN: llc -mtriple=aarch64-unknown-linux-musl -global-isel -global-isel-abort=1 < %s | FileCheck %s
+
+define <2 x i8> @test_bitcast_assertion(<4 x i32> %vqaddq_v2.i.i, ptr %BS_VAR_0) {
+; CHECK-LABEL: test_bitcast_assertion:
+; CHECK:       sub sp, sp, #16
+; CHECK:       movi v[[ZERO_REG:[0-9]+]].2d, #0
+; CHECK:       mov [[PTR_TMP:x[0-9]+]], sp
+
+; CHECK:       .LBB0_1: // %for.cond
+; CHECK:       umov [[EXTRACTED:w[0-9]+]], v[[ZERO_REG]].h[0]
+; CHECK:       str q0, [sp]
+; CHECK:       umull [[IDX:x[0-9]+]], [[EXTRACTED]], w9
+; CHECK:       ldrh w[[VAL_REG:[0-9]+]], [[[PTR_TMP]], [[IDX]]]
+; CHECK:       stp q[[ZERO_REG]], q[[ZERO_REG]], [x0, #32]
+; CHECK:       stp q[[ZERO_REG]], q[[ZERO_REG]], [x0, #64]
+; CHECK:       fmov d[[RES_REG:[0-9]+]], x[[VAL_REG]]
+; CHECK:       stp q[[ZERO_REG]], q[[ZERO_REG]], [x0, #96]
+; CHECK:       mov v[[RES_REG]].d[1], xzr
+; CHECK:       stp q[[RES_REG]], q[[ZERO_REG]], [x0]
+; CHECK:       b .LBB0_1
+
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond, %entry
+  %0 = phi <64 x i16> [ %2, %for.cond ], [ zeroinitializer, %entry ]
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arsenm wrote:

Use named values in tests 

https://github.com/llvm/llvm-project/pull/179123