[llvm] [SelectionDAG] Provide context for vector count / type mismatch (PR #175433)

[Matt Arsenault via llvm-commits]

================
@@ -330,6 +330,17 @@ static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
   return Ctx.emitError(I, ErrMsg);
 }
 
+/// Emit a fatal error if the broken down registers don't match part type
+/// or count.
+static void ensureMatchedVecRegParts(unsigned NumRegs, unsigned NumParts,
+                                     MVT RegisterVT, MVT PartVT) {
+  if (NumRegs != NumParts || RegisterVT != PartVT)
----------------
arsenm wrote:

Early return and reduce indent 

https://github.com/llvm/llvm-project/pull/175433