[llvm] [AMDGPU] Add scheduling DAG mutation for hazard latencies (PR #170075)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,76 @@
+//===--- AMDGPUHazardLatency.cpp - AMDGPU Hazard Latency Adjustment -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file contains a DAG scheduling mutation to adjust the
+///       latency of data edges between instructions which use registers
+///       potentially subject to additional hazard waits not accounted
+///       for in the normal scheduling model.
+///       While the scheduling model is typically still accurate in these
+///       scenarios, adjusting latency of relevant edges can improve wait
+///       merging and reduce pipeline impact of any required waits.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUHazardLatency.h"
+#include "GCNSubtarget.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SIInstrInfo.h"
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+
+using namespace llvm;
+
+namespace {
+
+class HazardLatency : public ScheduleDAGMutation {
+private:
+  const GCNSubtarget &ST;
+  const SIRegisterInfo &TRI;
+  const MachineRegisterInfo &MRI;
+
+public:
+  HazardLatency(MachineFunction *MF)
+      : ST(MF->getSubtarget<GCNSubtarget>()), TRI(*ST.getRegisterInfo()),
+        MRI(MF->getRegInfo()) {}
+  void apply(ScheduleDAGInstrs *DAG) override;
+};
+
+void HazardLatency::apply(ScheduleDAGInstrs *DAG) {
+  constexpr unsigned MaskLatencyBoost = 3;
+
+  if (!ST.hasVALUMaskWriteHazard() || !ST.isWave64())
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arsenm wrote:

Why does this depend on the wave size?

https://github.com/llvm/llvm-project/pull/170075