[llvm] [X86][GISEL] Enable PostLegalize Combiner (PR #174696)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 30 09:52:02 PST 2026
https://github.com/mahesh-attarde updated https://github.com/llvm/llvm-project/pull/174696
>From ec5b5c1b0e0142e89e04e9491f95cfc64c15750a Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Tue, 16 Dec 2025 01:20:59 -0800
Subject: [PATCH 1/5] [X86][GISEL] Enable PostLegalize Combiner
---
llvm/lib/Target/X86/CMakeLists.txt | 4 +-
.../X86/GISel/X86PostLegalizerCombiner.cpp | 196 ++++++++++++++++++
llvm/lib/Target/X86/X86.h | 2 +
llvm/lib/Target/X86/X86Combine.td | 3 +
llvm/lib/Target/X86/X86TargetMachine.cpp | 7 +
5 files changed, 211 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index f2880d6c6ea5e..5e4aed41fd7c3 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -21,7 +21,8 @@ tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM X86GenFoldTables.inc -gen-x86-fold-tables -asmwriternum=1)
tablegen(LLVM X86GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="X86PreLegalizerCombiner")
-
+tablegen(LLVM X86GenPostLegalizeGICombiner.inc -gen-global-isel-combiner
+ -combiners="X86PostLegalizerCombiner")
add_public_tablegen_target(X86CommonTableGen)
set(sources
@@ -89,6 +90,7 @@ set(sources
GISel/X86CallLowering.cpp
GISel/X86InstructionSelector.cpp
GISel/X86LegalizerInfo.cpp
+ GISel/X86PostLegalizerCombiner.cpp
GISel/X86PreLegalizerCombiner.cpp
GISel/X86RegisterBankInfo.cpp
)
diff --git a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
new file mode 100644
index 0000000000000..8032ba9cdcd12
--- /dev/null
+++ b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
@@ -0,0 +1,196 @@
+//=== X86PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// Post-legalization combines on generic MachineInstrs.
+///
+/// The combines here must preserve instruction legality.
+///
+/// Lowering combines (e.g. pseudo matching) should be handled by
+/// X86PostLegalizerLowering.
+///
+/// Combines which don't rely on instruction legality should go in the
+/// X86PreLegalizerCombiner.
+///
+//===----------------------------------------------------------------------===//
+#include "X86.h"
+#include "X86TargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
+#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/Combiner.h"
+#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
+#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/Support/Debug.h"
+
+#define GET_GICOMBINER_DEPS
+#include "X86GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_DEPS
+
+#define DEBUG_TYPE "X86-postlegalizer-combiner"
+
+using namespace llvm;
+using namespace MIPatternMatch;
+
+namespace {
+
+#define GET_GICOMBINER_TYPES
+#include "X86GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_TYPES
+
+class X86PostLegalizerCombinerImpl : public Combiner {
+protected:
+ const CombinerHelper Helper;
+ const X86PostLegalizerCombinerImplRuleConfig &RuleConfig;
+ const X86Subtarget &STI;
+
+public:
+ X86PostLegalizerCombinerImpl(
+ MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+ GISelValueTracking &VT, GISelCSEInfo *CSEInfo,
+ const X86PostLegalizerCombinerImplRuleConfig &RuleConfig,
+ const X86Subtarget &STI, MachineDominatorTree *MDT,
+ const LegalizerInfo *LI);
+
+ static const char *getName() { return "X86PostLegalizerCombiner"; }
+
+ bool tryCombineAll(MachineInstr &I) const override;
+ bool tryCombineAllImpl(MachineInstr &I) const;
+
+private:
+#define GET_GICOMBINER_CLASS_MEMBERS
+#include "X86GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CLASS_MEMBERS
+};
+
+#define GET_GICOMBINER_IMPL
+#include "X86GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_IMPL
+
+X86PostLegalizerCombinerImpl::X86PostLegalizerCombinerImpl(
+ MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+ GISelValueTracking &VT, GISelCSEInfo *CSEInfo,
+ const X86PostLegalizerCombinerImplRuleConfig &RuleConfig,
+ const X86Subtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI)
+ : Combiner(MF, CInfo, TPC, &VT, CSEInfo),
+ Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI),
+ RuleConfig(RuleConfig), STI(STI),
+#define GET_GICOMBINER_CONSTRUCTOR_INITS
+#include "X86GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CONSTRUCTOR_INITS
+{
+}
+
+bool X86PostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
+ if (tryCombineAllImpl(MI))
+ return true;
+ LLVM_DEBUG(dbgs() << "\nNo table match found.\nTry Custom Combine for "
+ << MI);
+ return false;
+}
+
+class X86PostLegalizerCombiner : public MachineFunctionPass {
+public:
+ static char ID;
+
+ X86PostLegalizerCombiner(bool IsOptNone = false);
+
+ StringRef getPassName() const override { return "X86PostLegalizerCombiner"; }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+private:
+ bool IsOptNone;
+ X86PostLegalizerCombinerImplRuleConfig RuleConfig;
+};
+} // end anonymous namespace
+
+void X86PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<TargetPassConfig>();
+ AU.setPreservesCFG();
+ getSelectionDAGFallbackAnalysisUsage(AU);
+ AU.addRequired<GISelValueTrackingAnalysisLegacy>();
+ AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
+ if (!IsOptNone) {
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<GISelCSEAnalysisWrapperPass>();
+ AU.addPreserved<GISelCSEAnalysisWrapperPass>();
+ }
+ MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+X86PostLegalizerCombiner::X86PostLegalizerCombiner(bool IsOptNone)
+ : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
+ if (!RuleConfig.parseCommandLineOption())
+ report_fatal_error("Invalid rule identifier");
+}
+
+bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
+ if (MF.getProperties().hasFailedISel())
+ return false;
+ assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
+ auto *TPC = &getAnalysis<TargetPassConfig>();
+ const Function &F = MF.getFunction();
+ bool EnableOpt =
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
+
+ const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
+ const auto *LI = ST.getLegalizerInfo();
+
+ GISelValueTracking *VT =
+ &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
+ MachineDominatorTree *MDT =
+ IsOptNone ? nullptr
+ : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ GISelCSEAnalysisWrapper &Wrapper =
+ getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+ auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
+
+ CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
+ /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
+ F.hasMinSize());
+ // Disable fixed-point iteration to reduce compile-time
+ CInfo.MaxIterations = 1;
+ CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
+ // Legalizer performs DCE, so a full DCE pass is unnecessary.
+ CInfo.EnableFullDCE = false;
+ X86PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *VT, CSEInfo, RuleConfig,
+ ST, MDT, LI);
+ bool Changed = Impl.combineMachineInstrs();
+ return Changed;
+}
+
+char X86PostLegalizerCombiner::ID = 0;
+INITIALIZE_PASS_BEGIN(X86PostLegalizerCombiner, DEBUG_TYPE,
+ "Combine X86 MachineInstrs after legalization", false,
+ false)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
+INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
+INITIALIZE_PASS_END(X86PostLegalizerCombiner, DEBUG_TYPE,
+ "Combine X86 MachineInstrs after legalization", false,
+ false)
+
+namespace llvm {
+FunctionPass *createX86PostLegalizerCombiner(bool IsOptNone) {
+ return new X86PostLegalizerCombiner(IsOptNone);
+}
+} // end namespace llvm
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 718c5a0c96e49..0587763156627 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -353,6 +353,7 @@ InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
const X86RegisterBankInfo &);
FunctionPass *createX86PreLegalizerCombiner();
+FunctionPass *createX86PostLegalizerCombiner();
FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
class X86LoadValueInjectionRetHardeningPass
@@ -429,6 +430,7 @@ void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &);
void initializeX86TileConfigLegacyPass(PassRegistry &);
void initializeX86WinEHUnwindV2Pass(PassRegistry &);
void initializeX86PreLegalizerCombinerPass(PassRegistry &);
+void initializeX86PostLegalizerCombinerPass(PassRegistry &);
namespace X86AS {
enum : unsigned {
diff --git a/llvm/lib/Target/X86/X86Combine.td b/llvm/lib/Target/X86/X86Combine.td
index 99d1edadc83f1..b6d010c41e25f 100644
--- a/llvm/lib/Target/X86/X86Combine.td
+++ b/llvm/lib/Target/X86/X86Combine.td
@@ -18,3 +18,6 @@ def all_x86combines : GICombineGroup<[identity_combines, reassocs,
def X86PreLegalizerCombiner : GICombiner<"X86PreLegalizerCombinerImpl", [all_x86combines]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
+def X86PostLegalizerCombiner : GICombiner<"X86PostLegalizerCombinerImpl", [redundant_or, constant_fold_fp_ops, identity_combines, copy_prop]> {
+ let CombineAllMethodName = "tryCombineAllImpl";
+}
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 1affb7c9dd16c..30f3ad7a5b47a 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -372,6 +372,7 @@ class X86PassConfig : public TargetPassConfig {
bool addInstSelector() override;
bool addIRTranslator() override;
bool addLegalizeMachineIR() override;
+ void addPreRegBankSelect() override;
bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override;
void addPreLegalizeMachineIR() override;
@@ -471,6 +472,12 @@ bool X86PassConfig::addIRTranslator() {
return false;
}
+void X86PassConfig::addPreRegBankSelect() {
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
+ if (!IsOptNone) {
+ addPass(createX86PostLegalizerCombiner());
+ }
+}
bool X86PassConfig::addLegalizeMachineIR() {
addPass(new Legalizer());
return false;
>From e94b52af9990cbedd965027ab7ea588868c27f85 Mon Sep 17 00:00:00 2001
From: "Attarde, Mahesh" <mahesh.attarde at intel.com>
Date: Tue, 23 Dec 2025 01:12:29 -0800
Subject: [PATCH 2/5] update test
---
llvm/lib/Target/X86/X86.h | 2 +-
llvm/lib/Target/X86/X86TargetMachine.cpp | 2 +-
.../X86/GlobalISel/regbankselect-x87.ll | 13 ++-
llvm/test/CodeGen/X86/exp10-libcall-names.ll | 4 +-
llvm/test/CodeGen/X86/finite-libcalls.ll | 24 ++----
llvm/test/CodeGen/X86/isel-ceil.ll | 4 +-
llvm/test/CodeGen/X86/isel-floor.ll | 4 +-
llvm/test/CodeGen/X86/isel-ftrunc.ll | 4 +-
llvm/test/CodeGen/X86/isel-icmp.ll | 85 +++++++++----------
llvm/test/CodeGen/X86/isel-llvm.acos.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.asin.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.atan.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.atan2.ll | 10 +--
llvm/test/CodeGen/X86/isel-llvm.cos.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.cosh.ll | 4 +-
.../CodeGen/X86/isel-llvm.set.rounding.ll | 25 ++----
llvm/test/CodeGen/X86/isel-llvm.sin.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.sinh.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.tan.ll | 4 +-
llvm/test/CodeGen/X86/isel-llvm.tanh.ll | 4 +-
llvm/test/CodeGen/X86/isel-or.ll | 9 +-
llvm/test/CodeGen/X86/isel-xor.ll | 3 +-
llvm/test/CodeGen/X86/llround-conv.ll | 8 +-
llvm/test/CodeGen/X86/lround-conv-i32.ll | 4 +-
llvm/test/CodeGen/X86/lround-conv-i64.ll | 4 +-
llvm/test/CodeGen/X86/powi.ll | 10 +--
26 files changed, 86 insertions(+), 165 deletions(-)
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 0587763156627..5c56ba3168def 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -353,7 +353,7 @@ InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
const X86RegisterBankInfo &);
FunctionPass *createX86PreLegalizerCombiner();
-FunctionPass *createX86PostLegalizerCombiner();
+FunctionPass *createX86PostLegalizerCombiner(bool);
FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
class X86LoadValueInjectionRetHardeningPass
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 30f3ad7a5b47a..61bb0a72c6ea5 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -475,7 +475,7 @@ bool X86PassConfig::addIRTranslator() {
void X86PassConfig::addPreRegBankSelect() {
bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
if (!IsOptNone) {
- addPass(createX86PostLegalizerCombiner());
+ addPass(createX86PostLegalizerCombiner(IsOptNone));
}
}
bool X86PassConfig::addLegalizeMachineIR() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
index 83c319b073c4a..6c06d505e8231 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
@@ -165,18 +165,17 @@ define void @f5(ptr %a, ptr %b) {
; X86-NEXT: [[LOAD2:%[0-9]+]]:gpr(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.a, align 8)
; X86-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 4
; X86-NEXT: [[PTR_ADD:%[0-9]+]]:gpr(p0) = nuw inbounds G_PTR_ADD [[LOAD]], [[C]](s32)
- ; X86-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY [[PTR_ADD]](p0)
- ; X86-NEXT: [[LOAD3:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.a + 4, basealign 8)
+ ; X86-NEXT: [[LOAD3:%[0-9]+]]:gpr(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %ir.a + 4, basealign 8)
; X86-NEXT: [[MV:%[0-9]+]]:gpr(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; X86-NEXT: [[LOAD4:%[0-9]+]]:gpr(s32) = G_LOAD [[LOAD1]](p0) :: (load (s32) from %ir.b, align 8)
; X86-NEXT: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = nuw inbounds G_PTR_ADD [[LOAD1]], [[C]](s32)
; X86-NEXT: [[LOAD5:%[0-9]+]]:gpr(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from %ir.b + 4, basealign 8)
; X86-NEXT: [[MV1:%[0-9]+]]:gpr(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)
- ; X86-NEXT: [[COPY1:%[0-9]+]]:psr(s64) = COPY [[MV]](s64)
- ; X86-NEXT: [[COPY2:%[0-9]+]]:psr(s64) = COPY [[MV1]](s64)
- ; X86-NEXT: [[FADD:%[0-9]+]]:psr(s64) = G_FADD [[COPY1]], [[COPY2]]
- ; X86-NEXT: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[FADD]](s64)
- ; X86-NEXT: [[UV:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
+ ; X86-NEXT: [[COPY:%[0-9]+]]:psr(s64) = COPY [[MV]](s64)
+ ; X86-NEXT: [[COPY1:%[0-9]+]]:psr(s64) = COPY [[MV1]](s64)
+ ; X86-NEXT: [[FADD:%[0-9]+]]:psr(s64) = G_FADD [[COPY]], [[COPY1]]
+ ; X86-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[FADD]](s64)
+ ; X86-NEXT: [[UV:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
; X86-NEXT: G_STORE [[UV]](s32), [[LOAD]](p0) :: (store (s32) into %ir.a, align 8)
; X86-NEXT: G_STORE [[UV1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.a + 4, basealign 8)
; X86-NEXT: RET 0
diff --git a/llvm/test/CodeGen/X86/exp10-libcall-names.ll b/llvm/test/CodeGen/X86/exp10-libcall-names.ll
index 2688474b2ce5c..614658b2be4c6 100644
--- a/llvm/test/CodeGen/X86/exp10-libcall-names.ll
+++ b/llvm/test/CodeGen/X86/exp10-libcall-names.ll
@@ -58,10 +58,8 @@ define double @test_exp10_f64(double %x) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll exp10
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/finite-libcalls.ll b/llvm/test/CodeGen/X86/finite-libcalls.ll
index ea2695dc96997..acc7ddeb9a886 100644
--- a/llvm/test/CodeGen/X86/finite-libcalls.ll
+++ b/llvm/test/CodeGen/X86/finite-libcalls.ll
@@ -59,10 +59,8 @@ define double @exp_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll exp
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -185,10 +183,8 @@ define double @exp2_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll exp2
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -311,10 +307,8 @@ define double @log_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll log
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -437,10 +431,8 @@ define double @log2_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll log2
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -563,10 +555,8 @@ define double @log10_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll log10
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -697,10 +687,8 @@ define double @pow_f64(double %x) #0 {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: movl $8, %edx
; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
diff --git a/llvm/test/CodeGen/X86/isel-ceil.ll b/llvm/test/CodeGen/X86/isel-ceil.ll
index 21df3f1160003..5721752331b5e 100644
--- a/llvm/test/CodeGen/X86/isel-ceil.ll
+++ b/llvm/test/CodeGen/X86/isel-ceil.ll
@@ -80,10 +80,8 @@ define double @ceil_f64(double %a) nounwind readnone {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll ceil
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-floor.ll b/llvm/test/CodeGen/X86/isel-floor.ll
index 66eeee89169ba..acae9b12ce7fc 100644
--- a/llvm/test/CodeGen/X86/isel-floor.ll
+++ b/llvm/test/CodeGen/X86/isel-floor.ll
@@ -80,10 +80,8 @@ define double @floor_f64(double %a) nounwind readnone {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll floor
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-ftrunc.ll b/llvm/test/CodeGen/X86/isel-ftrunc.ll
index dcdb016d29aca..c2be47ca04567 100644
--- a/llvm/test/CodeGen/X86/isel-ftrunc.ll
+++ b/llvm/test/CodeGen/X86/isel-ftrunc.ll
@@ -80,10 +80,8 @@ define double @trunc_f64(double %a) nounwind readnone {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll trunc
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-icmp.ll b/llvm/test/CodeGen/X86/isel-icmp.ll
index 065d701bab1fd..ce4aba5d14e4d 100644
--- a/llvm/test/CodeGen/X86/isel-icmp.ll
+++ b/llvm/test/CodeGen/X86/isel-icmp.ll
@@ -747,38 +747,36 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind {
;
; GISEL-X64-LABEL: test_icmp_sge_i96:
; GISEL-X64: ## %bb.0:
-; GISEL-X64-NEXT: movq %rcx, %rax
-; GISEL-X64-NEXT: movq %rdi, %r8
-; GISEL-X64-NEXT: movb $32, %cl
-; GISEL-X64-NEXT: shlq %cl, %r8
-; GISEL-X64-NEXT: shlq %cl, %rsi
-; GISEL-X64-NEXT: shrq %cl, %rdi
+; GISEL-X64-NEXT: movq %rdi, %rax
+; GISEL-X64-NEXT: shlq $32, %rax
+; GISEL-X64-NEXT: shlq $32, %rsi
+; GISEL-X64-NEXT: shrq $32, %rdi
; GISEL-X64-NEXT: orq %rsi, %rdi
-; GISEL-X64-NEXT: shrq %cl, %r8
+; GISEL-X64-NEXT: shrq $32, %rax
; GISEL-X64-NEXT: movq %rdi, %rsi
-; GISEL-X64-NEXT: shlq %cl, %rsi
-; GISEL-X64-NEXT: orq %r8, %rsi
-; GISEL-X64-NEXT: sarq %cl, %rdi
-; GISEL-X64-NEXT: movq %rdx, %rcx
-; GISEL-X64-NEXT: shlq $32, %rcx
-; GISEL-X64-NEXT: shlq $32, %rax
-; GISEL-X64-NEXT: shrq $32, %rdx
-; GISEL-X64-NEXT: orq %rax, %rdx
-; GISEL-X64-NEXT: shrq $32, %rcx
+; GISEL-X64-NEXT: shlq $32, %rsi
+; GISEL-X64-NEXT: orq %rax, %rsi
+; GISEL-X64-NEXT: sarq $32, %rdi
; GISEL-X64-NEXT: movq %rdx, %rax
; GISEL-X64-NEXT: shlq $32, %rax
-; GISEL-X64-NEXT: orq %rcx, %rax
+; GISEL-X64-NEXT: shlq $32, %rcx
+; GISEL-X64-NEXT: shrq $32, %rdx
+; GISEL-X64-NEXT: orq %rcx, %rdx
+; GISEL-X64-NEXT: shrq $32, %rax
+; GISEL-X64-NEXT: movq %rdx, %rcx
+; GISEL-X64-NEXT: shlq $32, %rcx
+; GISEL-X64-NEXT: orq %rax, %rcx
; GISEL-X64-NEXT: sarq $32, %rdx
-; GISEL-X64-NEXT: xorl %ecx, %ecx
-; GISEL-X64-NEXT: cmpq %rax, %rsi
-; GISEL-X64-NEXT: setae %cl
+; GISEL-X64-NEXT: xorl %r8d, %r8d
+; GISEL-X64-NEXT: cmpq %rcx, %rsi
+; GISEL-X64-NEXT: setae %r8b
; GISEL-X64-NEXT: xorl %eax, %eax
-; GISEL-X64-NEXT: xorl %esi, %esi
+; GISEL-X64-NEXT: xorl %ecx, %ecx
; GISEL-X64-NEXT: cmpq %rdx, %rdi
; GISEL-X64-NEXT: setge %al
-; GISEL-X64-NEXT: sete %sil
-; GISEL-X64-NEXT: testl %esi, %esi
-; GISEL-X64-NEXT: cmovnew %cx, %ax
+; GISEL-X64-NEXT: sete %cl
+; GISEL-X64-NEXT: testl %ecx, %ecx
+; GISEL-X64-NEXT: cmovnew %r8w, %ax
; GISEL-X64-NEXT: andl $1, %eax
; GISEL-X64-NEXT: retq
;
@@ -833,21 +831,17 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind {
;
; GISEL-X86-LABEL: test_icmp_sge_i96:
; GISEL-X86: ## %bb.0:
-; GISEL-X86-NEXT: pushl %ebp
; GISEL-X86-NEXT: pushl %ebx
; GISEL-X86-NEXT: pushl %edi
; GISEL-X86-NEXT: pushl %esi
-; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edi
-; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; GISEL-X86-NEXT: movl %edx, %eax
-; GISEL-X86-NEXT: movb $31, %cl
-; GISEL-X86-NEXT: sarl %cl, %eax
-; GISEL-X86-NEXT: cmpl %edi, {{[0-9]+}}(%esp)
+; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT: cmpl %ecx, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: setae %ch
; GISEL-X86-NEXT: xorl %ebx, %ebx
-; GISEL-X86-NEXT: cmpl %ebp, {{[0-9]+}}(%esp)
+; GISEL-X86-NEXT: cmpl %esi, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: setae %cl
; GISEL-X86-NEXT: sete %bl
; GISEL-X86-NEXT: testl %ebx, %ebx
@@ -855,32 +849,33 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind {
; GISEL-X86-NEXT: ## %bb.1:
; GISEL-X86-NEXT: movb %ch, %cl
; GISEL-X86-NEXT: LBB13_2:
-; GISEL-X86-NEXT: movl %esi, %edi
+; GISEL-X86-NEXT: movl %eax, %esi
+; GISEL-X86-NEXT: sarl $31, %esi
+; GISEL-X86-NEXT: movl %edx, %edi
; GISEL-X86-NEXT: sarl $31, %edi
; GISEL-X86-NEXT: xorl %ebx, %ebx
-; GISEL-X86-NEXT: cmpl %esi, %edx
-; GISEL-X86-NEXT: setae %dl
+; GISEL-X86-NEXT: cmpl %edx, %eax
+; GISEL-X86-NEXT: setae %al
; GISEL-X86-NEXT: sete %bl
; GISEL-X86-NEXT: testl %ebx, %ebx
; GISEL-X86-NEXT: je LBB13_4
; GISEL-X86-NEXT: ## %bb.3:
-; GISEL-X86-NEXT: movl %ecx, %edx
+; GISEL-X86-NEXT: movl %ecx, %eax
; GISEL-X86-NEXT: LBB13_4:
-; GISEL-X86-NEXT: xorl %ecx, %ecx
-; GISEL-X86-NEXT: cmpl %edi, %eax
-; GISEL-X86-NEXT: setge %al
-; GISEL-X86-NEXT: sete %cl
-; GISEL-X86-NEXT: testl %ecx, %ecx
+; GISEL-X86-NEXT: xorl %edx, %edx
+; GISEL-X86-NEXT: cmpl %edi, %esi
+; GISEL-X86-NEXT: setge %cl
+; GISEL-X86-NEXT: sete %dl
+; GISEL-X86-NEXT: testl %edx, %edx
; GISEL-X86-NEXT: je LBB13_6
; GISEL-X86-NEXT: ## %bb.5:
-; GISEL-X86-NEXT: movl %edx, %eax
+; GISEL-X86-NEXT: movl %eax, %ecx
; GISEL-X86-NEXT: LBB13_6:
-; GISEL-X86-NEXT: movzbl %al, %eax
+; GISEL-X86-NEXT: movzbl %cl, %eax
; GISEL-X86-NEXT: andl $1, %eax
; GISEL-X86-NEXT: popl %esi
; GISEL-X86-NEXT: popl %edi
; GISEL-X86-NEXT: popl %ebx
-; GISEL-X86-NEXT: popl %ebp
; GISEL-X86-NEXT: retl
%r = icmp sge i96 %a, %b
%res = zext i1 %r to i32
diff --git a/llvm/test/CodeGen/X86/isel-llvm.acos.ll b/llvm/test/CodeGen/X86/isel-llvm.acos.ll
index 9176cf47bda78..9fc63ffeed8d5 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.acos.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.acos.ll
@@ -57,10 +57,8 @@ define double @use_acosf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll acos
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.asin.ll b/llvm/test/CodeGen/X86/isel-llvm.asin.ll
index 87ffcc9c963c2..111303b0e9058 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.asin.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.asin.ll
@@ -57,10 +57,8 @@ define double @use_asinf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll asin
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.atan.ll b/llvm/test/CodeGen/X86/isel-llvm.atan.ll
index c03361d18c1d2..910b58393e186 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.atan.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.atan.ll
@@ -57,10 +57,8 @@ define double @use_atanf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll atan
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.atan2.ll b/llvm/test/CodeGen/X86/isel-llvm.atan2.ll
index aa56068e17780..2f43cd001b122 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.atan2.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.atan2.ll
@@ -59,27 +59,23 @@ define double @use_atan2f64(double %a, double %b) nounwind {
;
; GISEL-X86-LABEL: use_atan2f64:
; GISEL-X86: # %bb.0:
-; GISEL-X86-NEXT: pushl %edi
; GISEL-X86-NEXT: pushl %esi
-; GISEL-X86-NEXT: subl $20, %esp
+; GISEL-X86-NEXT: subl $24, %esp
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; GISEL-X86-NEXT: movl 4(%edx), %edx
-; GISEL-X86-NEXT: xorl %edi, %edi
-; GISEL-X86-NEXT: addl %esp, %edi
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edi)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: movl $8, %eax
; GISEL-X86-NEXT: addl %esp, %eax
; GISEL-X86-NEXT: movl %esi, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: movl %edx, 4(%eax)
; GISEL-X86-NEXT: calll atan2
-; GISEL-X86-NEXT: addl $20, %esp
+; GISEL-X86-NEXT: addl $24, %esp
; GISEL-X86-NEXT: popl %esi
-; GISEL-X86-NEXT: popl %edi
; GISEL-X86-NEXT: retl
;
; GISEL-X64-LABEL: use_atan2f64:
diff --git a/llvm/test/CodeGen/X86/isel-llvm.cos.ll b/llvm/test/CodeGen/X86/isel-llvm.cos.ll
index af039854d3491..0abaaec87699f 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.cos.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.cos.ll
@@ -57,10 +57,8 @@ define double @test_cos_f64(double %Val) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll cos
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.cosh.ll b/llvm/test/CodeGen/X86/isel-llvm.cosh.ll
index a61867c11fd41..c665f84bf1377 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.cosh.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.cosh.ll
@@ -57,10 +57,8 @@ define double @use_coshf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll cosh
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
index d271e97d8832a..859c6d1965b68 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
@@ -117,10 +117,7 @@ define void @func_02() nounwind {
; GISEL-X86-NOSSE: # %bb.0:
; GISEL-X86-NOSSE-NEXT: pushl %eax
; GISEL-X86-NOSSE-NEXT: fnstcw (%esp)
-; GISEL-X86-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
-; GISEL-X86-NOSSE-NEXT: andw (%esp), %ax
-; GISEL-X86-NOSSE-NEXT: orw $0, %ax
-; GISEL-X86-NOSSE-NEXT: movw %ax, (%esp)
+; GISEL-X86-NOSSE-NEXT: andw $-3073, (%esp) # imm = 0xF3FF
; GISEL-X86-NOSSE-NEXT: fldcw (%esp)
; GISEL-X86-NOSSE-NEXT: popl %eax
; GISEL-X86-NOSSE-NEXT: retl
@@ -135,10 +132,7 @@ define void @func_02() nounwind {
; GISEL-X64-NOSSE-LABEL: func_02:
; GISEL-X64-NOSSE: # %bb.0:
; GISEL-X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp)
-; GISEL-X64-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
-; GISEL-X64-NOSSE-NEXT: andw -{{[0-9]+}}(%rsp), %ax
-; GISEL-X64-NOSSE-NEXT: orw $0, %ax
-; GISEL-X64-NOSSE-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: andw $-3073, -{{[0-9]+}}(%rsp) # imm = 0xF3FF
; GISEL-X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp)
; GISEL-X64-NOSSE-NEXT: retq
;
@@ -155,10 +149,7 @@ define void @func_02() nounwind {
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: pushl %eax
; GISEL-X86-NEXT: fnstcw (%esp)
-; GISEL-X86-NEXT: movw $-3073, %ax # imm = 0xF3FF
-; GISEL-X86-NEXT: andw (%esp), %ax
-; GISEL-X86-NEXT: orw $0, %ax
-; GISEL-X86-NEXT: movw %ax, (%esp)
+; GISEL-X86-NEXT: andw $-3073, (%esp) # imm = 0xF3FF
; GISEL-X86-NEXT: fldcw (%esp)
; GISEL-X86-NEXT: popl %eax
; GISEL-X86-NEXT: retl
@@ -176,16 +167,10 @@ define void @func_02() nounwind {
; GISEL-X64-LABEL: func_02:
; GISEL-X64: # %bb.0:
; GISEL-X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
-; GISEL-X64-NEXT: movw $-3073, %ax # imm = 0xF3FF
-; GISEL-X64-NEXT: andw -{{[0-9]+}}(%rsp), %ax
-; GISEL-X64-NEXT: orw $0, %ax
-; GISEL-X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: andw $-3073, -{{[0-9]+}}(%rsp) # imm = 0xF3FF
; GISEL-X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; GISEL-X64-NEXT: stmxcsr -{{[0-9]+}}(%rsp)
-; GISEL-X64-NEXT: movl $-24577, %eax # imm = 0x9FFF
-; GISEL-X64-NEXT: andl -{{[0-9]+}}(%rsp), %eax
-; GISEL-X64-NEXT: orl $0, %eax
-; GISEL-X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: andl $-24577, -{{[0-9]+}}(%rsp) # imm = 0x9FFF
; GISEL-X64-NEXT: ldmxcsr -{{[0-9]+}}(%rsp)
; GISEL-X64-NEXT: retq
call void @llvm.set.rounding(i32 1) ; ToNearestTiesToEven (CW[11-10] = 00)
diff --git a/llvm/test/CodeGen/X86/isel-llvm.sin.ll b/llvm/test/CodeGen/X86/isel-llvm.sin.ll
index 0f17f83d01023..559a104863928 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.sin.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.sin.ll
@@ -57,10 +57,8 @@ define double @test_sin_f64(double %Val) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll sin
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.sinh.ll b/llvm/test/CodeGen/X86/isel-llvm.sinh.ll
index ef30f8de06953..6bd7cfbb301cb 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.sinh.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.sinh.ll
@@ -57,10 +57,8 @@ define double @use_sinhf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll sinh
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.tan.ll b/llvm/test/CodeGen/X86/isel-llvm.tan.ll
index 4e76653cd1299..4b51d208bfadd 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.tan.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.tan.ll
@@ -57,10 +57,8 @@ define double @use_tanf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll tan
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-llvm.tanh.ll b/llvm/test/CodeGen/X86/isel-llvm.tanh.ll
index c4f6e2f179cf9..29a7cbfb99af5 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.tanh.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.tanh.ll
@@ -57,10 +57,8 @@ define double @use_tanhf64(double %a) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll tanh
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/isel-or.ll b/llvm/test/CodeGen/X86/isel-or.ll
index 449f29a027743..8b191c007675c 100644
--- a/llvm/test/CodeGen/X86/isel-or.ll
+++ b/llvm/test/CodeGen/X86/isel-or.ll
@@ -335,10 +335,9 @@ define i64 @or_imm8_i64(i64 %a) {
;
; GISEL-X86-LABEL: or_imm8_i64:
; GISEL-X86: # %bb.0:
+; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: movl $1, %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
-; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm8_i64:
@@ -441,9 +440,8 @@ define i64 @or_imm16_i64(i64 %a) {
; GISEL-X86-LABEL: or_imm16_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-5022, %eax # imm = 0xEC62
-; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
-; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm16_i64:
@@ -501,9 +499,8 @@ define i64 @or_imm32_i64(i64 %a) {
; GISEL-X86-LABEL: or_imm32_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-125778, %eax # imm = 0xFFFE14AE
-; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
-; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm32_i64:
diff --git a/llvm/test/CodeGen/X86/isel-xor.ll b/llvm/test/CodeGen/X86/isel-xor.ll
index a31ad78524ee1..0549a6436a1a4 100644
--- a/llvm/test/CodeGen/X86/isel-xor.ll
+++ b/llvm/test/CodeGen/X86/isel-xor.ll
@@ -335,10 +335,9 @@ define i64 @xor_imm8_i64(i64 %a) {
;
; GISEL-X86-LABEL: xor_imm8_i64:
; GISEL-X86: # %bb.0:
+; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: movl $1, %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
-; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm8_i64:
diff --git a/llvm/test/CodeGen/X86/llround-conv.ll b/llvm/test/CodeGen/X86/llround-conv.ll
index 83151ebf9af07..93fec71b6eccc 100644
--- a/llvm/test/CodeGen/X86/llround-conv.ll
+++ b/llvm/test/CodeGen/X86/llround-conv.ll
@@ -133,10 +133,8 @@ define i64 @test_llround_f64(double %x) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll llround
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
@@ -363,10 +361,8 @@ define i64 @test_llround_i64_f64(double %x) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll llround
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/lround-conv-i32.ll b/llvm/test/CodeGen/X86/lround-conv-i32.ll
index 73abbee86880f..4e95da14b45a1 100644
--- a/llvm/test/CodeGen/X86/lround-conv-i32.ll
+++ b/llvm/test/CodeGen/X86/lround-conv-i32.ll
@@ -112,10 +112,8 @@ define i32 @test_lround_i32_f64(double %x) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll lround
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/lround-conv-i64.ll b/llvm/test/CodeGen/X86/lround-conv-i64.ll
index 81f01cc27eb14..0002bb8936d5d 100644
--- a/llvm/test/CodeGen/X86/lround-conv-i64.ll
+++ b/llvm/test/CodeGen/X86/lround-conv-i64.ll
@@ -135,10 +135,8 @@ define i64 @test_lround_i64_f64(double %x) nounwind {
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
-; GISEL-X86-NEXT: xorl %edx, %edx
-; GISEL-X86-NEXT: addl %esp, %edx
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%edx)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll lround
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/powi.ll b/llvm/test/CodeGen/X86/powi.ll
index 4420d0499a5d0..9446cc071c1fc 100644
--- a/llvm/test/CodeGen/X86/powi.ll
+++ b/llvm/test/CodeGen/X86/powi.ll
@@ -86,20 +86,16 @@ define double @test_powi_f64_i32(double %Val, i32 %x) nounwind {
;
; GISEL-X86-LABEL: test_powi_f64_i32:
; GISEL-X86: # %bb.0:
-; GISEL-X86-NEXT: pushl %esi
-; GISEL-X86-NEXT: subl $24, %esp
+; GISEL-X86-NEXT: subl $12, %esp
; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl 4(%eax), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; GISEL-X86-NEXT: xorl %esi, %esi
-; GISEL-X86-NEXT: addl %esp, %esi
; GISEL-X86-NEXT: movl %ecx, (%esp)
-; GISEL-X86-NEXT: movl %eax, 4(%esi)
+; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
; GISEL-X86-NEXT: calll __powidf2
-; GISEL-X86-NEXT: addl $24, %esp
-; GISEL-X86-NEXT: popl %esi
+; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl
;
; FAST-X64-LABEL: test_powi_f64_i32:
>From 2eaaad906870c47764bf4daf041c90b1c572cce9 Mon Sep 17 00:00:00 2001
From: "Attarde, Mahesh" <mahesh.attarde at intel.com>
Date: Tue, 23 Dec 2025 01:32:33 -0800
Subject: [PATCH 3/5] update optnonoe
---
.../X86/GISel/X86PostLegalizerCombiner.cpp | 31 +++++++------------
llvm/lib/Target/X86/X86.h | 3 +-
llvm/lib/Target/X86/X86TargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
index 8032ba9cdcd12..59953d32152fc 100644
--- a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
@@ -99,18 +99,14 @@ X86PostLegalizerCombinerImpl::X86PostLegalizerCombinerImpl(
}
bool X86PostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
- if (tryCombineAllImpl(MI))
- return true;
- LLVM_DEBUG(dbgs() << "\nNo table match found.\nTry Custom Combine for "
- << MI);
- return false;
+ return tryCombineAllImpl(MI);
}
class X86PostLegalizerCombiner : public MachineFunctionPass {
public:
static char ID;
- X86PostLegalizerCombiner(bool IsOptNone = false);
+ X86PostLegalizerCombiner();
StringRef getPassName() const override { return "X86PostLegalizerCombiner"; }
@@ -118,7 +114,6 @@ class X86PostLegalizerCombiner : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override;
private:
- bool IsOptNone;
X86PostLegalizerCombinerImplRuleConfig RuleConfig;
};
} // end anonymous namespace
@@ -129,17 +124,16 @@ void X86PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
getSelectionDAGFallbackAnalysisUsage(AU);
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
- if (!IsOptNone) {
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addPreserved<MachineDominatorTreeWrapperPass>();
- AU.addRequired<GISelCSEAnalysisWrapperPass>();
- AU.addPreserved<GISelCSEAnalysisWrapperPass>();
- }
+ // This is only added when processing level is not OptNone.
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<GISelCSEAnalysisWrapperPass>();
+ AU.addPreserved<GISelCSEAnalysisWrapperPass>();
+
MachineFunctionPass::getAnalysisUsage(AU);
}
-X86PostLegalizerCombiner::X86PostLegalizerCombiner(bool IsOptNone)
- : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
+X86PostLegalizerCombiner::X86PostLegalizerCombiner() : MachineFunctionPass(ID) {
if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -159,8 +153,7 @@ bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
GISelValueTracking *VT =
&getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
MachineDominatorTree *MDT =
- IsOptNone ? nullptr
- : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
GISelCSEAnalysisWrapper &Wrapper =
getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
@@ -190,7 +183,7 @@ INITIALIZE_PASS_END(X86PostLegalizerCombiner, DEBUG_TYPE,
false)
namespace llvm {
-FunctionPass *createX86PostLegalizerCombiner(bool IsOptNone) {
- return new X86PostLegalizerCombiner(IsOptNone);
+FunctionPass *createX86PostLegalizerCombiner() {
+ return new X86PostLegalizerCombiner();
}
} // end namespace llvm
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 5c56ba3168def..c2ffcca716eb5 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -352,8 +352,7 @@ InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
const X86Subtarget &,
const X86RegisterBankInfo &);
-FunctionPass *createX86PreLegalizerCombiner();
-FunctionPass *createX86PostLegalizerCombiner(bool);
+FunctionPass *createX86PostLegalizerCombiner();
FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
class X86LoadValueInjectionRetHardeningPass
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 61bb0a72c6ea5..30f3ad7a5b47a 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -475,7 +475,7 @@ bool X86PassConfig::addIRTranslator() {
void X86PassConfig::addPreRegBankSelect() {
bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
if (!IsOptNone) {
- addPass(createX86PostLegalizerCombiner(IsOptNone));
+ addPass(createX86PostLegalizerCombiner());
}
}
bool X86PassConfig::addLegalizeMachineIR() {
>From 11ca3d92c15d6ef7c68a33dd0a89b5ee5d0c4a8c Mon Sep 17 00:00:00 2001
From: "Attarde, Mahesh" <mahesh.attarde at intel.com>
Date: Mon, 5 Jan 2026 22:49:29 -0800
Subject: [PATCH 4/5] fix merge error
---
llvm/lib/Target/X86/X86.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index c2ffcca716eb5..bad2a6d79d753 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -353,6 +353,7 @@ InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
const X86RegisterBankInfo &);
FunctionPass *createX86PostLegalizerCombiner();
+FunctionPass *createX86PreLegalizerCombiner();
FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
class X86LoadValueInjectionRetHardeningPass
>From 906c34469716caca4e5926da5ee0fea8895e6146 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Wed, 28 Jan 2026 20:36:21 -0800
Subject: [PATCH 5/5] update review comemnts
---
.../X86/GISel/X86PostLegalizerCombiner.cpp | 18 +++----
llvm/test/CodeGen/X86/GlobalISel/add-ext.ll | 32 +++++------
llvm/test/CodeGen/X86/isel-fpclass.ll | 53 +++++--------------
3 files changed, 36 insertions(+), 67 deletions(-)
diff --git a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
index 59953d32152fc..373d46d1b53a9 100644
--- a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
@@ -1,4 +1,4 @@
-//=== X86PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
+//===--------------- X86PostLegalizerCombiner.cpp ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -90,7 +90,7 @@ X86PostLegalizerCombinerImpl::X86PostLegalizerCombinerImpl(
const X86PostLegalizerCombinerImplRuleConfig &RuleConfig,
const X86Subtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI)
: Combiner(MF, CInfo, TPC, &VT, CSEInfo),
- Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI),
+ Helper(Observer, B, /*IsPreLegalize=*/false, &VT, MDT, LI),
RuleConfig(RuleConfig), STI(STI),
#define GET_GICOMBINER_CONSTRUCTOR_INITS
#include "X86GenPostLegalizeGICombiner.inc"
@@ -135,7 +135,7 @@ void X86PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
X86PostLegalizerCombiner::X86PostLegalizerCombiner() : MachineFunctionPass(ID) {
if (!RuleConfig.parseCommandLineOption())
- report_fatal_error("Invalid rule identifier");
+ reportFatalInternalError("Invalid rule identifier");
}
bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
@@ -144,8 +144,6 @@ bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
const auto *LI = ST.getLegalizerInfo();
@@ -158,9 +156,10 @@ bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
- CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
- /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
- F.hasMinSize());
+ CombinerInfo CInfo(/*AllowIllegalOps=*/true,
+ /*ShouldLegalizeIllegal=*/false,
+ /*LegalizerInfo=*/nullptr, !skipFunction(F),
+ F.hasOptSize(), F.hasMinSize());
// Disable fixed-point iteration to reduce compile-time
CInfo.MaxIterations = 1;
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
@@ -168,8 +167,7 @@ bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
CInfo.EnableFullDCE = false;
X86PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *VT, CSEInfo, RuleConfig,
ST, MDT, LI);
- bool Changed = Impl.combineMachineInstrs();
- return Changed;
+ return Impl.combineMachineInstrs();
}
char X86PostLegalizerCombiner::ID = 0;
diff --git a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
index fb4b98ac38957..8146252235b00 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
@@ -162,17 +162,15 @@ define void @PR20134(ptr %a, i32 %i) {
; CHECK-NEXT: shlq $2, %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: leal 2(%rsi), %ecx
-; CHECK-NEXT: movslq %ecx, %rdx
-; CHECK-NEXT: movb $2, %cl
-; CHECK-NEXT: shlq %cl, %rdx
-; CHECK-NEXT: leaq (%rdi,%rdx), %rcx
-; CHECK-NEXT: movl (%rcx), %edx
-; CHECK-NEXT: addl (%rax), %edx
+; CHECK-NEXT: movslq %ecx, %rcx
+; CHECK-NEXT: shlq $2, %rcx
+; CHECK-NEXT: addq %rdi, %rcx
+; CHECK-NEXT: movl (%rcx), %ecx
+; CHECK-NEXT: addl (%rax), %ecx
; CHECK-NEXT: movslq %esi, %rax
-; CHECK-NEXT: movb $2, %cl
-; CHECK-NEXT: shlq %cl, %rax
+; CHECK-NEXT: shlq $2, %rax
; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: movl %edx, (%rax)
+; CHECK-NEXT: movl %ecx, (%rax)
; CHECK-NEXT: retq
%add1 = add nsw i32 %i, 1
@@ -202,17 +200,15 @@ define void @PR20134_zext(ptr %a, i32 %i) {
; CHECK-NEXT: shlq $2, %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: leal 2(%rsi), %ecx
-; CHECK-NEXT: movl %ecx, %edx
-; CHECK-NEXT: movb $2, %cl
-; CHECK-NEXT: shlq %cl, %rdx
-; CHECK-NEXT: leaq (%rdi,%rdx), %rcx
-; CHECK-NEXT: movl (%rcx), %edx
-; CHECK-NEXT: addl (%rax), %edx
+; CHECK-NEXT: movl %ecx, %ecx
+; CHECK-NEXT: shlq $2, %rcx
+; CHECK-NEXT: addq %rdi, %rcx
+; CHECK-NEXT: movl (%rcx), %ecx
+; CHECK-NEXT: addl (%rax), %ecx
; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: movb $2, %cl
-; CHECK-NEXT: shlq %cl, %rax
+; CHECK-NEXT: shlq $2, %rax
; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: movl %edx, (%rax)
+; CHECK-NEXT: movl %ecx, (%rax)
; CHECK-NEXT: retq
%add1 = add nuw i32 %i, 1
diff --git a/llvm/test/CodeGen/X86/isel-fpclass.ll b/llvm/test/CodeGen/X86/isel-fpclass.ll
index 3a3939fef0f09..0393ae602fd10 100644
--- a/llvm/test/CodeGen/X86/isel-fpclass.ll
+++ b/llvm/test/CodeGen/X86/isel-fpclass.ll
@@ -102,13 +102,11 @@ define i1 @issignaling_f(float %x) nounwind {
; X64-GISEL: # %bb.0:
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: seta %dl
+; X64-GISEL-NEXT: seta %cl
; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-GISEL-NEXT: setb %al
-; X64-GISEL-NEXT: andb %dl, %al
-; X64-GISEL-NEXT: orb %cl, %al
+; X64-GISEL-NEXT: andb %cl, %al
; X64-GISEL-NEXT: retq
%a0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan"
ret i1 %a0
@@ -147,10 +145,8 @@ define i1 @issignaling_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-GISEL-NEXT: setae %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan"
@@ -190,19 +186,16 @@ define i1 @not_isquiet_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: setb %dl
+; X64-GISEL-NEXT: setb %cl
+; X64-GISEL-NEXT: sete %dl
; X64-GISEL-NEXT: orb %cl, %dl
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: sete %cl
-; X64-GISEL-NEXT: orb %dl, %cl
-; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: seta %dl
+; X64-GISEL-NEXT: seta %cl
; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-GISEL-NEXT: setb %al
-; X64-GISEL-NEXT: andb %dl, %al
-; X64-GISEL-NEXT: orb %cl, %al
+; X64-GISEL-NEXT: andb %cl, %al
+; X64-GISEL-NEXT: orb %dl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1021) ; ~"qnan"
@@ -242,10 +235,8 @@ define i1 @isinf_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GISEL-NEXT: sete %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
@@ -285,13 +276,10 @@ define i1 @not_isinf_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
-; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: setb %dl
-; X64-GISEL-NEXT: orb %cl, %dl
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GISEL-NEXT: setb %cl
; X64-GISEL-NEXT: seta %al
-; X64-GISEL-NEXT: orb %dl, %al
+; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; ~0x204 = "~inf"
@@ -324,11 +312,9 @@ define i1 @is_plus_inf_f(float %x) nounwind {
;
; X64-GISEL-LABEL: is_plus_inf_f:
; X64-GISEL: # %bb.0: # %entry
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GISEL-NEXT: sete %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
@@ -361,11 +347,9 @@ define i1 @is_minus_inf_f(float %x) nounwind {
;
; X64-GISEL-LABEL: is_minus_inf_f:
; X64-GISEL: # %bb.0: # %entry
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X64-GISEL-NEXT: sete %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
@@ -401,15 +385,13 @@ define i1 @not_is_minus_inf_f(float %x) nounwind {
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: movl %eax, %ecx
; X64-GISEL-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %edx, %edx
; X64-GISEL-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-GISEL-NEXT: setb %sil
-; X64-GISEL-NEXT: orb %dl, %sil
+; X64-GISEL-NEXT: setb %dl
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: sete %dl
+; X64-GISEL-NEXT: sete %sil
+; X64-GISEL-NEXT: orb %dl, %sil
; X64-GISEL-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
; X64-GISEL-NEXT: seta %al
-; X64-GISEL-NEXT: orb %dl, %al
; X64-GISEL-NEXT: orb %sil, %al
; X64-GISEL-NEXT: retq
entry:
@@ -450,10 +432,8 @@ define i1 @isfinite_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GISEL-NEXT: setb %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
@@ -493,13 +473,10 @@ define i1 @not_isfinite_f(float %x) nounwind {
; X64-GISEL: # %bb.0: # %entry
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GISEL-NEXT: xorl %ecx, %ecx
-; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GISEL-NEXT: sete %dl
-; X64-GISEL-NEXT: orb %cl, %dl
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GISEL-NEXT: sete %cl
; X64-GISEL-NEXT: seta %al
-; X64-GISEL-NEXT: orb %dl, %al
+; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
@@ -532,11 +509,9 @@ define i1 @is_plus_finite_f(float %x) nounwind {
;
; X64-GISEL-LABEL: is_plus_finite_f:
; X64-GISEL: # %bb.0: # %entry
-; X64-GISEL-NEXT: xorl %ecx, %ecx
; X64-GISEL-NEXT: movd %xmm0, %eax
; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GISEL-NEXT: setb %al
-; X64-GISEL-NEXT: orb %cl, %al
; X64-GISEL-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
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