[llvm] 4ea1791 - [X86] Truncate unused bit for blendw mask (#178883)

[via llvm-commits]

Author: Mahesh-Attarde
Date: 2026-01-30T17:20:30Z
New Revision: 4ea1791890b800aeeb0228f6cc64fd0b6e4ee803

URL: https://github.com/llvm/llvm-project/commit/4ea1791890b800aeeb0228f6cc64fd0b6e4ee803
DIFF: https://github.com/llvm/llvm-project/commit/4ea1791890b800aeeb0228f6cc64fd0b6e4ee803.diff

LOG: [X86] Truncate unused bit for blendw mask (#178883)

While tuning ProcessBLENDWToBLENDD 

https://github.com/mahesh-attarde/llvm-project/blob/07ec2fa1443ccd3cbb55612937f1dddebfe51c15/llvm/lib/Target/X86/X86FixupInstTuning.cpp#L262
we creating mask from `getImm()` which returns 64bit int and APInt
accept 64 bit int.
```
    APInt MaskW =
        APInt(8, MI.getOperand(NumOperands - 1).getImm(), /*IsSigned=*/false);
```
It fails with MIR for BLENDW instruction that requires8 bit mask 0xAA
from 64 bit Imm.
```
  renamable $xmm2 = VPBLENDWrri renamable $xmm1, killed renamable $xmm2, -86
```
APInt construction complains since higher bits of are also set for
transformations where mask bits are set (results in negative values).

https://github.com/mahesh-attarde/llvm-project/blob/07ec2fa1443ccd3cbb55612937f1dddebfe51c15/llvm/include/llvm/ADT/APInt.h#L125

This patch uses implictTruncate from APInt constructor to get around.

other approach could have been using direct mask(same effect as implicit
truncate) `AND` with Imm or use signed version (not applicable since
mask).

This case was generate using bisect so most of test excercises, i tried
with VPBLEND generating IR refuse to generate mask in range 0b10101010,
so patch lacks test.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86FixupInstTuning.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index 4747977e3f43b..af3c3af38e681 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -260,7 +260,8 @@ bool X86FixupInstTuningImpl::processInstruction(
       return false;
     // Convert to VPBLENDD if scaling the VPBLENDW mask down/up loses no bits.
     APInt MaskW =
-        APInt(8, MI.getOperand(NumOperands - 1).getImm(), /*IsSigned=*/false);
+        APInt(8, MI.getOperand(NumOperands - 1).getImm(), /*IsSigned=*/false,
+              /*implicitTrunc=*/true);
     APInt MaskD = APIntOps::ScaleBitMask(MaskW, 4, /*MatchAllBits=*/true);
     if (MaskW != APIntOps::ScaleBitMask(MaskD, 8, /*MatchAllBits=*/true))
       return false;