[llvm] [SDAG] Check for `nsz` in DAG.canIgnoreSignBitOfZero() (PR #178905)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 30 08:38:46 PST 2026
https://github.com/MacDue updated https://github.com/llvm/llvm-project/pull/178905
>From 789c9152812f576e98a212be60a0dcddb1622f82 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Fri, 30 Jan 2026 15:18:08 +0000
Subject: [PATCH 1/2] [SDAG] Check for `nsz` in DAG.canIgnoreSignBitOfZero()
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 3 ++-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +++++---------
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +++++
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 +--
llvm/test/CodeGen/AArch64/sve-bf16-combines.ll | 16 ++++++++--------
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index a208481df0c70..eed3769882545 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2365,7 +2365,8 @@ class SelectionDAG {
/// Check if a use of a float value is insensitive to signed zeros.
LLVM_ABI bool canIgnoreSignBitOfZero(const SDUse &Use) const;
- /// Check if at most two uses of a value are insensitive to signed zeros.
+ /// Check if \p Op has no-signed-zeros, or all users (limited to checking two
+ /// for compile-time performance) are insensitive to signed zeros.
LLVM_ABI bool canIgnoreSignBitOfZero(SDValue Op) const;
/// Test whether two SDValues are known to compare equal. This
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b8a61f0f63758..716072080340a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18154,8 +18154,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
// N0 + -0.0 --> N0 (also allowed with +0.0 and fast-math)
ConstantFPSDNode *N1C = isConstOrConstSplatFP(N1, true);
if (N1C && N1C->isZero())
- if (N1C->isNegative() || Flags.hasNoSignedZeros() ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0)))
+ if (N1C->isNegative() || DAG.canIgnoreSignBitOfZero(SDValue(N, 0)))
return N0;
if (SDValue NewSel = foldBinOpIntoSelect(N))
@@ -18367,8 +18366,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
// (fsub A, 0) -> A
if (N1CFP && N1CFP->isZero()) {
- if (!N1CFP->isNegative() || Flags.hasNoSignedZeros() ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0))) {
+ if (!N1CFP->isNegative() || DAG.canIgnoreSignBitOfZero(SDValue(N, 0))) {
return N0;
}
}
@@ -18381,8 +18379,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
// (fsub -0.0, N1) -> -N1
if (N0CFP && N0CFP->isZero()) {
- if (N0CFP->isNegative() || Flags.hasNoSignedZeros() ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0))) {
+ if (N0CFP->isNegative() || DAG.canIgnoreSignBitOfZero(SDValue(N, 0))) {
// We cannot replace an FSUB(+-0.0,X) with FNEG(X) when denormals are
// flushed to zero, unless all users treat denorms as zero (DAZ).
// FIXME: This transform will change the sign of a NaN and the behavior
@@ -19031,7 +19028,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
}
// Fold X/Sqrt(X) -> Sqrt(X)
- if ((Flags.hasNoSignedZeros() || DAG.canIgnoreSignBitOfZero(SDValue(N, 0))) &&
+ if (DAG.canIgnoreSignBitOfZero(SDValue(N, 0)) &&
Flags.hasAllowReassociation())
if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
return N1;
@@ -19083,8 +19080,7 @@ SDValue DAGCombiner::visitFREM(SDNode *N) {
TLI.isOperationLegalOrCustom(ISD::FDIV, VT) &&
TLI.isOperationLegalOrCustom(ISD::FTRUNC, VT) &&
DAG.isKnownToBeAPowerOfTwoFP(N1)) {
- bool NeedsCopySign = !Flags.hasNoSignedZeros() &&
- !DAG.canIgnoreSignBitOfZero(SDValue(N, 0)) &&
+ bool NeedsCopySign = !DAG.canIgnoreSignBitOfZero(SDValue(N, 0)) &&
!DAG.cannotBeOrderedNegativeFP(N0);
SDValue Div = DAG.getNode(ISD::FDIV, DL, VT, N0, N1);
SDValue Rnd = DAG.getNode(ISD::FTRUNC, DL, VT, Div);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 4823f77a61c4a..2c2b0546c51d8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6249,6 +6249,9 @@ bool SelectionDAG::cannotBeOrderedNegativeFP(SDValue Op) const {
bool SelectionDAG::canIgnoreSignBitOfZero(const SDUse &Use) const {
assert(Use.getValueType().isFloatingPoint());
const SDNode *User = Use.getUser();
+ if (User->getFlags().hasNoSignedZeros())
+ return true;
+
unsigned OperandNo = Use.getOperandNo();
// Check if this use is insensitive to the sign of zero
switch (User->getOpcode()) {
@@ -6277,6 +6280,8 @@ bool SelectionDAG::canIgnoreSignBitOfZero(const SDUse &Use) const {
}
bool SelectionDAG::canIgnoreSignBitOfZero(SDValue Op) const {
+ if (Op->getFlags().hasNoSignedZeros())
+ return true;
// FIXME: Limit the amount of checked uses to not introduce a compile-time
// regression. Ideally, this should be implemented as a demanded-bits
// optimization that stems from the users.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2775ddcff353c..bda1993ef9238 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7864,8 +7864,7 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
: Intrinsic::aarch64_neon_bfmlalt);
EVT AccVT = UseSVEBFMLAL ? MVT::nxv4f32 : MVT::v4f32;
- bool IgnoreZeroSign =
- Op->getFlags().hasNoSignedZeros() || DAG.canIgnoreSignBitOfZero(Op);
+ bool IgnoreZeroSign = DAG.canIgnoreSignBitOfZero(Op);
SDValue Zero = DAG.getConstantFP(IgnoreZeroSign ? +0.0F : -0.0F, DL, AccVT);
SDValue Pg = getPredicateForVector(DAG, DL, AccVT);
diff --git a/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll b/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
index a8049806a679b..35fc1c6a9773c 100644
--- a/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
+++ b/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
@@ -486,8 +486,8 @@ define <vscale x 8 x bfloat> @fsub_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <
define <vscale x 8 x bfloat> @fadd_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_nsz_nxv8bf16:
; SVE: // %bb.0:
-; SVE-NEXT: mov z3.s, #0x80000000
-; SVE-NEXT: mov z4.s, #0x80000000
+; SVE-NEXT: movi v3.2d, #0000000000000000
+; SVE-NEXT: movi v4.2d, #0000000000000000
; SVE-NEXT: ptrue p1.s
; SVE-NEXT: bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT: bfmlalt z4.s, z1.h, z2.h
@@ -522,8 +522,8 @@ define <vscale x 8 x bfloat> @fadd_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %
define <vscale x 8 x bfloat> @fsub_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_nsz_nxv8bf16:
; SVE: // %bb.0:
-; SVE-NEXT: mov z3.s, #0x80000000
-; SVE-NEXT: mov z4.s, #0x80000000
+; SVE-NEXT: movi v3.2d, #0000000000000000
+; SVE-NEXT: movi v4.2d, #0000000000000000
; SVE-NEXT: ptrue p1.s
; SVE-NEXT: bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT: bfmlalt z4.s, z1.h, z2.h
@@ -636,8 +636,8 @@ define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloa
define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fadd_sel_fmul_negzero_nsz_nxv8bf16:
; SVE: // %bb.0:
-; SVE-NEXT: mov z3.s, #0x80000000
-; SVE-NEXT: mov z4.s, #0x80000000
+; SVE-NEXT: movi v3.2d, #0000000000000000
+; SVE-NEXT: movi v4.2d, #0000000000000000
; SVE-NEXT: ptrue p1.s
; SVE-NEXT: bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT: bfmlalt z4.s, z1.h, z2.h
@@ -673,8 +673,8 @@ define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x b
define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, <vscale x 8 x i1> %mask) {
; SVE-LABEL: fsub_sel_fmul_negzero_nsz_nxv8bf16:
; SVE: // %bb.0:
-; SVE-NEXT: mov z3.s, #0x80000000
-; SVE-NEXT: mov z4.s, #0x80000000
+; SVE-NEXT: movi v3.2d, #0000000000000000
+; SVE-NEXT: movi v4.2d, #0000000000000000
; SVE-NEXT: ptrue p1.s
; SVE-NEXT: bfmlalb z3.s, z1.h, z2.h
; SVE-NEXT: bfmlalt z4.s, z1.h, z2.h
>From 6ef289862ba414b5ef06b02962975c0e5562b58c Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Fri, 30 Jan 2026 16:34:30 +0000
Subject: [PATCH 2/2] Update other target tests
---
.../amdgpu-simplify-libcall-pow-codegen.ll | 34 +++++++++----------
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 10 +++---
llvm/test/CodeGen/RISCV/fma-combine.ll | 22 +++++-------
3 files changed, 29 insertions(+), 37 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 0329f23ea434f..a8e5e11b37f25 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -60,15 +60,14 @@ define half @test_pow_fast_f16__integral_y(half %x, i32 %y.i) {
; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
; CHECK-NEXT: v_log_f16_e64 v3, |v0|
; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CHECK-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CHECK-NEXT: v_cvt_i32_f32_e32 v1, v1
-; CHECK-NEXT: v_cvt_f32_i32_e32 v2, v1
-; CHECK-NEXT: v_lshlrev_b16_e32 v1, 15, v1
-; CHECK-NEXT: v_and_b32_e32 v0, v1, v0
-; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CHECK-NEXT: v_mul_f16_e32 v2, v3, v2
-; CHECK-NEXT: v_exp_f16_e32 v2, v2
-; CHECK-NEXT: v_or_b32_e32 v0, v0, v2
+; CHECK-NEXT: v_cvt_f32_f16_e32 v2, v1
+; CHECK-NEXT: v_trunc_f16_e32 v1, v1
+; CHECK-NEXT: v_mul_f16_e32 v1, v3, v1
+; CHECK-NEXT: v_exp_f16_e32 v1, v1
+; CHECK-NEXT: v_cvt_i32_f32_e32 v2, v2
+; CHECK-NEXT: v_lshlrev_b16_e32 v2, 15, v2
+; CHECK-NEXT: v_and_b32_e32 v0, v2, v0
+; CHECK-NEXT: v_or_b32_e32 v0, v0, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%y = sitofp i32 %y.i to half
%pow = tail call fast half @_Z3powDhDh(half %x, half %y)
@@ -79,28 +78,28 @@ define float @test_pow_fast_f32__integral_y(float %x, i32 %y.i) {
; CHECK-LABEL: test_pow_fast_f32__integral_y:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 32, vcc
-; CHECK-NEXT: v_cvt_i32_f32_e32 v1, v1
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_log_f32_e32 v3, v3
+; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
-; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; CHECK-NEXT: v_sub_f32_e32 v2, v3, v2
+; CHECK-NEXT: v_trunc_f32_e32 v3, v1
+; CHECK-NEXT: v_mul_f32_e32 v4, v2, v3
; CHECK-NEXT: s_mov_b32 s4, 0xc2fc0000
-; CHECK-NEXT: v_mul_f32_e32 v3, v2, v4
; CHECK-NEXT: v_mov_b32_e32 v5, 0x42800000
-; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
-; CHECK-NEXT: v_fma_f32 v2, v2, v4, v3
+; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v5, vcc
+; CHECK-NEXT: v_fma_f32 v2, v2, v3, v4
; CHECK-NEXT: v_exp_f32_e32 v2, v2
+; CHECK-NEXT: v_cvt_i32_f32_e32 v1, v1
; CHECK-NEXT: v_not_b32_e32 v3, 63
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v1
; CHECK-NEXT: v_ldexp_f32 v2, v2, v3
+; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v1
; CHECK-NEXT: v_and_or_b32 v0, v1, v0, v2
; CHECK-NEXT: s_setpc_b64 s[30:31]
%y = sitofp i32 %y.i to float
@@ -768,4 +767,3 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
%call = tail call fast double @_Z4powndi(double %x, i32 %y)
ret double %call
}
-
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 810cebfab9798..3e7d67a40b12b 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -648,6 +648,8 @@ define amdgpu_ps double @fneg_fadd_0_f64_nsz(double inreg %tmp2, double inreg %t
; SI-LABEL: fneg_fadd_0_f64_nsz:
; SI: ; %bb.0: ; %.entry
; SI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_brev_b32 s5, 1
; SI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
@@ -660,10 +662,7 @@ define amdgpu_ps double @fneg_fadd_0_f64_nsz(double inreg %tmp2, double inreg %t
; SI-NEXT: v_mov_b32_e32 v2, s1
; SI-NEXT: v_mov_b32_e32 v3, s0
; SI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; SI-NEXT: s_mov_b32 s2, 0
-; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; SI-NEXT: s_brev_b32 s3, 1
-; SI-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
+; SI-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; SI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
@@ -690,8 +689,7 @@ define amdgpu_ps double @fneg_fadd_0_f64_nsz(double inreg %tmp2, double inreg %t
; VI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_brev_b32 s3, 1
-; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; VI-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
+; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[2:3]
; VI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
diff --git a/llvm/test/CodeGen/RISCV/fma-combine.ll b/llvm/test/CodeGen/RISCV/fma-combine.ll
index 9291ce42d765c..0168fede6b88f 100644
--- a/llvm/test/CodeGen/RISCV/fma-combine.ll
+++ b/llvm/test/CodeGen/RISCV/fma-combine.ll
@@ -11,28 +11,24 @@ define double @fnmadd_non_trivial(ptr %p0, ptr %p1, ptr %dst, double %mul425) {
; CHECK-NEXT: li a3, -2047
; CHECK-NEXT: slli a3, a3, 51
; CHECK-NEXT: fmv.d.x fa5, a3
-; CHECK-NEXT: lui a3, 2049
-; CHECK-NEXT: slli a3, a3, 39
-; CHECK-NEXT: fmv.d.x fa4, a3
; CHECK-NEXT: lui a3, 8201
; CHECK-NEXT: slli a3, a3, 37
-; CHECK-NEXT: fmv.d.x fa3, a3
-; CHECK-NEXT: li a3, 1023
-; CHECK-NEXT: fmv.d.x fa2, zero
+; CHECK-NEXT: fmv.d.x fa4, a3
+; CHECK-NEXT: li a3, -1025
; CHECK-NEXT: slli a3, a3, 52
-; CHECK-NEXT: fsub.d fa1, fa2, fa0
-; CHECK-NEXT: fmadd.d fa1, fa1, fa3, fa4
-; CHECK-NEXT: fmadd.d fa4, fa0, fa3, fa4
; CHECK-NEXT: fmv.d.x fa3, a3
; CHECK-NEXT: lui a3, %hi(.LCPI0_0)
+; CHECK-NEXT: fmv.d.x fa2, zero
; CHECK-NEXT: ld a3, %lo(.LCPI0_0)(a3)
+; CHECK-NEXT: fnmsub.d fa1, fa0, fa4, fa5
+; CHECK-NEXT: fmadd.d fa4, fa0, fa4, fa5
; CHECK-NEXT: fmul.d fa5, fa0, fa5
-; CHECK-NEXT: fnmadd.d fa4, fa4, fa2, fa3
-; CHECK-NEXT: fnmadd.d fa3, fa1, fa2, fa3
+; CHECK-NEXT: fmadd.d fa1, fa1, fa2, fa3
+; CHECK-NEXT: fmadd.d fa4, fa4, fa2, fa3
; CHECK-NEXT: sd a3, 0(a2)
; CHECK-NEXT: fsd fa5, 0(a0)
-; CHECK-NEXT: fnmadd.d fa5, fa4, fa2, fa0
-; CHECK-NEXT: fnmadd.d fa0, fa0, fa2, fa3
+; CHECK-NEXT: fnmadd.d fa5, fa1, fa2, fa0
+; CHECK-NEXT: fnmadd.d fa0, fa0, fa2, fa4
; CHECK-NEXT: fsd fa5, 0(a1)
; CHECK-NEXT: ret
store double 0x3FEE666666666666, ptr %dst, align 8
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