[llvm] [AArch64][llvm] Remove `+d128` gating on `sysp`, `msrr` and `mrrs` instructions (PR #178912)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 30 08:22:34 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
<details>
<summary>Changes</summary>
Remove `+d128` gating on `sysp`, `msrr` and `mrrs` instructions.
We removed gating for `sys`, `mrs` and `mrs` instructions previously,
on the basis that it doesn't add value, as it doesn't indicate that
any particular system registers or system instructions are available.
Therefore, remove `+d128` gating for these too.
(In an upcoming change, some `tlbip` instructions, which are `sysp` aliases
are allowed to be used with either `+d128` or `tlbid`. If we don't remove
this gating, then it would require some ugly work-arounds in the code to
support the relaxation mandated by the 2025 MemSys specification.
In this change, retain `+d128` gating for all `tlbip` instructions, which
will then be loosened to either `+d128` or `+tlbid` in a subsequent change)
---
Patch is 67.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/178912.diff
9 Files Affected:
- (modified) llvm/docs/ReleaseNotes.md (+3)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+43-47)
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+4-2)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+2)
- (modified) llvm/test/MC/AArch64/armv9-mrrs.s (+7-97)
- (modified) llvm/test/MC/AArch64/armv9-msrr.s (+7-53)
- (modified) llvm/test/MC/AArch64/armv9a-sysp.s (+122-196)
- (modified) llvm/test/MC/AArch64/directive-arch_extension-negative.s (+2-3)
- (modified) llvm/test/MC/AArch64/directive-arch_extension.s (+1-1)
``````````diff
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index c3ff79e5422ab..5c34551cac07f 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -83,6 +83,9 @@ Changes to Vectorizers
Changes to the AArch64 Backend
------------------------------
+* The `sysp`, `mrrs`, and `msrr` instructions are now accepted without
+ requiring the `+d128` feature gating.
+
Changes to the AMDGPU Backend
-----------------------------
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index cefec898f4dc7..1fd01691c780e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -11289,40 +11289,38 @@ let Predicates = [HasRCPC3, HasNEON] in {
//===----------------------------------------------------------------------===//
// 128-bit System Instructions (FEAT_SYSINSTR128)
//===----------------------------------------------------------------------===//
-let Predicates = [HasD128] in {
- def SYSPxt : SystemPXtI<0, "sysp">;
-
- def SYSPxt_XZR
- : BaseSystemI<0, (outs),
- (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair),
- "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">,
- Sched<[WriteSys]>
- {
- // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)
- // and therefore autogenerates a decoder that builds an MC representation that has 4 fields
- // (decodeToMCInst), but when printing we expect the MC representation to have 5 fields (one
- // extra for the XZR) because AArch64InstPrinter::printInstruction in AArch64GenAsmWriter.inc
- // is based off of the asm template (maybe) and therefore wants to print 5 operands.
- // I could add a bits<5> xzr_pair. But without a way to constrain it to 0b11111 here it would
- // overlap with the main SYSP instruction.
- let DecoderMethod = "DecodeSyspXzrInstruction";
- bits<3> op1;
- bits<4> Cn;
- bits<4> Cm;
- bits<3> op2;
- let Inst{22} = 0b1; // override BaseSystemI
- let Inst{20-19} = 0b01;
- let Inst{18-16} = op1;
- let Inst{15-12} = Cn;
- let Inst{11-8} = Cm;
- let Inst{7-5} = op2;
- let Inst{4-0} = 0b11111;
- }
-
- def : InstAlias<"sysp $op1, $Cn, $Cm, $op2",
- (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
+def SYSPxt : SystemPXtI<0, "sysp">;
+
+def SYSPxt_XZR
+ : BaseSystemI<0, (outs),
+ (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair),
+ "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">,
+ Sched<[WriteSys]>
+{
+ // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)
+ // and therefore autogenerates a decoder that builds an MC representation that has 4 fields
+ // (decodeToMCInst), but when printing we expect the MC representation to have 5 fields (one
+ // extra for the XZR) because AArch64InstPrinter::printInstruction in AArch64GenAsmWriter.inc
+ // is based off of the asm template (maybe) and therefore wants to print 5 operands.
+ // I could add a bits<5> xzr_pair. But without a way to constrain it to 0b11111 here it would
+ // overlap with the main SYSP instruction.
+ let DecoderMethod = "DecodeSyspXzrInstruction";
+ bits<3> op1;
+ bits<4> Cn;
+ bits<4> Cm;
+ bits<3> op2;
+ let Inst{22} = 0b1; // override BaseSystemI
+ let Inst{20-19} = 0b01;
+ let Inst{18-16} = op1;
+ let Inst{15-12} = Cn;
+ let Inst{11-8} = Cm;
+ let Inst{7-5} = op2;
+ let Inst{4-0} = 0b11111;
}
+def : InstAlias<"sysp $op1, $Cn, $Cm, $op2",
+ (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
+
//---
// 128-bit System Registers (FEAT_SYSREG128)
//---
@@ -11340,22 +11338,20 @@ let Predicates = [HasD128] in {
//
// ...where t is even (X0, X2, etc).
-let Predicates = [HasD128] in {
- def MRRS : RtSystemI128<1,
- (outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),
- "mrrs", "\t$Rt, $systemreg">
- {
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
- }
+def MRRS : RtSystemI128<1,
+ (outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),
+ "mrrs", "\t$Rt, $systemreg">
+{
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
+}
- def MSRR : RtSystemI128<0,
- (outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),
- "msrr", "\t$systemreg, $Rt">
- {
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
- }
+def MSRR : RtSystemI128<0,
+ (outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),
+ "msrr", "\t$systemreg, $Rt">
+{
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
}
//===----------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index cb098751fd74d..844af6e3a4eb7 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,10 +903,12 @@ multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm
let ExtraRequires = ["AArch64::FeatureXS"];
}
if !eq(hasTLBIP, true) then {
- def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;
+ def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg> {
+ let ExtraRequires = ["AArch64::FeatureD128"];
+ }
def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> {
let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureXS"];
+ let ExtraRequires = ["AArch64::FeatureD128", "AArch64::FeatureXS"];
}
}
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5ef3e2e50ec86..6dcd7f5ec4cc9 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4269,6 +4269,8 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
const AArch64TLBIP::TLBIP *TLBIPorig = AArch64TLBIP::lookupTLBIPByName(Op);
if (!TLBIPorig)
return TokError("invalid operand for TLBIP instruction");
+ if (!getSTI().getFeatureBits()[AArch64::FeatureD128])
+ return TokError("instruction requires: d128");
const AArch64TLBIP::TLBIP TLBIP(
TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
TLBIPorig->NeedsReg, TLBIPorig->OptionalReg,
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
index 1fc7274f64d4a..1c6733dffb421 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -1,15 +1,13 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+el2vmsa,+vh < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \
-// RUN: | llvm-objdump -d --mattr=+d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \
-// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+el2vmsa,+vh < %s \
+// RUN: | llvm-objdump -d --mattr=+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+el2vmsa,+vh < %s \
+// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+el2vmsa,+vh < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
@@ -20,263 +18,175 @@
mrrs x0, x1, TTBR0_EL1
// CHECK-INST: mrrs x0, x1, TTBR0_EL1
// CHECK-ENCODING: encoding: [0x00,0x20,0x78,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d5782000 <unknown>
mrrs x0, x1, TTBR1_EL1
// CHECK-INST: mrrs x0, x1, TTBR1_EL1
// CHECK-ENCODING: encoding: [0x20,0x20,0x78,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d5782020 <unknown>
mrrs x0, x1, PAR_EL1
// CHECK-INST: mrrs x0, x1, PAR_EL1
// CHECK-ENCODING: encoding: [0x00,0x74,0x78,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d5787400 <unknown>
mrrs x0, x1, RCWSMASK_EL1
// CHECK-INST: mrrs x0, x1, RCWSMASK_EL1
// CHECK-ENCODING: encoding: [0x60,0xd0,0x78,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d578d060 <unknown>
mrrs x0, x1, RCWMASK_EL1
// CHECK-INST: mrrs x0, x1, RCWMASK_EL1
// CHECK-ENCODING: encoding: [0xc0,0xd0,0x78,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d578d0c0 <unknown>
mrrs x0, x1, TTBR0_EL2
// CHECK-INST: mrrs x0, x1, TTBR0_EL2
// CHECK-ENCODING: encoding: [0x00,0x20,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2000 <unknown>
mrrs x0, x1, TTBR1_EL2
// CHECK-INST: mrrs x0, x1, TTBR1_EL2
// CHECK-ENCODING: encoding: [0x20,0x20,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2020 <unknown>
mrrs x0, x1, VTTBR_EL2
// CHECK-INST: mrrs x0, x1, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x00,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2100 <unknown>
mrrs x0, x1, VTTBR_EL2
// CHECK-INST: mrrs x0, x1, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x00,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2100 <unknown>
mrrs x2, x3, VTTBR_EL2
// CHECK-INST: mrrs x2, x3, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x02,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2102 <unknown>
mrrs x4, x5, VTTBR_EL2
// CHECK-INST: mrrs x4, x5, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x04,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2104 <unknown>
mrrs x6, x7, VTTBR_EL2
// CHECK-INST: mrrs x6, x7, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x06,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2106 <unknown>
mrrs x8, x9, VTTBR_EL2
// CHECK-INST: mrrs x8, x9, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x08,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2108 <unknown>
mrrs x10, x11, VTTBR_EL2
// CHECK-INST: mrrs x10, x11, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x0a,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c210a <unknown>
mrrs x12, x13, VTTBR_EL2
// CHECK-INST: mrrs x12, x13, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x0c,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c210c <unknown>
mrrs x14, x15, VTTBR_EL2
// CHECK-INST: mrrs x14, x15, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x0e,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c210e <unknown>
mrrs x16, x17, VTTBR_EL2
// CHECK-INST: mrrs x16, x17, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x10,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2110 <unknown>
mrrs x18, x19, VTTBR_EL2
// CHECK-INST: mrrs x18, x19, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x12,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2112 <unknown>
mrrs x20, x21, VTTBR_EL2
// CHECK-INST: mrrs x20, x21, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x14,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2114 <unknown>
mrrs x22, x23, VTTBR_EL2
// CHECK-INST: mrrs x22, x23, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x16,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2116 <unknown>
mrrs x24, x25, VTTBR_EL2
// CHECK-INST: mrrs x24, x25, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x18,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c2118 <unknown>
mrrs x26, x27, VTTBR_EL2
// CHECK-INST: mrrs x26, x27, VTTBR_EL2
// CHECK-ENCODING: encoding: [0x1a,0x21,0x7c,0xd5]
-// CHECK-ERROR: error: instruction requires: d128
-// CHECK-UNKNOWN: d57c211a <unknown>
msrr TTBR0_EL1, x0, x1
// CHECK-INST: msrr TTBR0_EL1, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x20,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d5582000 <unknown>
msrr TTBR1_EL1, x0, x1
// CHECK-INST: msrr TTBR1_EL1, x0, x1
// CHECK-ENCODING: encoding: [0x20,0x20,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d5582020 <unknown>
msrr PAR_EL1, x0, x1
// CHECK-INST: msrr PAR_EL1, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x74,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d5587400 <unknown>
msrr RCWSMASK_EL1, x0, x1
// CHECK-INST: msrr RCWSMASK_EL1, x0, x1
// CHECK-ENCODING: encoding: [0x60,0xd0,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d558d060 <unknown>
msrr RCWMASK_EL1, x0, x1
// CHECK-INST: msrr RCWMASK_EL1, x0, x1
// CHECK-ENCODING: encoding: [0xc0,0xd0,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d558d0c0 <unknown>
msrr TTBR0_EL2, x0, x1
// CHECK-INST: msrr TTBR0_EL2, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x20,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2000 <unknown>
msrr TTBR1_EL2, x0, x1
// CHECK-INST: msrr TTBR1_EL2, x0, x1
// CHECK-ENCODING: encoding: [0x20,0x20,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2020 <unknown>
msrr VTTBR_EL2, x0, x1
// CHECK-INST: msrr VTTBR_EL2, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2100 <unknown>
msrr VTTBR_EL2, x0, x1
// CHECK-INST: msrr VTTBR_EL2, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2100 <unknown>
msrr VTTBR_EL2, x2, x3
// CHECK-INST: msrr VTTBR_EL2, x2, x3
// CHECK-ENCODING: encoding: [0x02,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2102 <unknown>
msrr VTTBR_EL2, x4, x5
// CHECK-INST: msrr VTTBR_EL2, x4, x5
// CHECK-ENCODING: encoding: [0x04,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2104 <unknown>
msrr VTTBR_EL2, x6, x7
// CHECK-INST: msrr VTTBR_EL2, x6, x7
// CHECK-ENCODING: encoding: [0x06,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2106 <unknown>
msrr VTTBR_EL2, x8, x9
// CHECK-INST: msrr VTTBR_EL2, x8, x9
// CHECK-ENCODING: encoding: [0x08,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2108 <unknown>
msrr VTTBR_EL2, x10, x11
// CHECK-INST: msrr VTTBR_EL2, x10, x11
// CHECK-ENCODING: encoding: [0x0a,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c210a <unknown>
msrr VTTBR_EL2, x12, x13
// CHECK-INST: msrr VTTBR_EL2, x12, x13
// CHECK-ENCODING: encoding: [0x0c,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c210c <unknown>
msrr VTTBR_EL2, x14, x15
// CHECK-INST: msrr VTTBR_EL2, x14, x15
// CHECK-ENCODING: encoding: [0x0e,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c210e <unknown>
msrr VTTBR_EL2, x16, x17
// CHECK-INST: msrr VTTBR_EL2, x16, x17
// CHECK-ENCODING: encoding: [0x10,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2110 <unknown>
msrr VTTBR_EL2, x18, x19
// CHECK-INST: msrr VTTBR_EL2, x18, x19
// CHECK-ENCODING: encoding: [0x12,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2112 <unknown>
msrr VTTBR_EL2, x20, x21
// CHECK-INST: msrr VTTBR_EL2, x20, x21
// CHECK-ENCODING: encoding: [0x14,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2114 <unknown>
msrr VTTBR_EL2, x22, x23
// CHECK-INST: msrr VTTBR_EL2, x22, x23
// CHECK-ENCODING: encoding: [0x16,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2116 <unknown>
msrr VTTBR_EL2, x24, x25
// CHECK-INST: msrr VTTBR_EL2, x24, x25
// CHECK-ENCODING: encoding: [0x18,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c2118 <unknown>
msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128
-// CHECK-UNKNOWN: d55c211a <unknown>
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
index 439e054779b07..1c419e1e5c7ef 100644
--- a/llvm/test/MC/AArch64/armv9-msrr.s
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -1,15 +1,13 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+el2vmsa,+vh < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \
-// RUN: | llvm-objdump -d --mattr=+d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \
-// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+el2vmsa,+vh < %s \
+// RUN: | llvm-objdump -d --mattr=+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+el2vmsa,+vh < %s \
+// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+el2vmsa,+vh < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
@@ -20,131 +18,87 @@
msrr TTBR0_EL1, x0, x1
// CHECK-INST: msrr TTBR0_EL1, x0, x1
// CHECK-ENCODING: encoding: [0x00,0x20,0x58,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:1: error: instructi...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/178912
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