[llvm] [AMDGPU] Have VCC as a first-class member of the SGPR pool. (PR #173870)

[Ivan Kosarev via llvm-commits]

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@@ -2784,7 +2785,23 @@ ParseStatus AMDGPUAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
 
 bool AMDGPUAsmParser::AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
                                             RegisterKind RegKind,
-                                            MCRegister Reg1, SMLoc Loc) {
+                                            MCRegister Reg1,
+                                            RegisterKind RegKind1, SMLoc Loc) {
+  // Allow VCC_LO/HI at the end of SGPR lists.
+  if (RegKind == IS_SGPR) {
+    unsigned RegIdx = (Reg - AMDGPU::SGPR0) + RegWidth / 32;
+    if ((RegIdx == 106 && Reg1 == AMDGPU::VCC_LO) ||
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kosarev wrote:

Yes, that's just the sequential number of the 32-bit SGPR. We make VCC_LO and VCC_HI to be treated as the 106th and 107th SGPRs respectively.

https://github.com/llvm/llvm-project/pull/173870