[llvm] [AMDGPU] Insert readfirstlane for uniform VGPR arguments (PR #178198)

[Matt Arsenault via llvm-commits]

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@@ -3551,6 +3554,10 @@ SDValue SITargetLowering::LowerFormalArguments(
 
     Reg = MF.addLiveIn(Reg, RC);
     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
+    if (Arg.Flags.isInReg() && RC == &AMDGPU::VGPR_32RegClass) {
+      Val = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Val.getValueType(),
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arsenm wrote:

Or as long as the chain from the original copy is forwarded along to where the chains are managed, that's also fine 

https://github.com/llvm/llvm-project/pull/178198