[llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)

[Matt Arsenault via llvm-commits]

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@@ -2141,6 +2160,113 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
   addPass(SIShrinkInstructionsPass());
 }
 
+static const char NPMRegAllocOptNotSupportedMessage[] =
+    "-regalloc-npm not supported with amdgcn. Use -sgpr-regalloc-npm, "
+    "-wwm-regalloc-npm, "
+    "and -vgpr-regalloc-npm";
+
+template <typename RegAllocPassT>
+typename RegAllocPassT::Options
+AMDGPUCodeGenPassBuilder::getRAOptionsForPhase(RegAllocPhase Phase) const {
+#define RA_OPTIONS(FilterFunc, Name, ClearVirtRegs)                            \
+  [&]() {                                                                      \
+    if constexpr (std::is_same_v<RegAllocPassT, RegAllocFastPass>) {           \
+      return RegAllocFastPass::Options{FilterFunc, Name, ClearVirtRegs};       \
+    } else {                                                                   \
+      return typename RegAllocPassT::Options{FilterFunc, Name};                \
+    }                                                                          \
+  }()
+
+  switch (Phase) {
+  case RegAllocPhase::SGPR:
+    return RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
+  case RegAllocPhase::WWM:
+    return RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
+  case RegAllocPhase::VGPR:
+    return RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
+  }
+
+  llvm_unreachable("invalid phase value");
+#undef RA_OPTIONS
+}
+
+template <typename RegAllocPassT>
+void AMDGPUCodeGenPassBuilder::addRegAlloc(AddMachinePass &addPass,
+                                           RegAllocPhase Phase) const {
+  RegAllocType RAType;
+  // Read the appropriate phase's regalloc type.
+  switch (Phase) {
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arsenm wrote:

switch to assign a variable you just switch over. Just handle Phase directly in the second switch? 

https://github.com/llvm/llvm-project/pull/129035