[llvm] e9e8b38 - [AMDGPU] Update documentation for wave reduction intrinsics (#175132)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 30 04:49:44 PST 2026
Author: Aaditya
Date: 2026-01-30T18:19:40+05:30
New Revision: e9e8b38c800d92e146aca1b694020382cb427dd7
URL: https://github.com/llvm/llvm-project/commit/e9e8b38c800d92e146aca1b694020382cb427dd7
DIFF: https://github.com/llvm/llvm-project/commit/e9e8b38c800d92e146aca1b694020382cb427dd7.diff
LOG: [AMDGPU] Update documentation for wave reduction intrinsics (#175132)
Added:
Modified:
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 101ba4e896638..cd5410a31b98f 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1387,9 +1387,22 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
0: Target default preference,
1: `Iterative strategy`, and
2: `DPP`.
- If target does not support the DPP operations (e.g. gfx6/7),
+ If the target does not support the DPP operations (e.g. gfx6/7),
reduction will be performed using default iterative strategy.
- Intrinsic is currently only implemented for i32.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.min Similar to `llvm.amdgcn.wave.reduce.umin`, but performs a signed min
+ reduction on signed integers.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.fmin Similar to `llvm.amdgcn.wave.reduce.umin`, but performs a floating point min
+ reduction on floating point values.
+ Intrinsic is implemented for float and double types.
+ Intrinsic is modelled similar to `llvm.minnum` intrinsic.
+ For a reduction between two NAN values, a NAN is returned.
+ For a reduction between a NAN and a number, the number is returned.
+ -0.0 < +0.0 is true for this reduction.
+ The ordering behaviour of SNANs is non-deterministic.
llvm.amdgcn.wave.reduce.umax Performs an arithmetic unsigned max reduction on the unsigned values
provided by each lane in the wavefront.
@@ -1397,9 +1410,68 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
0: Target default preference,
1: `Iterative strategy`, and
2: `DPP`.
- If target does not support the DPP operations (e.g. gfx6/7),
+ If the target does not support the DPP operations (e.g. gfx6/7),
+ reduction will be performed using default iterative strategy.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.max Similar to `llvm.amdgcn.wave.reduce.umax`, but performs a signed max
+ reduction on signed integers.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.fmax Similar to `llvm.amdgcn.wave.reduce.umax`, but performs a floating point max
+ reduction on floating point values.
+ Intrinsic is implemented for float and double types.
+ Intrinsic is modelled similar to `llvm.maxnum` intrinsic.
+ For a reduction between two NAN values, a NAN is returned.
+ For a reduction between a NAN and a number, the number is returned.
+ -0.0 < +0.0 is true for this reduction.
+ The ordering behaviour of SNANs is non-deterministic.
+
+ llvm.amdgcn.wave.reduce.add Performs an arithmetic add reduction on the signed/unsigned values
+ provided by each lane in the wavefront.
+ Intrinsic takes a hint for reduction strategy using second operand
+ 0: Target default preference,
+ 1: `Iterative strategy`, and
+ 2: `DPP`.
+ If the target does not support the DPP operations (e.g. gfx6/7),
+ reduction will be performed using default iterative strategy.
+ Intrinsic is implemented for signed/unsigned i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.fadd Similar to `llvm.amdgcn.wave.reduce.add`, but performs a floating point add
+ reduction on floating point values.
+ Intrinsic is implemented for float and double types.
+
+ llvm.amdgcn.wave.reduce.sub Performs an arithmetic sub reduction on the signed/unsigned values
+ provided by each lane in the wavefront.
+ Intrinsic takes a hint for reduction strategy using second operand
+ 0: Target default preference,
+ 1: `Iterative strategy`, and
+ 2: `DPP`.
+ If the target does not support the DPP operations (e.g. gfx6/7),
reduction will be performed using default iterative strategy.
- Intrinsic is currently only implemented for i32.
+ Intrinsic is implemented for signed/unsigned i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.fsub Similar to `llvm.amdgcn.wave.reduce.sub`, but performs a floating point sub
+ reduction on floating point values.
+ Intrinsic is implemented for float and double types.
+
+ llvm.amdgcn.wave.reduce.and Performs a bitwise-and reduction on the values
+ provided by each lane in the wavefront.
+ Intrinsic takes a hint for reduction strategy using second operand
+ 0: Target default preference,
+ 1: `Iterative strategy`, and
+ 2: `DPP`.
+ If the target does not support the DPP operations (e.g. gfx6/7),
+ reduction will be performed using default iterative strategy.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.or Similar to `llvm.amdgcn.wave.reduce.and`, but performs a bitwise-or
+ reduction on the values provided by each wavefront.
+ Intrinsic is implemented for i32 and i64 types.
+
+ llvm.amdgcn.wave.reduce.xor Similar to `llvm.amdgcn.wave.reduce.and`, but performs a bitwise-xor
+ reduction on the values provided by each wavefront.
+ Intrinsic is implemented for i32 and i64 types.
llvm.amdgcn.permlane16 Provides direct access to v_permlane16_b32. Performs arbitrary gather-style
operation within a row (16 contiguous lanes) of the second input operand.
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