[llvm] Revert "[DAG] Enable bitcast STLF for Constant/Undef" (PR #178872)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 30 03:49:12 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Alex Bradbury (asb)
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->172523
As explained in https://github.com/llvm/llvm-project/pull/172523#issuecomment-3823234270 (along with reproducer), this causes compiler crashes building llvm-test-suite for RVV targets.
---
Patch is 50.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/178872.diff
42 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-26)
- (modified) llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/pr161013.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll (+1)
- (removed) llvm/test/CodeGen/AArch64/sve-stlf.ll (-12)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll (+6-3)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll (+8)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll (+14)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll (+8-4)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll (+5-2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll (+8-4)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll (+4-2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll (+6-3)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll (+8-4)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll (+22-8)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll (+4-2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll (+6-3)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll (+3-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll (+4-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll (+6-2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll (+5-4)
- (modified) llvm/test/CodeGen/AArch64/v3f-to-int.ll (+4-1)
- (modified) llvm/test/CodeGen/PowerPC/vsx-p9.ll (+2-2)
- (removed) llvm/test/CodeGen/RISCV/rvv/stlf.ll (-12)
- (modified) llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll (+2)
- (modified) llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll (+4-1)
- (removed) llvm/test/CodeGen/X86/dag-stlf-mismatch.ll (-71)
- (modified) llvm/test/CodeGen/X86/pr30290.ll (+3-2)
- (modified) llvm/test/CodeGen/X86/pr38533.ll (+6-3)
- (modified) llvm/test/CodeGen/X86/vectorcall.ll (+4-4)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d1de43318bd09..b8a61f0f63758 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20747,32 +20747,9 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
if (!isTypeLegal(LDMemType))
break;
if (STMemType != LDMemType) {
- if (LdMemSize == StMemSize) {
- if (TLI.isOperationLegal(ISD::BITCAST, LDMemType) &&
- isTypeLegal(LDMemType) &&
- TLI.isOperationLegal(ISD::BITCAST, STMemType) &&
- isTypeLegal(STMemType) &&
- TLI.isLoadBitCastBeneficial(LDMemType, STMemType, DAG,
- *LD->getMemOperand()))
- Val = DAG.getBitcast(LDMemType, Val);
- else
- break;
- } else if (LDMemType.isVector()) {
- EVT EltVT = LDMemType.getVectorElementType();
- uint64_t EltSize = EltVT.getSizeInBits();
-
- if (!StMemSize.isKnownMultipleOf(EltSize))
- break;
-
- EVT InterVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
- StMemSize.divideCoefficientBy(EltSize));
- if (!TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, InterVT))
- break;
-
- Val = DAG.getExtractSubvector(SDLoc(LD), LDMemType,
- DAG.getBitcast(InterVT, Val), 0);
- } else if (!STMemType.isVector() && !LDMemType.isVector() &&
- STMemType.isInteger() && LDMemType.isInteger())
+ // TODO: Support vectors? This requires extract_subvector/bitcast.
+ if (!STMemType.isVector() && !LDMemType.isVector() &&
+ STMemType.isInteger() && LDMemType.isInteger())
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD), LDMemType, Val);
else
break;
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index 2c1b735ffe28c..35ffc99f7a405 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -508,8 +508,8 @@ define <4 x i8> @small_vector(<4 x i8> %0) {
; CHECK-NEXT: add x29, sp, #176
; CHECK-NEXT: .seh_add_fp 176
; CHECK-NEXT: .seh_endprologue
-; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: str w0, [sp, #12]
+; CHECK-NEXT: ldr s0, [sp, #12]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: blr x9
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
index 6fba6a3974574..dc352244deeef 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
@@ -477,8 +477,8 @@ declare <4 x i8> @small_vector(<4 x i8> %0) nounwind;
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: stur s0, [x29, #-4]
; CHECK-NEXT: blr x16
-; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: stur w8, [x29, #-8]
+; CHECK-NEXT: ldur s0, [x29, #-8]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: .seh_startepilogue
diff --git a/llvm/test/CodeGen/AArch64/pr161013.ll b/llvm/test/CodeGen/AArch64/pr161013.ll
index c493a80ce2edb..d163914f1ac0e 100644
--- a/llvm/test/CodeGen/AArch64/pr161013.ll
+++ b/llvm/test/CodeGen/AArch64/pr161013.ll
@@ -6,7 +6,8 @@ define <16 x i4> @avir_v2i4_v16i4(<2 x i4> %arg) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: str d0, [sp, #8]
+; CHECK-NEXT: ldr x8, [sp, #8]
; CHECK-NEXT: and w10, w8, #0xf
; CHECK-NEXT: ubfx w9, w8, #4, #4
; CHECK-NEXT: fmov s0, w10
diff --git a/llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll b/llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
index 8fe8873ec3e0a..8620c9a34b5d6 100644
--- a/llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
+++ b/llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
@@ -62,6 +62,7 @@ define <vscale x 4 x i32> @sti64ldi32(ptr nocapture %P, <vscale x 2 x i64> %v) {
; CHECK-LABEL: sti64ldi32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str z0, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
; CHECK-NEXT: ret
entry:
%0 = bitcast ptr %P to ptr
diff --git a/llvm/test/CodeGen/AArch64/sve-stlf.ll b/llvm/test/CodeGen/AArch64/sve-stlf.ll
deleted file mode 100644
index 7403da8298312..0000000000000
--- a/llvm/test/CodeGen/AArch64/sve-stlf.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s
-
-define <vscale x 4 x i32> @test_stlf_scalable(ptr %p, <vscale x 4 x i32> %v) {
-; CHECK-LABEL: test_stlf_scalable:
-; CHECK: // %bb.0:
-; CHECK-NEXT: str z0, [x0]
-; CHECK-NEXT: ret
- store <vscale x 4 x i32> %v, ptr %p
- %res = load <vscale x 4 x i32>, ptr %p
- ret <vscale x 4 x i32> %res
-}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
index baaf8c3d906c9..39f8aa104f484 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
@@ -639,7 +639,8 @@ define <1 x i64> @ctlz_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: clz x8, x8
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %op)
@@ -2308,7 +2309,8 @@ define <1 x i64> @ctpop_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: and x9, x9, #0xf0f0f0f0f0f0f0f
; NONEON-NOSVE-NEXT: mul x8, x9, x8
; NONEON-NOSVE-NEXT: lsr x8, x8, #56
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %op)
@@ -3187,7 +3189,8 @@ define <1 x i64> @cttz_v1i64(<1 x i64> %op) {
; NONEON-NOSVE-NEXT: fmov x8, d0
; NONEON-NOSVE-NEXT: rbit x8, x8
; NONEON-NOSVE-NEXT: clz x8, x8
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %op)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
index 85b09facb3285..72ea2f9bf3d87 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
@@ -451,7 +451,8 @@ define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcmp d0, d1
; NONEON-NOSVE-NEXT: csetm x8, eq
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%cmp = fcmp oeq <1 x double> %op1, %op2
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
index 4aea35dad369a..6c29666890bef 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
@@ -415,6 +415,8 @@ define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldr h0, [x0]
; NONEON-NOSVE-NEXT: fcvt d0, h0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: str d0, [x1]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
index 3f6050c079f9b..fddd5df323e46 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
@@ -591,6 +591,8 @@ define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmadd d0, d0, d1, d2
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%mul = fmul contract <1 x double> %op1, %op2
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
index 369b698f23eaf..e5266eb95f697 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
@@ -392,6 +392,8 @@ define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmaxnm d0, d0, d1
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2)
@@ -851,6 +853,8 @@ define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fminnm d0, d0, d1
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2)
@@ -1310,6 +1314,8 @@ define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmax d0, d0, d1
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2)
@@ -1769,6 +1775,8 @@ define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fmin d0, d0, d1
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
index f278423f9f85a..443cb93aa8ca1 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
@@ -355,6 +355,8 @@ define <1 x double> @frintp_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintp d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.ceil.v1f64(<1 x double> %op)
@@ -769,6 +771,8 @@ define <1 x double> @frintm_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintm d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.floor.v1f64(<1 x double> %op)
@@ -1183,6 +1187,8 @@ define <1 x double> @frinti_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frinti d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %op)
@@ -1597,6 +1603,8 @@ define <1 x double> @frintx_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintx d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.rint.v1f64(<1 x double> %op)
@@ -2011,6 +2019,8 @@ define <1 x double> @frinta_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frinta d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.round.v1f64(<1 x double> %op)
@@ -2425,6 +2435,8 @@ define <1 x double> @frintn_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintn d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %op)
@@ -2839,6 +2851,8 @@ define <1 x double> @frintz_v1f64(<1 x double> %op) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: frintz d0, d0
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call <1 x double> @llvm.trunc.v1f64(<1 x double> %op)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
index 11446df7dbe4f..eced98dda447a 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
@@ -379,6 +379,8 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: fcsel d0, d0, d1, ne
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
index 76aa8e45ccda3..21a26921ab031 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
@@ -433,7 +433,8 @@ define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvt s0, h0
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptoui <1 x half> %op1 to <1 x i64>
@@ -1638,7 +1639,8 @@ define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptoui <1 x double> %op1 to <1 x i64>
@@ -2131,7 +2133,8 @@ define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvt s0, h0
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptosi <1 x half> %op1 to <1 x i64>
@@ -3339,7 +3342,8 @@ define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = fptosi <1 x double> %op1 to <1 x i64>
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
index 1030e96939852..a08b71ce83ec1 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
@@ -482,6 +482,8 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1>
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: fcsel d0, d0, d1, ne
+; NONEON-NOSVE-NEXT: str d0, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
index 5f21c80c2fdd0..ad00e99b704dd 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
@@ -426,7 +426,8 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) {
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5
-; NONEON-NOSVE-NEXT: fmov d0, x8
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%r = insertelement <1 x i64> %op1, i64 5, i64 0
@@ -759,7 +760,9 @@ define <1 x double> @insertelement_v1f64(<1 x double> %op1) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
-; NONEON-NOSVE-NEXT: fmov d0, #5.00000000
+; NONEON-NOSVE-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000
+; NONEON-NOSVE-NEXT: str x8, [sp, #8]
+; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%r = insertelement <1 x double> %op1, double 5.0, i64 0
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
index 28980d3f08579..63b0242264678 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
@@ -658,7 +658,8 @@ define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: fmov x8, d1
; NONEON-NOSVE-NEXT: fmov x9, d0
; NONEON-NOSVE-NEXT: add x8, x9, x8
-; NONEON-NOSVE-NEXT: fmo...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/178872
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