[llvm] [ARM][AArch64] Replace manual CLS expansion with ISD::CTLS (PR #178430)

[Simon Pilgrim via llvm-commits]

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@@ -3845,12 +3852,14 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
         DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
     SDValue OR =
         DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
-    SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
-    return Result;
+    return DAG.getNode(ISD::CTLZ, dl, VTy, OR);
   }
   case Intrinsic::arm_cls64: {
-    // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
-    //          else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
+    // cls64(x) = if cls(hi(x)) != 31 then cls(hi(x))
+    //            else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
+    // Note: This intrinsic returns i32 but takes i64 input, so we handle
+    // it directly here rather than using ISD::CTLS which expects matching
+    // types.
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RKSimon wrote:

why not just truncate the CTLS result?

https://github.com/llvm/llvm-project/pull/178430