[llvm] ca7ecec - [X86] Add baseline tests exposing invalid masked folds. (#178411)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 29 22:49:30 PST 2026
Author: azwolski
Date: 2026-01-30T06:49:25Z
New Revision: ca7ececd7f61a47740a518bc5a86d3261b59c993
URL: https://github.com/llvm/llvm-project/commit/ca7ececd7f61a47740a518bc5a86d3261b59c993
DIFF: https://github.com/llvm/llvm-project/commit/ca7ececd7f61a47740a518bc5a86d3261b59c993.diff
LOG: [X86] Add baseline tests exposing invalid masked folds. (#178411)
This tests exposes invalid same-mask fold.
We need prevent folding the load into an "interleave‑type instruction",
because doing so removes the double mask application, which affects the
final result of the operation. For some instructions, folding the load
is simply invalid, even if the same mask is used. I have already
prepared a patch.
Few examples
```
EVEX.128.66.0F.WIG 67 /r VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128
A: 00010203 7F000001 80000002 DEADBEEF
E : 00000000 00000001 00000002 00000003
D: 11111111 22222222 33333333 44444444
k = 0x0400
Masked_e = 00000000 00000000 00000000 00000000 (vmovdqu8{k}{z} Masked_e E)
res1 = 00000000 00000000 00010000 00000000 (VPACKUSWB D{k}{z}, A, E)
res2 = 00000000 00000000 00000000 00000000 (VPACKUSWB D{k}{z}, A, Masked_e)
EVEX.128.66.0F38.W0 C4 /r VPCONFLICTD xmm1 {k1}{z}, xmm2/m128/m32bcst
A: DAA66D2B FFFFFFFC FFFFFFFC D9A0643C
E : 7DDF743F 00000000 5FD99E73 4ED634C9
D: 2629AB38 9E37782F 67BB800F AD66764A
k = 0x0002
Masked_e = (vmovdqu32 {k}{z} Masked_e E)
res1 = 00000000 00000000 00000000 00000000 (VPCONFLICTD D{k}{z}, E)
res2 = 00000000 00000001 00000000 00000000 (VPCONFLICTD D{k}{z}, Masked_e)
EVEX.128.66.0F38.W1 8D /r VPERMW xmm1 {k1}{z}, xmm2, xmm3/m128
A: 00010203 7F000001 80000002 DEADBEEF
E : 00000000 00000001 00000002 00000003
D: 11111111 22222222 33333333 44444444
k = 0x0010
Masked_e = 00000000 00000000 00000002 00000000 (vmovdqu16 {k}{z} Masked_e E)
res1 = 00000000 00000000 00000001 00000000 (vpermw D{k}{z}, A, E)
res2 = 00000000 00000000 00000000 00000000 (vpermw D{k}{z}, A, Masked_e)
EVEX.128.66.0F38.W0 78 /r VPBROADCASTB xmm1{k1}{z}, xmm2/m8
E : 7F4A7C15 6E490933 5D4C9659 4C433CE3
D: F63F9D36 97F6E2B2 9432E8E6 FAEE7A3E
k = 0x0002
Masked_e = 00007C00 00000000 00000000 00000000 (vmovdqu8{k}{z} Masked_e E)
res = 00001500 00000000 00000000 00000000 (vpbroadcastb D{k}{z}, E)
res = 00000000 00000000 00000000 00000000 (vpbroadcastb D{k}{z}, Masked_e)
```
Added:
llvm/test/CodeGen/X86/interleave-load-fold.ll
llvm/test/CodeGen/X86/non-foldable-with-the-same-mask.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/interleave-load-fold.ll b/llvm/test/CodeGen/X86/interleave-load-fold.ll
new file mode 100644
index 0000000000000..28f313bf6a0fa
--- /dev/null
+++ b/llvm/test/CodeGen/X86/interleave-load-fold.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -O2 -mcpu=skylake-avx512 < %s -o - | FileCheck %s --check-prefixes=X64
+
+define <16 x i8> @interleave_masked_select(ptr %mask, ptr %src) nounwind {
+; X64-LABEL: interleave_masked_select:
+; X64: # %bb.0:
+; X64-NEXT: kmovw (%rdi), %k1
+; X64-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; X64-NEXT: vpunpcklbw {{.*#+}} xmm0 {%k1} {z} = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3],xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7]
+; X64-NEXT: retq
+ %mask_vec = load <16 x i1>, ptr %mask
+ %vec2 = load <16 x i8>, ptr %src
+ %selected = select <16 x i1> %mask_vec, <16 x i8> %vec2, <16 x i8> splat (i8 1)
+ %interleaved = shufflevector <16 x i8> zeroinitializer, <16 x i8> %selected, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+ %masked = select <16 x i1> %mask_vec, <16 x i8> %interleaved, <16 x i8> zeroinitializer
+ ret <16 x i8> %masked
+}
+
+define <16 x i1> @interleave_masked_blend(i16 %mask, ptr %src1, ptr %src2) nounwind {
+; X64-LABEL: interleave_masked_blend:
+; X64: # %bb.0:
+; X64-NEXT: vmovdqa (%rsi), %xmm0
+; X64-NEXT: kmovd %edi, %k1
+; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X64-NEXT: vpunpcklbw {{.*#+}} xmm2 {%k1} {z} = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3],xmm1[4],mem[4],xmm1[5],mem[5],xmm1[6],mem[6],xmm1[7],mem[7]
+; X64-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; X64-NEXT: vpcmpeqb %xmm0, %xmm2, %xmm0
+; X64-NEXT: retq
+ %mask_vec = bitcast i16 %mask to <16 x i1>
+ %vec1 = load <16 x i8>, ptr %src1
+ %vec2 = load <16 x i8>, ptr %src2
+ %blended = select <16 x i1> %mask_vec, <16 x i8> %vec2, <16 x i8> %vec1
+ %interleaved1 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %blended, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+ %masked = select <16 x i1> %mask_vec, <16 x i8> %interleaved1, <16 x i8> zeroinitializer
+ %interleaved2 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %vec1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+ %cmp = icmp eq <16 x i8> %masked, %interleaved2
+ ret <16 x i1> %cmp
+}
diff --git a/llvm/test/CodeGen/X86/non-foldable-with-the-same-mask.mir b/llvm/test/CodeGen/X86/non-foldable-with-the-same-mask.mir
new file mode 100644
index 0000000000000..3281218848c0a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/non-foldable-with-the-same-mask.mir
@@ -0,0 +1,874 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=x86_64-- -mcpu=skylake-avx512 -run-pass=peephole-opt %s -o - | FileCheck %s
+
+---
+name: test_valignd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_valignd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VALIGNDZ128rmik:%[0-9]+]]:vr128 = VALIGNDZ128rmik [[AVX512_128_SET0_]], [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 1 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VALIGNDZ128rmik]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VALIGNDZ128rrik %1, %0, %3, %2, 1
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpalignr_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk16wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpalignr_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPALIGNRZ128rmikz:%[0-9]+]]:vr128 = VPALIGNRZ128rmikz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 4 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPALIGNRZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk16wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU8Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VPALIGNRZ128rrikz %0, %3, %2, 4
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vbroadcastss_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vbroadcastss_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VBROADCASTSSZ128rmk:%[0-9]+]]:vr128 = VBROADCASTSSZ128rmk [[AVX512_128_SET0_]], [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VBROADCASTSSZ128rmk]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VBROADCASTSSZ128rrk %1, %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vmovddup_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk2wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vmovddup_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk2wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VMOVDDUPZ128rmkz:%[0-9]+]]:vr128 = VMOVDDUPZ128rmkz [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VMOVDDUPZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk2wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPDZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VMOVDDUPZ128rrkz %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vmovshdup_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vmovshdup_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VMOVSHDUPZ128rmkz:%[0-9]+]]:vr128 = VMOVSHDUPZ128rmkz [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VMOVSHDUPZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VMOVSHDUPZ128rrkz %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vpbroadcastd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpbroadcastd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPBROADCASTDZ128rmkz:%[0-9]+]]:vr128 = VPBROADCASTDZ128rmkz [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPBROADCASTDZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VPBROADCASTDZ128rrkz %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vdbpsadbw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vdbpsadbw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VDBPSADBWZ128rmikz:%[0-9]+]]:vr128 = VDBPSADBWZ128rmikz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 0 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VDBPSADBWZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VDBPSADBWZ128rrikz %0, %3, %2, 0
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vgf2p8affineqb_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk16wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vgf2p8affineqb_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VGF2P8AFFINEQBZ128rmikz:%[0-9]+]]:vr128 = VGF2P8AFFINEQBZ128rmikz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 0 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VGF2P8AFFINEQBZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk16wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU8Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VGF2P8AFFINEQBZ128rrikz %0, %3, %2, 0
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vmpsadbw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vmpsadbw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VMPSADBWZ128rmikz:%[0-9]+]]:vr128 = VMPSADBWZ128rmikz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 0 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VMPSADBWZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VMPSADBWZ128rrikz %0, %3, %2, 0
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpconflictd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpconflictd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPCONFLICTDZ128rmk:%[0-9]+]]:vr128 = VPCONFLICTDZ128rmk [[AVX512_128_SET0_]], [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPCONFLICTDZ128rmk]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VPCONFLICTDZ128rrk %1, %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vpmultishiftqb_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk16wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpmultishiftqb_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPMULTISHIFTQBZ128rmkz:%[0-9]+]]:vr128 = VPMULTISHIFTQBZ128rmkz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPMULTISHIFTQBZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk16wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU8Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VPMULTISHIFTQBZ128rrkz %0, %3, %2
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vexpandps_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vexpandps_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VEXPANDPSZ128rmk:%[0-9]+]]:vr128 = VEXPANDPSZ128rmk [[AVX512_128_SET0_]], [[COPY]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VEXPANDPSZ128rmk]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VEXPANDPSZ128rrk %1, %0, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vinserti32x4_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr256x }
+ - { id: 2, class: vr256x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr256 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vinserti32x4_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_256_SET0_:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[AVX512_256_SET0_1:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[VINSERTI32X4Z256rmikz:%[0-9]+]]:vr256 = VINSERTI32X4Z256rmikz [[COPY]], [[AVX512_256_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 1 :: (load (s128))
+ ; CHECK-NEXT: $ymm0 = COPY [[VINSERTI32X4Z256rmikz]]
+ ; CHECK-NEXT: RET 0, $ymm0
+ %0:vk4wm = COPY $k1
+ %1:vr256x = AVX512_256_SET0
+ %2:vr256x = AVX512_256_SET0
+ %3:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %4:vr256 = VINSERTI32X4Z256rrikz %0, %2, %3, 1
+ $ymm0 = COPY %4
+ RET 0, $ymm0
+...
+---
+name: test_vpackssdw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpackssdw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPACKSSDWZ128rmk:%[0-9]+]]:vr128 = VPACKSSDWZ128rmk [[AVX512_128_SET0_]], [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPACKSSDWZ128rmk]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VPACKSSDWZ128rrk %1, %0, %3, %2
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpermd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr256x }
+ - { id: 2, class: vr256x }
+ - { id: 3, class: vr256x }
+ - { id: 4, class: vr256 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_256_SET0_:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[AVX512_256_SET0_1:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[VPERMDZ256rmk:%[0-9]+]]:vr256 = VPERMDZ256rmk [[AVX512_256_SET0_]], [[COPY]], [[AVX512_256_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s256))
+ ; CHECK-NEXT: $ymm0 = COPY [[VPERMDZ256rmk]]
+ ; CHECK-NEXT: RET 0, $ymm0
+ %0:vk8wm = COPY $k1
+ %1:vr256x = AVX512_256_SET0
+ %2:vr256x = VMOVDQA32Z256rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s256))
+ %3:vr256x = AVX512_256_SET0
+ %4:vr256 = VPERMDZ256rrk %1, %0, %3, %2
+ $ymm0 = COPY %4
+ RET 0, $ymm0
+...
+---
+name: test_vpermi2d_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128x }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermi2d_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPERMI2DZ128rmkz:%[0-9]+]]:vr128x = VPERMI2DZ128rmkz [[AVX512_128_SET0_]], [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPERMI2DZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128x = VPERMI2DZ128rrkz %1, %0, %3, %2
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpermilps_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermilps_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[VPERMILPSZ128mikz:%[0-9]+]]:vr128 = VPERMILPSZ128mikz [[COPY]], $rdi, 1, $noreg, 0, $noreg, 27 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPERMILPSZ128mikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %2:vr128 = VPERMILPSZ128rikz %0, %1, 27
+ $xmm0 = COPY %2
+ RET 0, $xmm0
+...
+---
+name: test_vpermps_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr256x }
+ - { id: 2, class: vr256x }
+ - { id: 3, class: vr256x }
+ - { id: 4, class: vr256 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermps_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_256_SET0_:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[AVX512_256_SET0_1:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[VPERMPSZ256rmkz:%[0-9]+]]:vr256 = VPERMPSZ256rmkz [[COPY]], [[AVX512_256_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s256))
+ ; CHECK-NEXT: $ymm0 = COPY [[VPERMPSZ256rmkz]]
+ ; CHECK-NEXT: RET 0, $ymm0
+ %0:vk8wm = COPY $k1
+ %1:vr256x = AVX512_256_SET0
+ %2:vr256x = VMOVAPSZ256rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s256))
+ %3:vr256x = AVX512_256_SET0
+ %4:vr256 = VPERMPSZ256rrkz %0, %3, %2
+ $ymm0 = COPY %4
+ RET 0, $ymm0
+...
+---
+name: test_vpermt2d_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128x }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermt2d_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPERMT2DZ128rmkz:%[0-9]+]]:vr128x = VPERMT2DZ128rmkz [[AVX512_128_SET0_]], [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPERMT2DZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128x = VPERMT2DZ128rrkz %1, %0, %3, %2
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpermw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128x }
+ - { id: 4, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpermw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[AVX512_128_SET0_1:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPERMWZ128rmkz:%[0-9]+]]:vr128 = VPERMWZ128rmkz [[COPY]], [[AVX512_128_SET0_1]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPERMWZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128x = AVX512_128_SET0
+ %4:vr128 = VPERMWZ128rrkz %0, %3, %2
+ $xmm0 = COPY %4
+ RET 0, $xmm0
+...
+---
+name: test_vpshufd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpshufd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[VPSHUFDZ128mikz:%[0-9]+]]:vr128 = VPSHUFDZ128mikz [[COPY]], $rdi, 1, $noreg, 0, $noreg, 27 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPSHUFDZ128mikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = VMOVDQA32Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %2:vr128 = VPSHUFDZ128rikz %0, %1, 27
+ $xmm0 = COPY %2
+ RET 0, $xmm0
+...
+---
+name: test_vpshufhw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpshufhw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[VPSHUFHWZ128mikz:%[0-9]+]]:vr128 = VPSHUFHWZ128mikz [[COPY]], $rdi, 1, $noreg, 0, $noreg, 27 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPSHUFHWZ128mikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %2:vr128 = VPSHUFHWZ128rikz %0, %1, 27
+ $xmm0 = COPY %2
+ RET 0, $xmm0
+...
+---
+name: test_vpshuflw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpshuflw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[VPSHUFLWZ128mikz:%[0-9]+]]:vr128 = VPSHUFLWZ128mikz [[COPY]], $rdi, 1, $noreg, 0, $noreg, 27 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPSHUFLWZ128mikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk8wm = COPY $k1
+ %1:vr128x = VMOVDQU16Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %2:vr128 = VPSHUFLWZ128rikz %0, %1, 27
+ $xmm0 = COPY %2
+ RET 0, $xmm0
+...
+---
+name: test_vshuff32x4_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk8wm }
+ - { id: 1, class: vr256x }
+ - { id: 2, class: vr256x }
+ - { id: 3, class: vr256x }
+ - { id: 4, class: vr256 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vshuff32x4_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk8wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_256_SET0_:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[AVX512_256_SET0_1:%[0-9]+]]:vr256x = AVX512_256_SET0
+ ; CHECK-NEXT: [[VSHUFF32X4Z256rmikz:%[0-9]+]]:vr256 = VSHUFF32X4Z256rmikz [[COPY]], [[AVX512_256_SET0_1]], $rdi, 1, $noreg, 0, $noreg, 2 :: (load (s256))
+ ; CHECK-NEXT: $ymm0 = COPY [[VSHUFF32X4Z256rmikz]]
+ ; CHECK-NEXT: RET 0, $ymm0
+ %0:vk8wm = COPY $k1
+ %1:vr256x = AVX512_256_SET0
+ %2:vr256x = VMOVAPSZ256rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s256))
+ %3:vr256x = AVX512_256_SET0
+ %4:vr256 = VSHUFF32X4Z256rrikz %0, %3, %2, 2
+ $ymm0 = COPY %4
+ RET 0, $ymm0
+...
+---
+name: test_vshufpd_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk2wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vshufpd_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk2wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VSHUFPDZ128rmikz:%[0-9]+]]:vr128 = VSHUFPDZ128rmikz [[COPY]], [[AVX512_128_SET0_]], $rdi, 1, $noreg, 0, $noreg, 1 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VSHUFPDZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk2wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPDZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VSHUFPDZ128rrikz %0, %1, %2, 1
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vshufps_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vshufps_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VSHUFPSZ128rmikz:%[0-9]+]]:vr128 = VSHUFPSZ128rmikz [[COPY]], [[AVX512_128_SET0_]], $rdi, 1, $noreg, 0, $noreg, 68 :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VSHUFPSZ128rmikz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VSHUFPSZ128rrikz %0, %1, %2, 68
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vpunpckhbw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk16wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpunpckhbw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPUNPCKHBWZ128rmkz:%[0-9]+]]:vr128 = VPUNPCKHBWZ128rmkz [[COPY]], [[AVX512_128_SET0_]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPUNPCKHBWZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk16wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU8Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VPUNPCKHBWZ128rrkz %0, %1, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vpunpcklbw_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk16wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vpunpcklbw_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk16wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VPUNPCKLBWZ128rmkz:%[0-9]+]]:vr128 = VPUNPCKLBWZ128rmkz [[COPY]], [[AVX512_128_SET0_]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VPUNPCKLBWZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk16wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVDQU8Z128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VPUNPCKLBWZ128rrkz %0, %1, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
+---
+name: test_vunpcklps_same_mask
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vk4wm }
+ - { id: 1, class: vr128x }
+ - { id: 2, class: vr128x }
+ - { id: 3, class: vr128 }
+liveins:
+ - { reg: '$rdi' }
+ - { reg: '$k1' }
+body: |
+ bb.0:
+ liveins: $rdi, $k1
+ ; CHECK-LABEL: name: test_vunpcklps_same_mask
+ ; CHECK: liveins: $rdi, $k1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vk4wm = COPY $k1
+ ; CHECK-NEXT: [[AVX512_128_SET0_:%[0-9]+]]:vr128x = AVX512_128_SET0
+ ; CHECK-NEXT: [[VUNPCKLPSZ128rmkz:%[0-9]+]]:vr128 = VUNPCKLPSZ128rmkz [[COPY]], [[AVX512_128_SET0_]], $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ ; CHECK-NEXT: $xmm0 = COPY [[VUNPCKLPSZ128rmkz]]
+ ; CHECK-NEXT: RET 0, $xmm0
+ %0:vk4wm = COPY $k1
+ %1:vr128x = AVX512_128_SET0
+ %2:vr128x = VMOVAPSZ128rmkz %0, $rdi, 1, $noreg, 0, $noreg :: (load (s128))
+ %3:vr128 = VUNPCKLPSZ128rrkz %0, %1, %2
+ $xmm0 = COPY %3
+ RET 0, $xmm0
+...
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