[llvm] [AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (PR #175257)

[Anshil Gandhi via llvm-commits]

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@@ -932,6 +932,17 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{B64, Ptr32}, {{}, {VgprB64, VgprPtr32}}})
       .Any({{B96, Ptr32}, {{}, {VgprB96, VgprPtr32}}})
       .Any({{B128, Ptr32}, {{}, {VgprB128, VgprPtr32}}});
+
+  // Atomics always operate per-lane; keep both the pointer and the value/result
+  // in VGPRs regardless of uniformity. Use Ptr32/Ptr64 to cover all addrspaces
+  // (e.g. local/region/private for Ptr32, global/flat for Ptr64).
+  addRulesForGOpcs({G_ATOMICRMW_FADD})
+      .Any({{B32, Ptr32, B32}, {{VgprB32}, {VgprPtr32, VgprB32}}})
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gandhi56 wrote:

Pushed a revision:
* Exclusively only allow divergent results, for Ptr32 and Ptr64 input operands.
* Verified that there is a test for Ptr32 and Ptr64 in regbankselect-atomicrmw-fadd.mir.

https://github.com/llvm/llvm-project/pull/175257