[llvm] [AMDGPU] Fix uniform parameter pass using vgpr (PR #178198)

[Matt Arsenault via llvm-commits]

================
@@ -3550,6 +3553,11 @@ SDValue SITargetLowering::LowerFormalArguments(
 
     Reg = MF.addLiveIn(Reg, RC);
     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
+    if (Arg.Flags.isInReg() && RC == &AMDGPU::VGPR_32RegClass) {
+      SmallVector<SDValue, 3> ReadfirstlaneArgs({ReadFirstLaneID, Val});
+      Val = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Val.getValueType(),
+                        ReadfirstlaneArgs);
----------------
arsenm wrote:

```suggestion
      Val = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Val.getValueType(),
                        ReadFirstLaneID, Val);
```

https://github.com/llvm/llvm-project/pull/178198