[llvm] [RISCV] Add macro fusion support for spacemit-x100 (PR #178594)

[Craig Topper via llvm-commits]

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@@ -147,3 +155,118 @@ def TuneSHXADDLoadFusion
                  "Enable SH(1|2|3)ADD(.UW) + load macrofusion",
                  CheckOpcode<[SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW]>,
                  CheckOpcode<Load>>;
+
+// Fuse logic operation followed by another logic operation:
+//   and/or/xor rd, rs1, rs2
+//   and/or/xor rd, rd, rs3
+let IsCommutable = 1 in
+def TuneLogicRegRegFusion
+  : SimpleFusion<"logic-reg-reg-fusion", "HasLogicRegRegFusion",
+                 "Enable AND/OR/XOR+AND/OR/XOR macrofusion",
+                 CheckOpcode<LogicOp>,
+                 CheckOpcode<LogicOp>>;
+
+// Fuse logic operation followed by logic immediate operation:
+//   and/or/xor rd, rs1, rs2
+//   andi/ori/xori rd, rd, imm
+def TuneLogicRegImmFusion
+  : SimpleFusion<"logic-reg-imm-fusion", "HasLogicRegImmFusion",
+                 "Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion",
+                 CheckOpcode<LogicOp>,
+                 CheckOpcode<LogicImmOp>>;
+
+// Fuse logic immediate operation followed by logic operation:
+//   andi/ori/xori rd, rs1, imm
+//   and/or/xor rd, rd, rs2
+let IsCommutable = 1 in
+def TuneLogicImmRegFusion
+  : SimpleFusion<"logic-imm-reg-fusion", "HasLogicImmRegFusion",
+                 "Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion",
+                 CheckOpcode<LogicImmOp>,
+                 CheckOpcode<LogicOp>>;
+
+// Fuse multiply followed by add:
+//   mul(w) rd, rs1, rs2
+//   add(w) rd, rd, rs3
+def TuneMulAddFusion
+  : Fusion<"mul-add-fusion", "HasMulAddFusion",
+           "Enable MUL+ADD macrofusion",
+           [
+             SecondFusionPredicateWithMCInstPredicate<
+               CheckOpcode<[ADD, ADDW]>
+             >,
+             WildcardTrue,
+             FirstFusionPredicateWithMCInstPredicate<
+               CheckOpcode<[MUL, MULW]>
+             >,
+             // Check that both instructions have the same width
+             FusionPredicateWithCode<[{
+               if ((FirstMI->getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask) ^
----------------
topperc wrote:

Use `!=` insead of `^`

https://github.com/llvm/llvm-project/pull/178594