[llvm] [SDAG] Use the precise isTruncFree overload more often (PR #176575)

[via llvm-commits]

https://github.com/DaKnig updated https://github.com/llvm/llvm-project/pull/176575

>From d4a9cd74bfb059eb7d0f95a0f5815c7df397c3dd Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sat, 17 Jan 2026 17:26:42 +0200
Subject: [PATCH] [SDAG] Use the precise isTruncFree overload more often

Using the `isTruncFree(SDValue, EVT)` overload lets us have more
precise knowledge of when it is free to truncate.

This is in preparation for a stronger default overload for this method.
---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5cdceb02897e7..40ffe3f167897 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1887,7 +1887,8 @@ bool TargetLowering::SimplifyDemandedBits(
           EVT SmallVT = EVT::getIntegerVT(*TLO.DAG.getContext(), SmallVTBits);
           if (isNarrowingProfitable(Op.getNode(), VT, SmallVT) &&
               isTypeDesirableForOp(ISD::SHL, SmallVT) &&
-              isTruncateFree(VT, SmallVT) && isZExtFree(SmallVT, VT) &&
+              isTruncateFree(Op.getOperand(0), SmallVT) &&
+              isZExtFree(SmallVT, VT) &&
               (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, SmallVT))) {
             assert(DemandedSize <= SmallVTBits &&
                    "Narrowed below demanded bits?");
@@ -1911,7 +1912,7 @@ bool TargetLowering::SimplifyDemandedBits(
         EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), HalfWidth);
         if (isNarrowingProfitable(Op.getNode(), VT, HalfVT) &&
             isTypeDesirableForOp(ISD::SHL, HalfVT) &&
-            isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) &&
+            isTruncateFree(Op0, HalfVT) && isZExtFree(HalfVT, VT) &&
             (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) {
           // If we're demanding the upper bits at all, we must ensure
           // that the upper bits of the shift result are known to be zero,
@@ -2025,7 +2026,7 @@ bool TargetLowering::SimplifyDemandedBits(
         EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), BitWidth / 2);
         if (isNarrowingProfitable(Op.getNode(), VT, HalfVT) &&
             isTypeDesirableForOp(ISD::SRL, HalfVT) &&
-            isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) &&
+            isTruncateFree(Op0, HalfVT) && isZExtFree(HalfVT, VT) &&
             (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) &&
             ((InDemandedMask.countLeadingZeros() >= (BitWidth / 2)) ||
              TLO.DAG.MaskedValueIsZero(Op0, HiBits))) {
@@ -4161,12 +4162,12 @@ SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
   // TODO: This conservatively checks for type legality on the source and
   //       destination types. That may inhibit optimizations, but it also
   //       allows setcc->shift transforms that may be more beneficial.
-  auto *AndC = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  auto *AndC = isConstOrConstSplat(N0.getOperand(1), true);
   if (AndC && isNullConstant(N1) && AndC->getAPIntValue().isPowerOf2() &&
       isTypeLegal(OpVT) && N0.hasOneUse()) {
     EVT NarrowVT = EVT::getIntegerVT(*DAG.getContext(),
                                      AndC->getAPIntValue().getActiveBits());
-    if (isTruncateFree(OpVT, NarrowVT) && isTypeLegal(NarrowVT)) {
+    if (isTypeLegal(NarrowVT) && isTruncateFree(N0.getOperand(0), NarrowVT)) {
       SDValue Trunc = DAG.getZExtOrTrunc(N0.getOperand(0), DL, NarrowVT);
       SDValue Zero = DAG.getConstant(0, DL, NarrowVT);
       return DAG.getSetCC(DL, VT, Trunc, Zero,