[llvm] [AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bit register pair (PR #177662)

[via llvm-commits]

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@@ -16852,6 +16849,58 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
           return LHS.getOperand(0);
       }
     }
+
+    // Fold setcc patterns which test only upper 32 bits of operand
+    // hi64 = v.64 & 0x????'????'0000'0000
+    // setcc hi64, (x.32 << 32), op
+    //  =>
+    // mask.32 = v.hi32 & 0x????'????
+    // setcc mask.32, x.32, op
+    if (VT == MVT::i64) {
+      const uint64_t CRHSInt = CRHSVal.getZExtValue();
+
+      const uint64_t Mask32 = maskTrailingOnes<uint64_t>(32);
+      const uint64_t Bit32 = Mask32 + 1;
+
+      ISD::CondCode HiCC = ISD::SETCC_INVALID;
+      uint32_t HiConstant = 0;
+
+      // Handle special case of comparisons with 1 << 32 or (1 << 32) - 1
+      // In this case, isolating the higher bits of v.64 with a mask are not
+      // necessary.
+      //
+      // setcc v.64, 0x1'0000'0000, ult => setcc v.hi32, 0, eq
+      // setcc v.64, 0x1'0000'0000, uge => setcc v.hi32, 0, ne
+      // setcc v.64, 0xffff'ffff, ule   => setcc v.hi32, 0, eq
+      // setcc v.64, 0xffff'ffff, ugt   => setcc v.hi32, 0, ne
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zGoldthorpe wrote:

You're right; that makes much more sense as the generalisation. I'll remove my not-generalisation and adapt the patch to this.

https://github.com/llvm/llvm-project/pull/177662