[llvm] [AMDGPU] Remove `NoSignedZerosFPMath` uses (PR #178343)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 28 04:06:17 PST 2026
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/178343
>From bfa88f4feb9bf6f264e6d71976dd91a23e33f107 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Wed, 28 Jan 2026 10:37:21 +0800
Subject: [PATCH 1/3] [AMDGPU] Remove `NoSignedZerosFPMath` uses
---
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp | 3 +--
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 6 +-----
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | 5 -----
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h | 6 ------
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 4 +---
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 6 ++----
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 2 --
7 files changed, 5 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index d23521c87e202..77be58c533671 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -143,8 +143,7 @@ static bool allUsesHaveSourceMods(MachineInstr &MI, MachineRegisterInfo &MRI,
}
static bool mayIgnoreSignedZero(MachineInstr &MI) {
- const TargetOptions &Options = MI.getMF()->getTarget().Options;
- return Options.NoSignedZerosFPMath || MI.getFlag(MachineInstr::MIFlag::FmNsz);
+ return MI.getFlag(MachineInstr::MIFlag::FmNsz);
}
static bool isInv2Pi(const APFloat &APF) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index c5dc82ed619b0..5a6da9f55e657 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -631,9 +631,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
}
bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {
- if (getTargetMachine().Options.NoSignedZerosFPMath)
- return true;
-
const auto Flags = Op.getNode()->getFlags();
if (Flags.hasNoSignedZeros())
return true;
@@ -2565,11 +2562,10 @@ SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
SDLoc SL(Op);
SDValue X = Op.getOperand(0);
EVT VT = Op.getValueType();
+ SelectionDAG::FlagInserter Inserter(DAG, Op->getFlags());
SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
- // TODO: Should this propagate fast-math-flags?
-
SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
index 6606c31dd248a..1730757c3d573 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
@@ -80,11 +80,6 @@ AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F,
if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL)
ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign);
- // FIXME: Shouldn't be target specific
- Attribute NSZAttr = F.getFnAttribute("no-signed-zeros-fp-math");
- NoSignedZerosFPMath =
- NSZAttr.isStringAttribute() && NSZAttr.getValueAsString() == "true";
-
const GlobalVariable *DynLdsGlobal = getKernelDynLDSGlobalFromFunction(F);
if (DynLdsGlobal || hasLDSKernelArgument(F))
UsesDynamicLDS = true;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
index fc64e16ffbeb8..1317210a445d2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
@@ -61,8 +61,6 @@ class AMDGPUMachineFunction : public MachineFunctionInfo {
// Functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve CC.
bool IsChainFunction = false;
- bool NoSignedZerosFPMath = false;
-
// Function may be memory bound.
bool MemoryBound = false;
@@ -107,10 +105,6 @@ class AMDGPUMachineFunction : public MachineFunctionInfo {
return isEntryFunction() || isChainFunction();
}
- bool hasNoSignedZerosFPMath() const {
- return NoSignedZerosFPMath;
- }
-
bool isMemoryBound() const {
return MemoryBound;
}
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 17d7514c30a00..3f72b65e8148a 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2773,7 +2773,6 @@ bool SIFoldOperandsImpl::run(MachineFunction &MF) {
//
// FIXME: Also need to check strictfp
bool IsIEEEMode = MFI->getMode().IEEE;
- bool HasNSZ = MFI->hasNoSignedZerosFPMath();
bool Changed = false;
for (MachineBasicBlock *MBB : depth_first(&MF)) {
@@ -2812,8 +2811,7 @@ bool SIFoldOperandsImpl::run(MachineFunction &MF) {
// TODO: Omod might be OK if there is NSZ only on the source
// instruction, and not the omod multiply.
- if (IsIEEEMode || (!HasNSZ && !MI.getFlag(MachineInstr::FmNsz)) ||
- !tryFoldOMod(MI))
+ if (IsIEEEMode || !MI.getFlag(MachineInstr::FmNsz) || !tryFoldOMod(MI))
Changed |= tryFoldClamp(MI);
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index d484d33f8d8c4..c819c5641dbcf 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -744,9 +744,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
: ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
GDSSize(MFI.getGDSSize()), DynLDSAlign(MFI.getDynLDSAlign()),
- IsEntryFunction(MFI.isEntryFunction()),
- NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
- MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
+ IsEntryFunction(MFI.isEntryFunction()), MemoryBound(MFI.isMemoryBound()),
+ WaveLimiter(MFI.needsWaveLimiter()),
HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
NumWaveDispatchSGPRs(MFI.getNumWaveDispatchSGPRs()),
@@ -803,7 +802,6 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
Occupancy = YamlMFI.Occupancy;
IsEntryFunction = YamlMFI.IsEntryFunction;
- NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
MemoryBound = YamlMFI.MemoryBound;
WaveLimiter = YamlMFI.WaveLimiter;
HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index d901f4c216551..617862db8f506 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -267,7 +267,6 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
Align DynLDSAlign;
bool IsEntryFunction = false;
bool IsChainFunction = false;
- bool NoSignedZerosFPMath = false;
bool MemoryBound = false;
bool WaveLimiter = false;
bool HasSpilledSGPRs = false;
@@ -328,7 +327,6 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
YamlIO.mapOptional("isChainFunction", MFI.IsChainFunction, false);
- YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
>From 004e30244c5b8312d2ffc5cb0c2e8c8a44c8687d Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Wed, 28 Jan 2026 17:58:17 +0800
Subject: [PATCH 2/3] consider fmf from fneg
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 5a6da9f55e657..e014c2ad8a402 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5003,7 +5003,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
SDLoc SL(N);
switch (Opc) {
case ISD::FADD: {
- if (!mayIgnoreSignedZero(N0))
+ if (!mayIgnoreSignedZero(N0) && !N->getFlags().hasNoSignedZeros())
return SDValue();
// (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
@@ -5051,7 +5051,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
case ISD::FMA:
case ISD::FMAD: {
// TODO: handle llvm.amdgcn.fma.legacy
- if (!mayIgnoreSignedZero(N0))
+ if (!mayIgnoreSignedZero(N0) && !N->getFlags().hasNoSignedZeros())
return SDValue();
// (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
>From d14f6cf4d8367c9101c36d8324b6f9f178a971b0 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Wed, 28 Jan 2026 19:03:30 +0800
Subject: [PATCH 3/3] Fix tests
---
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 4828 ++++--------
llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 6863 +++++++++--------
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 1328 ++--
llvm/test/CodeGen/AMDGPU/omod.ll | 32 +-
.../AMDGPU/select-fabs-fneg-extract.f16.ll | 1341 +---
.../AMDGPU/select-fabs-fneg-extract.ll | 2489 +++++-
.../AMDGPU/long-branch-reg-all-sgpr-used.ll | 2 -
.../AMDGPU/machine-function-info-after-pei.ll | 1 -
...ine-function-info-long-branch-reg-debug.ll | 1 -
.../machine-function-info-long-branch-reg.ll | 1 -
.../AMDGPU/machine-function-info-no-ir.mir | 5 -
.../MIR/AMDGPU/machine-function-info.ll | 4 -
.../preserve-machine-function-info-amdgpu.mir | 2 -
13 files changed, 8122 insertions(+), 8775 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index 16ec854a12c53..1ae7cf2187b1d 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -1,83 +1,72 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=SI,SI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=SI,SI-NSZ %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI,VI-NSZ %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=VI %s
; FIXME-TRUE16. fix true16 test
-; XUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-FAKE16 %s
-; XUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-FAKE16 %s
+; XUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-SAFE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11 %s
; --------------------------------------------------------------------------------
; fadd tests
; --------------------------------------------------------------------------------
define half @v_fneg_add_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_add_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%add = fadd half %a, %b
%fneg = fneg half %add
ret half %fneg
}
+define half @v_fneg_add_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e64 v0, -v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd nsz half %a, %b
+ %fneg = fneg nsz half %add
+ ret half %fneg
+}
+
define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {
; SI-LABEL: v_fneg_add_store_use_add_f16:
; SI: ; %bb.0:
@@ -124,78 +113,66 @@ define { half, half } @v_fneg_add_store_use_add_f16(half %a, half %b) #0 {
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_add_store_use_add_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_store_use_add_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v1, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_store_use_add_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v1, v0, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_store_use_add_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd half %a, %b
+ %fneg = fneg half %add
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %add, 1
+ ret { half, half } %insert.1
+}
+
define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_multi_use_add_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 4.0, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_multi_use_add_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v1, -v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_multi_use_add_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v1, v0, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; VI-NEXT: v_mul_f16_e32 v1, 4.0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f16_e32 v1, v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; VI-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v1
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_multi_use_add_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
-; VI-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_add_f16_e32 v1, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; GFX11-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v1
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_add_f16_e32 v0.h, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, 4.0, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_add_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_add_multi_use_add_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; GFX11-NEXT: v_mul_f16_e32 v1, 4.0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%add = fadd half %a, %b
%fneg = fneg half %add
%use1 = fmul half %add, 4.0
@@ -205,274 +182,247 @@ define { half, half } @v_fneg_add_multi_use_add_f16(half %a, half %b) #0 {
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_add_multi_use_add_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_multi_use_add_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_multi_use_add_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e64 v0, -v0, v1
+; VI-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_multi_use_add_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd nsz half %a, %b
+ %fneg = fneg nsz half %add
+ %use1 = fmul nsz half %add, 4.0
+
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1
+ ret { half, half } %insert.1
+}
+
define half @v_fneg_add_fneg_x_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_fneg_x_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_fneg_x_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_fneg_x_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_fneg_x_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v0, v1, v0
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_fneg_x_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_sub_f16_e32 v0, v1, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_fneg_x_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e32 v0, v0, v1
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_add_fneg_x_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%add = fadd half %fneg.a, %b
%fneg = fneg half %add
ret half %fneg
}
-define half @v_fneg_add_x_fneg_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_x_fneg_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+define half @v_fneg_add_fneg_x_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_fneg_x_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_x_fneg_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_fneg_x_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_x_fneg_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_sub_f16_e32 v0, v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_x_fneg_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e32 v0, v1, v0
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_x_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
- %fneg.b = fneg half %b
- %add = fadd half %a, %fneg.b
- %fneg = fneg half %add
+; GFX11-LABEL: v_fneg_add_fneg_x_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg nsz half %a
+ %add = fadd nsz half %fneg.a, %b
+ %fneg = fneg nsz half %add
ret half %fneg
}
-define half @v_fneg_add_fneg_fneg_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+define half @v_fneg_add_x_fneg_f16(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_x_fneg_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_x_fneg_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v0, v0, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_sub_f16_e64 v0, -v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_sub_f16_e64 v0, -v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
- %fneg.a = fneg half %a
+; GFX11-LABEL: v_fneg_add_x_fneg_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg half %b
- %add = fadd half %fneg.a, %fneg.b
+ %add = fadd half %a, %fneg.b
%fneg = fneg half %add
ret half %fneg
}
-define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_sub_f32_e32 v1, v1, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v1
-; SI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v2
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v1, v2, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v2, v1
-; SI-NSZ-NEXT: v_xor_b32_e32 v1, 0xffff8000, v0
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+define half @v_fneg_add_x_fneg_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_x_fneg_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v0
-; VI-SAFE-NEXT: v_sub_f16_e32 v0, v1, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, v2
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_xor_b32_e32 v2, 0x8000, v0
-; VI-NSZ-NEXT: v_sub_f16_e32 v0, v0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_sub_f16_e32 v1, v1, v0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v1
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
-; GFX11-NSZ-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_store_use_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_x_fneg_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v0, v1, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_x_fneg_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v0, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.b = fneg nsz half %b
+ %add = fadd nsz half %a, %fneg.b
+ %fneg = fneg nsz half %add
+ ret half %fneg
+}
+
+define half @v_fneg_add_fneg_fneg_f16(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_fneg_fneg_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_fneg_fneg_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e64 v0, -v0, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_fneg_fneg_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e64 v0, -v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fneg.b = fneg half %b
+ %add = fadd half %fneg.a, %fneg.b
+ %fneg = fneg half %add
+ ret half %fneg
+}
+
+define half @v_fneg_add_fneg_fneg_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_fneg_fneg_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_fneg_fneg_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_fneg_fneg_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg nsz half %a
+ %fneg.b = fneg nsz half %b
+ %add = fadd nsz half %fneg.a, %fneg.b
+ %fneg = fneg nsz half %add
+ ret half %fneg
+}
+
+define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_sub_f32_e32 v1, v1, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v2, -v1
+; SI-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; SI-NEXT: v_mov_b32_e32 v0, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v0
+; VI-NEXT: v_sub_f16_e32 v0, v1, v0
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: v_mov_b32_e32 v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_store_use_fneg_x_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v1, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%add = fadd half %fneg.a, %b
%fneg = fneg half %add
@@ -481,86 +431,76 @@ define { half, half } @v_fneg_add_store_use_fneg_x_f16(half %a, half %b) #0 {
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_add_store_use_fneg_x_f16_nsz(half %a, half %b) #0 {
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_sub_f32_e32 v1, v2, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v1
+; SI-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; SI-NEXT: v_mov_b32_e32 v0, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v0
+; VI-NEXT: v_sub_f16_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_store_use_fneg_x_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg nsz half %a
+ %add = fadd nsz half %fneg.a, %b
+ %fneg = fneg nsz half %add
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 1
+ ret { half, half } %insert.1
+}
+
define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-SAFE-NEXT: v_sub_f32_e32 v1, v1, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v1
-; SI-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v3
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_multi_use_fneg_x_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v3, -v3
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: v_mul_f32_e32 v1, v3, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v4, -v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v3, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, v4, v2
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_multi_use_fneg_x_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v1, v1, v0
+; VI-NEXT: v_xor_b32_e32 v3, 0x8000, v1
+; VI-NEXT: v_mul_f16_e64 v1, -v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, v3
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_sub_f16_e32 v1, v1, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x8000, v1
-; VI-SAFE-NEXT: v_mul_f16_e64 v1, -v0, v2
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, v3
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e32 v3, v0, v1
-; VI-NSZ-NEXT: v_mul_f16_e64 v1, -v0, v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, v3
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_sub_f16_e32 v1, v1, v0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v3, 0x8000, v1
-; GFX11-SAFE-NEXT: v_mul_f16_e64 v1, -v0, v2
-; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v3
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_sub_f16_e32 v3, v0, v1
-; GFX11-NSZ-NEXT: v_mul_f16_e64 v1, -v0, v2
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v3
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_add_multi_use_fneg_x_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v1, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_xor_b32_e32 v3, 0x8000, v1
+; GFX11-NEXT: v_mul_f16_e64 v1, -v0, v2
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%add = fadd half %fneg.a, %b
%fneg = fneg half %add
@@ -571,6 +511,47 @@ define { half, half } @v_fneg_add_multi_use_fneg_x_f16(half %a, half %b, half %c
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_add_multi_use_fneg_x_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_add_multi_use_fneg_x_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v3, -v3
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_mul_f32_e32 v1, v3, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_add_multi_use_fneg_x_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v3, v0, v1
+; VI-NEXT: v_mul_f16_e64 v1, -v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, v3
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_add_multi_use_fneg_x_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_sub_f16_e32 v3, v0, v1
+; GFX11-NEXT: v_mul_f16_e64 v1, -v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg nsz half %a
+ %add = fadd nsz half %fneg.a, %b
+ %fneg = fneg nsz half %add
+ %use1 = fmul nsz half %fneg.a, %c
+
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1
+ ret { half, half } %insert.1
+}
+
define amdgpu_ps half @fneg_fadd_0_safe_f16(half inreg %tmp2, half inreg %tmp6, <4 x i32> %arg) #0 {
; SI-LABEL: fneg_fadd_0_safe_f16:
; SI: ; %bb.0: ; %.entry
@@ -733,16 +714,6 @@ define half @v_fneg_mul_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e64 v0, v0, -v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %a, %b
%fneg = fneg half %mul
ret half %fneg
@@ -773,20 +744,6 @@ define { half, half } @v_fneg_mul_store_use_mul_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_store_use_mul_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_store_use_mul_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %a, %b
%fneg = fneg half %mul
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
@@ -821,20 +778,6 @@ define { half, half } @v_fneg_mul_multi_use_mul_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_multi_use_mul_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_multi_use_mul_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %a, %b
%fneg = fneg half %mul
%use1 = fmul half %mul, 4.0
@@ -864,16 +807,6 @@ define half @v_fneg_mul_fneg_x_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%mul = fmul half %fneg.a, %b
%fneg = fneg half %mul
@@ -901,16 +834,6 @@ define half @v_fneg_mul_x_fneg_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_x_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_x_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg half %b
%mul = fmul half %a, %fneg.b
%fneg = fneg half %mul
@@ -938,16 +861,6 @@ define half @v_fneg_mul_fneg_fneg_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e64 v0, v0, -v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_fneg_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fneg.b = fneg half %b
%mul = fmul half %fneg.a, %fneg.b
@@ -983,22 +896,6 @@ define { half, half } @v_fneg_mul_store_use_fneg_x_f16(half %a, half %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_store_use_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.h, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_store_use_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%mul = fmul half %fneg.a, %b
%fneg = fneg half %mul
@@ -1037,22 +934,6 @@ define { half, half } @v_fneg_mul_multi_use_fneg_x_f16(half %a, half %b, half %c
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_mul_multi_use_fneg_x_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.h, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_mul_multi_use_fneg_x_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%mul = fmul half %fneg.a, %b
%fneg = fneg half %mul
@@ -1092,22 +973,6 @@ define half @v_fneg_minnum_f16_ieee(half %a, half %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %b)
%fneg = fneg half %min
ret half %fneg
@@ -1134,16 +999,6 @@ define half @v_fneg_minnum_f16_no_ieee(half %a, half %b) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e64 v0, -v0, -v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %b)
%fneg = fneg half %min
ret half %fneg
@@ -1167,16 +1022,6 @@ define half @v_fneg_self_minnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %a)
%min.fneg = fneg half %min
ret half %min.fneg
@@ -1200,16 +1045,6 @@ define half @v_fneg_self_minnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %a)
%min.fneg = fneg half %min
ret half %min.fneg
@@ -1238,20 +1073,6 @@ define half @v_fneg_posk_minnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f16_e32 v0, -4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, -4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 4.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1277,16 +1098,6 @@ define half @v_fneg_posk_minnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e64 v0, -v0, -4.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -4.0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -4.0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 4.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1315,20 +1126,6 @@ define half @v_fneg_negk_minnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f16_e32 v0, 4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, 4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, 4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half -4.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1354,16 +1151,6 @@ define half @v_fneg_negk_minnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e64 v0, -v0, 4.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, 4.0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, 4.0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half -4.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1393,20 +1180,6 @@ define half @v_fneg_0_minnum_f16(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call nnan half @llvm.minnum.f16(half 0.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1435,20 +1208,6 @@ define half @v_fneg_neg0_minnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_max_f16_e32 v0, 0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half -0.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1479,22 +1238,6 @@ define half @v_fneg_inv2pi_minnum_f16(half %a) #0 {
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1525,22 +1268,6 @@ define half @v_fneg_neg_inv2pi_minnum_f16(half %a) #0 {
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1566,16 +1293,6 @@ define half @v_fneg_neg0_minnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e64 v0, -v0, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, 0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, 0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half -0.0, half %a)
%fneg = fneg half %min
ret half %fneg
@@ -1610,22 +1327,6 @@ define half @v_fneg_0_minnum_foldable_use_f16_ieee(half %a, half %b) #0 {
; GFX11-NEXT: v_min_f16_e32 v0, 0, v0
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 0.0, half %a)
%fneg = fneg half %min
%mul = fmul half %fneg, %b
@@ -1661,22 +1362,6 @@ define half @v_fneg_inv2pi_minnum_foldable_use_f16(half %a, half %b) #0 {
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)
%fneg = fneg half %min
%mul = fmul half %fneg, %b
@@ -1710,20 +1395,6 @@ define half @v_fneg_0_minnum_foldable_use_f16_no_ieee(half %a, half %b) #4 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_minnum_foldable_use_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half 0.0, half %a)
%fneg = fneg half %min
%mul = fmul half %fneg, %b
@@ -1761,24 +1432,6 @@ define { half, half } @v_fneg_minnum_multi_use_minnum_f16_ieee(half %a, half %b)
; GFX11-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %b)
%fneg = fneg half %min
%use1 = fmul half %min, 4.0
@@ -1834,22 +1487,6 @@ define <2 x half> @v_fneg_minnum_multi_use_minnum_f16_no_ieee(half %a, half %b)
; GFX11-NEXT: v_mul_f16_e32 v1, 4.0, v0
; GFX11-NEXT: v_pack_b32_f16 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.h, 4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, -v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_minnum_multi_use_minnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.h, 4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, -v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%min = call half @llvm.minnum.f16(half %a, half %b)
%fneg = fneg half %min
%use1 = fmul half %min, 4.0
@@ -1888,22 +1525,6 @@ define half @v_fneg_maxnum_f16_ieee(half %a, half %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %b)
%fneg = fneg half %max
ret half %fneg
@@ -1930,16 +1551,6 @@ define half @v_fneg_maxnum_f16_no_ieee(half %a, half %b) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f16_e64 v0, -v0, -v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %b)
%fneg = fneg half %max
ret half %fneg
@@ -1963,16 +1574,6 @@ define half @v_fneg_self_maxnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %a)
%max.fneg = fneg half %max
ret half %max.fneg
@@ -1996,16 +1597,6 @@ define half @v_fneg_self_maxnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_self_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_self_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %a)
%max.fneg = fneg half %max
ret half %max.fneg
@@ -2034,20 +1625,6 @@ define half @v_fneg_posk_maxnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f16_e32 v0, -4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, -4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half 4.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2073,16 +1650,6 @@ define half @v_fneg_posk_maxnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f16_e64 v0, -v0, -4.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_posk_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, -4.0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_posk_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, -4.0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half 4.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2111,20 +1678,6 @@ define half @v_fneg_negk_maxnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half -4.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2150,16 +1703,6 @@ define half @v_fneg_negk_maxnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f16_e64 v0, -v0, 4.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_negk_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, 4.0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_negk_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, 4.0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half -4.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2189,20 +1732,6 @@ define half @v_fneg_0_maxnum_f16(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call nnan half @llvm.maxnum.f16(half 0.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2231,20 +1760,6 @@ define half @v_fneg_neg0_maxnum_f16_ieee(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_min_f16_e32 v0, 0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half -0.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2270,16 +1785,6 @@ define half @v_fneg_neg0_maxnum_f16_no_ieee(half %a) #4 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_min_f16_e64 v0, -v0, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, 0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg0_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e64 v0.l, -v0.l, 0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half -0.0, half %a)
%fneg = fneg half %max
ret half %fneg
@@ -2314,22 +1819,6 @@ define half @v_fneg_0_maxnum_foldable_use_f16_ieee(half %a, half %b) #0 {
; GFX11-NEXT: v_max_f16_e32 v0, 0, v0
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half 0.0, half %a)
%fneg = fneg half %max
%mul = fmul half %fneg, %b
@@ -2363,20 +1852,6 @@ define half @v_fneg_0_maxnum_foldable_use_f16_no_ieee(half %a, half %b) #4 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_0_maxnum_foldable_use_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, 0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half 0.0, half %a)
%fneg = fneg half %max
%mul = fmul half %fneg, %b
@@ -2414,24 +1889,6 @@ define { half, half } @v_fneg_maxnum_multi_use_maxnum_f16_ieee(half %a, half %b)
; GFX11-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %b)
%fneg = fneg half %max
%use1 = fmul half %max, 4.0
@@ -2487,22 +1944,6 @@ define <2 x half> @v_fneg_maxnum_multi_use_maxnum_f16_no_ieee(half %a, half %b)
; GFX11-NEXT: v_mul_f16_e32 v1, 4.0, v0
; GFX11-NEXT: v_pack_b32_f16 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.h, 4.0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_pack_b32_f16 v0, -v0.l, v0.h
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_maxnum_multi_use_maxnum_f16_no_ieee:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.h, 4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_pack_b32_f16 v0, -v0.l, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call half @llvm.maxnum.f16(half %a, half %b)
%fneg = fneg half %max
%use1 = fmul half %max, 4.0
@@ -2516,155 +1957,30 @@ define <2 x half> @v_fneg_maxnum_multi_use_maxnum_f16_no_ieee(half %a, half %b)
; --------------------------------------------------------------------------------
define half @v_fneg_fma_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v3, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fmac_f16_e32 v2, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %a, half %b, half %c)
%fneg = fneg half %fma
ret half %fneg
@@ -2741,20 +2057,6 @@ define { half, half } @v_fneg_fma_store_use_fma_f16(half %a, half %b, half %c) #
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_store_use_fma_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v1.l, v0.l, v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_store_use_fma_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v1.l, v0.l, v1.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %a, half %b, half %c)
%fneg = fneg half %fma
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
@@ -2763,169 +2065,34 @@ define { half, half } @v_fneg_fma_store_use_fma_f16(half %a, half %b, half %c) #
}
define { half, half } @v_fneg_fma_multi_use_fma_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_multi_use_fma_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, v2
+; SI-NEXT: v_mul_f32_e32 v1, 4.0, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v3, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v1, -v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_multi_use_fma_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; VI-NEXT: v_mul_f16_e32 v1, 4.0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; VI-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v1
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; VI-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_multi_use_fma_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v2
-; GFX11-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_multi_use_fma_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_multi_use_fma_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, 4.0, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_multi_use_fma_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_multi_use_fma_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fmac_f16_e32 v2, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v2
+; GFX11-NEXT: v_mul_f16_e32 v1, 4.0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %a, half %b, half %c)
%fneg = fneg half %fma
%use1 = fmul half %fma, 4.0
@@ -2934,468 +2101,184 @@ define { half, half } @v_fneg_fma_multi_use_fma_f16(half %a, half %b, half %c) #
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_fma_multi_use_fma_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fma_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, -v1, -v2
+; SI-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_multi_use_fma_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; VI-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_multi_use_fma_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
+ %fneg = fneg half %fma
+ %use1 = fmul half %fma, 4.0
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1
+ ret { half, half } %insert.1
+}
+
define half @v_fneg_fma_fneg_x_y_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v4, -v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_fneg_x_y_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, -v0, v1, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_fneg_x_y_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, -v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, -v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, v1, -v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_fneg_x_y_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v0, -v0, v1, v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_fneg_x_y_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, v1, -v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_x_y_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_x_y_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_fneg_x_y_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, -v0, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)
%fneg = fneg half %fma
ret half %fneg
}
+define half @v_fneg_fma_fneg_x_y_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_y_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_fneg_x_y_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, -v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_fneg_x_y_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, v1, -v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fma = call nsz half @llvm.fma.f16(half %fneg.a, half %b, half %c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define half @v_fneg_fma_x_fneg_y_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v3, -v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_x_fneg_y_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, -v1, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_x_fneg_y_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, -v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, v1, -v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_x_fneg_y_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v0, v0, -v1, v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_x_fneg_y_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, v1, -v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_x_fneg_y_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_x_fneg_y_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_x_fneg_y_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg half %b
%fma = call half @llvm.fma.f16(half %a, half %fneg.b, half %c)
%fneg = fneg half %fma
ret half %fneg
}
+define half @v_fneg_fma_x_fneg_y_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_x_fneg_y_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_x_fneg_y_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, -v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_x_fneg_y_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, v1, -v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.b = fneg half %b
+ %fma = call nsz half @llvm.fma.f16(half %a, half %fneg.b, half %c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define half @v_fneg_fma_fneg_fneg_y_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_fneg_fneg_y_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v3, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_fneg_fneg_y_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_fneg_y_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_fneg_fneg_y_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fmac_f16_e32 v2, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fneg.b = fneg half %b
%fma = call half @llvm.fma.f16(half %fneg.a, half %fneg.b, half %c)
@@ -3403,156 +2286,60 @@ define half @v_fneg_fma_fneg_fneg_y_f16(half %a, half %b, half %c) #0 {
ret half %fneg
}
+define half @v_fneg_fma_fneg_fneg_y_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_fneg_fneg_y_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, -v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_fneg_fneg_y_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_fneg_fneg_y_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fneg.b = fneg half %b
+ %fma = call nsz half @llvm.fma.f16(half %fneg.a, half %fneg.b, half %c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define half @v_fneg_fma_fneg_x_fneg_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v4, -v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_fneg_x_fneg_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, -v0, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_fneg_x_fneg_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, -v0, v1, -v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, -v0, v1, -v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, v1, v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v0, -v0, v1, -v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v1.l, -v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_fneg_x_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_fneg_x_fneg_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, -v0, v1, -v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fneg.c = fneg half %c
%fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %fneg.c)
@@ -3560,510 +2347,247 @@ define half @v_fneg_fma_fneg_x_fneg_f16(half %a, half %b, half %c) #0 {
ret half %fneg
}
+define half @v_fneg_fma_fneg_x_fneg_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_fneg_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_fneg_x_fneg_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_fneg_x_fneg_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fneg.c = fneg half %c
+ %fma = call nsz half @llvm.fma.f16(half %fneg.a, half %b, half %fneg.c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define half @v_fneg_fma_x_y_fneg_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_x_y_fneg_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v3, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v4, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v4, v4, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v5, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v0, v4
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_x_y_fneg_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, -v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, v1, -v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_x_y_fneg_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v0, v0, v1, -v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_x_y_fneg_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_x_y_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_x_y_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_x_y_fneg_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, v1, -v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.c = fneg half %c
%fma = call half @llvm.fma.f16(half %a, half %b, half %fneg.c)
%fneg = fneg half %fma
ret half %fneg
}
+define half @v_fneg_fma_x_y_fneg_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_x_y_fneg_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_fma_f32 v0, v0, -v1, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_x_y_fneg_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_x_y_fneg_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.c = fneg half %c
+ %fma = call nsz half @llvm.fma.f16(half %a, half %b, half %fneg.c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define { half, half } @v_fneg_fma_store_use_fneg_x_y_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0xffff8000, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v3
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v4, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v5, v5, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v6, v5, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v5, v5, v6
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v5, 12, v4
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v6, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v5, v0, v5
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v5, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v6, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, v3
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v1
+; SI-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v1
+; SI-NEXT: v_fma_f32 v0, v0, v3, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v5, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[5:6], v5
-; SI-NSZ-NEXT: v_fma_f64 v[2:3], v[5:6], v[3:4], v[1:2]
-; SI-NSZ-NEXT: v_xor_b32_e32 v1, 0xffff8000, v0
-; SI-NSZ-NEXT: v_and_b32_e32 v0, 0x1ff, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 8, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NSZ-NEXT: v_bfe_u32 v4, v3, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v5, v5, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v6, v5, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v5, v5, v6
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v5, 12, v4
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v6, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v5, v0, v5
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v5, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v6, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_xor_b32_e32 v3, 0x8000, v0
+; VI-NEXT: v_fma_f16 v0, -v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x8000, v0
-; VI-SAFE-NEXT: v_fma_f16 v0, -v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, v3
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_xor_b32_e32 v3, 0x8000, v0
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, v1, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, v3
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v1, -v0, v1, v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v1
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v2, v0, v1, -v2
-; GFX11-NSZ-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.h, v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_store_use_fneg_x_y_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v1, -v0, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)
+ %fneg = fneg half %fma
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 1
+ ret { half, half } %insert.1
+}
+
+define { half, half } @v_fneg_fma_store_use_fneg_x_y_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fma_store_use_fneg_x_y_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_fma_f32 v1, v3, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v1
+; SI-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; SI-NEXT: v_mov_b32_e32 v0, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_store_use_fneg_x_y_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_xor_b32_e32 v3, 0x8000, v0
+; VI-NEXT: v_fma_f16 v0, v0, v1, -v2
+; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_store_use_fneg_x_y_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v2, v0, v1, -v2
+; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg half %a
+ %fma = call nsz half @llvm.fma.f16(half %fneg.a, half %b, half %c)
+ %fneg = fneg half %fma
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 1
+ ret { half, half } %insert.1
+}
+
+define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16(half %a, half %b, half %c, half %d) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_fma_f32 v1, v0, v1, v2
+; SI-NEXT: v_mul_f32_e32 v2, v0, v3
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, -v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; VI-NEXT: v_mul_f16_e64 v1, -v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v1, -v0, v1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; GFX11-NEXT: v_mul_f16_e64 v1, -v0, v3
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)
%fneg = fneg half %fma
+ %use1 = fmul half %fneg.a, %d
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
- %insert.1 = insertvalue { half, half } %insert.0, half %fneg.a, 1
+ %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1
ret { half, half } %insert.1
}
-define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16(half %a, half %b, half %c, half %d) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v8, -v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[6:7], v[4:5], v[0:1]
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-SAFE-NEXT: v_bfe_u32 v4, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v5, v5, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v6, v5, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v5, v5, v6
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v5, 12, v4
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v6, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v5, v0, v5
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v5, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v6, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x8000, v1
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, v8, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16_nsz(half %a, half %b, half %c, half %d) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v4, -v4
+; SI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; SI-NEXT: v_mul_f32_e32 v1, v4, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v6, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NSZ-NEXT: v_fma_f64 v[1:2], v[6:7], v[4:5], v[1:2]
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 0x1ff, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v1, v4, v1
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v4, 0xffe, v4
-; SI-NSZ-NEXT: v_bfe_u32 v5, v2, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v1, v4, v1
-; SI-NSZ-NEXT: v_sub_i32_e32 v6, vcc, s4, v5
-; SI-NSZ-NEXT: v_or_b32_e32 v4, 0x1000, v1
-; SI-NSZ-NEXT: v_med3_i32 v6, v6, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v7, v6, v4
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, v6, v7
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v5, vcc, s4, v5
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 12, v5
-; SI-NSZ-NEXT: v_or_b32_e32 v4, v7, v4
-; SI-NSZ-NEXT: v_or_b32_e32 v6, v1, v6
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v6, 7, v4
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 2, v4
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; SI-NSZ-NEXT: v_mov_b32_e32 v6, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v7, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v5
-; SI-NSZ-NEXT: v_mul_f32_e32 v0, v0, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NSZ-NEXT: v_and_b32_e32 v0, 0x8000, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v2, v0, v1, -v2
+; VI-NEXT: v_mul_f16_e64 v1, -v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, -v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v1
-; VI-SAFE-NEXT: v_mul_f16_e64 v1, -v0, v3
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, v2
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v2, v0, v1, -v2
-; VI-NSZ-NEXT: v_mul_f16_e64 v1, -v0, v3
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v1, -v0, v1, v2
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v2, 0x8000, v1
-; GFX11-SAFE-NEXT: v_mul_f16_e64 v1, -v0, v3
-; GFX11-SAFE-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v2, v0, v1, -v2
-; GFX11-NSZ-NEXT: v_mul_f16_e64 v1, -v0, v3
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v3.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.h, v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fma_multi_use_fneg_x_y_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v2, v0, v1, -v2
+; GFX11-NEXT: v_mul_f16_e64 v1, -v0, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
- %fma = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)
+ %fma = call nsz half @llvm.fma.f16(half %fneg.a, half %b, half %c)
%fneg = fneg half %fma
%use1 = fmul half %fneg.a, %d
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
@@ -4076,316 +2600,233 @@ define { half, half } @v_fneg_fma_multi_use_fneg_x_y_f16(half %a, half %b, half
; --------------------------------------------------------------------------------
define half @v_fneg_fmad_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fmad_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_mac_f32_e32 v2, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v2
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fmad_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fmad_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fmad_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fmad_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fmad_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fmad_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fmad_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fmad_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fmad_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fmac_f16_e32 v2, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
%fneg = fneg half %fma
ret half %fneg
}
+define half @v_fneg_fmad_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fmad_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v1, -v1
+; SI-NEXT: v_mad_f32 v0, v0, v1, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fmad_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fmad_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz half @llvm.fmuladd.f16(half %a, half %b, half %c)
+ %fneg = fneg half %fma
+ ret half %fneg
+}
+
define <4 x half> @v_fneg_fmad_v4f32(<4 x half> %a, <4 x half> %b, <4 x half> %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_v4f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v6, v6, v7
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: v_add_f32_e32 v6, v6, v7
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v9
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; SI-SAFE-NEXT: v_mul_f32_e32 v3, v7, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v8
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-SAFE-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-SAFE-NEXT: v_add_f32_e32 v1, v1, v5
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT: v_add_f32_e32 v0, v0, v4
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fmad_v4f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_mac_f32_e32 v9, v11, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_mac_f32_e32 v5, v1, v3
+; SI-NEXT: v_mac_f32_e32 v6, v8, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v6
+; SI-NEXT: v_mac_f32_e32 v4, v0, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v4
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; SI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fmad_v4f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NSZ-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-NSZ-NEXT: v_mul_f32_e32 v6, v6, v7
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v7, v7, v9
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, v1, v3
-; SI-NSZ-NEXT: v_mul_f32_e32 v0, v0, v2
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v10, 16, v4
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v6, v6
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v7, v7
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v10
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v5
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NSZ-NEXT: v_sub_f32_e32 v6, v6, v8
-; SI-NSZ-NEXT: v_sub_f32_e32 v2, v7, v2
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NSZ-NEXT: v_sub_f32_e32 v1, v1, v3
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v4
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v3, 16, v6
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fmad_v4f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; VI-NEXT: v_fma_f16 v6, v8, v7, v6
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; VI-NEXT: v_fma_f16 v7, v9, v8, v7
+; VI-NEXT: v_fma_f16 v0, v0, v2, v4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_fma_f16 v1, v1, v3, v5
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fmad_v4f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; VI-SAFE-NEXT: v_fma_f16 v6, v8, v7, v6
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; VI-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; VI-SAFE-NEXT: v_fma_f16 v7, v9, v8, v7
-; VI-SAFE-NEXT: v_fma_f16 v0, v0, v2, v4
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v7
-; VI-SAFE-NEXT: v_fma_f16 v1, v1, v3, v5
-; VI-SAFE-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-SAFE-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fmad_v4f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; VI-NSZ-NEXT: v_fma_f16 v6, v8, -v7, -v6
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; VI-NSZ-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; VI-NSZ-NEXT: v_fma_f16 v7, v9, -v8, -v7
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v2, -v4
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 16, v7
-; VI-NSZ-NEXT: v_fma_f16 v1, v1, -v3, -v5
-; VI-NSZ-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-NSZ-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fmad_v4f32:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_pk_fma_f16 v0, v0, v2, v4
-; GFX11-SAFE-NEXT: v_pk_fma_f16 v1, v1, v3, v5
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fmad_v4f32:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_pk_fma_f16 v0, v0, v2, v4 neg_lo:[0,1,1] neg_hi:[0,1,1]
-; GFX11-NSZ-NEXT: v_pk_fma_f16 v1, v1, v3, v5 neg_lo:[0,1,1] neg_hi:[0,1,1]
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fmad_v4f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_fma_f16 v0, v0, v2, v4
+; GFX11-NEXT: v_pk_fma_f16 v1, v1, v3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
%fneg = fneg <4 x half> %fma
ret <4 x half> %fneg
}
+define <4 x half> @v_fneg_fmad_v4f32_nsz(<4 x half> %a, <4 x half> %b, <4 x half> %c) #0 {
+; SI-LABEL: v_fneg_fmad_v4f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; SI-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_mad_f32 v6, v7, v11, -v6
+; SI-NEXT: v_mad_f32 v8, v9, v10, -v8
+; SI-NEXT: v_mad_f32 v0, v0, v2, -v4
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v6
+; SI-NEXT: v_mad_f32 v1, v1, v3, -v5
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fmad_v4f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; VI-NEXT: v_fma_f16 v6, v8, -v7, -v6
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; VI-NEXT: v_fma_f16 v7, v9, -v8, -v7
+; VI-NEXT: v_fma_f16 v0, v0, -v2, -v4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_fma_f16 v1, v1, -v3, -v5
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fmad_v4f32_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_pk_fma_f16 v0, v0, v2, v4 neg_lo:[0,1,1] neg_hi:[0,1,1]
+; GFX11-NEXT: v_pk_fma_f16 v1, v1, v3, v5 neg_lo:[0,1,1] neg_hi:[0,1,1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz <4 x half> @llvm.fmuladd.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
+ %fneg = fneg <4 x half> %fma
+ ret <4 x half> %fneg
+}
+
define { half, half } @v_fneg_fmad_multi_use_fmad_f16(half %a, half %b, half %c) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v2
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_fmad_multi_use_fmad_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_mac_f32_e32 v2, v0, v1
+; SI-NEXT: v_mul_f32_e32 v1, 4.0, v2
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v2
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v2
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v1, -v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_fmad_multi_use_fmad_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v1
+; VI-NEXT: v_mul_f16_e32 v1, 4.0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v1
-; VI-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v1
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; VI-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fmac_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v2
-; GFX11-SAFE-NEXT: v_mul_f16_e32 v1, 4.0, v2
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v0, v0, -v1, -v2
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_mul_f16_e32 v1, -4.0, v0
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, 4.0, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fmad_multi_use_fmad_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, -4.0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fneg_fmad_multi_use_fmad_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fmac_f16_e32 v2, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v2
+; GFX11-NEXT: v_mul_f16_e32 v1, 4.0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
%fneg = fneg half %fma
%use1 = fmul half %fma, 4.0
@@ -4394,6 +2835,42 @@ define { half, half } @v_fneg_fmad_multi_use_fmad_f16(half %a, half %b, half %c)
ret { half, half } %insert.1
}
+define { half, half } @v_fneg_fmad_multi_use_fmad_f16_nsz(half %a, half %b, half %c) #0 {
+; SI-LABEL: v_fneg_fmad_multi_use_fmad_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v1, -v1
+; SI-NEXT: v_mad_f32 v0, v0, v1, -v2
+; SI-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_fmad_multi_use_fmad_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; VI-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fmad_multi_use_fmad_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v0, v0, -v1, -v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f16_e32 v1, -4.0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz half @llvm.fmuladd.f16(half %a, half %b, half %c)
+ %fneg = fneg half %fma
+ %use1 = fmul half %fma, 4.0
+ %insert.0 = insertvalue { half, half } poison, half %fneg, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %use1, 1
+ ret { half, half } %insert.1
+}
+
; --------------------------------------------------------------------------------
; fp_extend tests
; --------------------------------------------------------------------------------
@@ -4422,22 +2899,6 @@ define double @v_fneg_fp_extend_f16_to_f64(half %a) #0 {
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_f16_to_f64:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_f16_to_f64:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %a to double
%fneg = fneg double %fpext
ret double %fneg
@@ -4465,20 +2926,6 @@ define double @v_fneg_fp_extend_fneg_f16_to_f64(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_fneg_f16_to_f64:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fpext = fpext half %fneg.a to double
%fneg = fneg double %fpext
@@ -4513,24 +2960,6 @@ define { double, half } @v_fneg_fp_extend_store_use_fneg_f16_to_f64(half %a) #0
; GFX11-NEXT: v_xor_b32_e32 v2, 0x8000, v2
; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v2.l, 0x8000, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_extend_store_use_fneg_f16_to_f64:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v2.l, 0x8000, v2.l
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fpext = fpext half %fneg.a to double
%fneg = fneg double %fpext
@@ -4568,26 +2997,6 @@ define { double, double } @v_fneg_multi_use_fp_extend_fneg_f16_to_f64(half %a) #
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v3
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f64:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v3
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %a to double
%fneg = fneg double %fpext
%insert.0 = insertvalue { double, double } poison, double %fneg, 0
@@ -4623,25 +3032,7 @@ define { double, double } @v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64(h
; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX11-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_foldable_use_fp_extend_fneg_f16_to_f64:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %a to double
%fneg = fneg double %fpext
%mul = fmul double %fpext, 4.0
@@ -4673,20 +3064,6 @@ define { float, float } @v_fneg_multi_use_fp_extend_fneg_f16_to_f32(half %a) #0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_extend_fneg_f16_to_f32:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fpext = fpext half %a to float
%fneg = fneg float %fpext
%insert.0 = insertvalue { float, float } poison, float %fneg, 0
@@ -5153,108 +3530,6 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v1, v0
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-SAFE-TRUE16-NEXT: v_bfe_u32 v4, v1, 20, 11
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-SAFE-TRUE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v3, v2
-; GFX11-SAFE-TRUE16-NEXT: v_med3_i32 v3, v5, 0, 13
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v5, 0x1000, v2
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v3, v5
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v3, v6
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-SAFE-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0xfffffc10, v4
-; GFX11-SAFE-TRUE16-NEXT: v_lshl_or_b32 v5, v4, 12, v2
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v5, 7, v3
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_dual_mov_b32 v6, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v6, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v4
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v3, 0x8000, v5, v2
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b32_e32 v1, v0
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_fp_round_store_use_fneg_f64_to_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v1, v0
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-NSZ-TRUE16-NEXT: v_bfe_u32 v4, v1, 20, 11
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NSZ-TRUE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v3, v2
-; GFX11-NSZ-TRUE16-NEXT: v_med3_i32 v3, v5, 0, 13
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v5, 0x1000, v2
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v6, v3, v5
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v3, v6
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v5
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-NSZ-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0xfffffc10, v4
-; GFX11-NSZ-TRUE16-NEXT: v_lshl_or_b32 v5, v4, 12, v2
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v5, 7, v3
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v5
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v5
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_dual_mov_b32 v6, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v5
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v6, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v4
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v3, 0x8000, v5, v2
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b32_e32 v1, v0
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg double %a
%fpround = fptrunc double %fneg.a to half
%fneg = fneg half %fpround
@@ -5569,104 +3844,6 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; GFX11-NEXT: v_and_or_b32 v1, 0x8000, v1, v0
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-SAFE-TRUE16-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-SAFE-TRUE16-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-SAFE-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-SAFE-TRUE16-NEXT: v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v4, 7, v2
-; GFX11-SAFE-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_and_or_b32 v1, 0x8000, v1, v0
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_multi_use_fp_round_fneg_f64_to_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-NSZ-TRUE16-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-NSZ-TRUE16-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-NSZ-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-NSZ-TRUE16-NEXT: v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v4, 7, v2
-; GFX11-NSZ-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_and_or_b32 v1, 0x8000, v1, v0
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fpround = fptrunc double %a to half
%fneg = fneg half %fpround
%insert.0 = insertvalue { half, half } poison, half %fneg, 0
@@ -5698,16 +3875,6 @@ define half @v_fneg_trunc_f16(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_trunc_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_trunc_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_trunc_f16_e64 v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_trunc_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_trunc_f16_e64 v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%trunc = call half @llvm.trunc.f16(half %a)
%fneg = fneg half %trunc
ret half %fneg
@@ -5729,103 +3896,88 @@ define half @v_fneg_round_f16(half %a) #0 {
; SI-NEXT: s_brev_b32 s4, -2
; SI-NEXT: v_bfi_b32 v0, s4, v2, v0
; SI-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_round_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_trunc_f16_e32 v1, v0
-; VI-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, 0x3c00
-; VI-SAFE-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; VI-SAFE-NEXT: s_movk_i32 s4, 0x7fff
-; VI-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
-; VI-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: v_fneg_round_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_trunc_f16_e32 v1, v0
-; VI-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x3c00
-; VI-NSZ-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; VI-NSZ-NEXT: s_movk_i32 s4, 0x7fff
-; VI-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
-; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: v_fneg_round_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_trunc_f16_e32 v1, v0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
-; GFX11-SAFE-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-SAFE-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
-; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: v_fneg_round_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_trunc_f16_e32 v1, v0
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
-; GFX11-NSZ-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-NSZ-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_round_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_trunc_f16_e32 v1.h, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v1.h
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s0
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_add_f16_e32 v0.l, v1.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_round_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_trunc_f16_e32 v1.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v1.h
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e64 v0.l, -v1.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_round_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_trunc_f16_e32 v1, v0
+; VI-NEXT: v_sub_f16_e32 v2, v0, v1
+; VI-NEXT: v_mov_b32_e32 v3, 0x3c00
+; VI-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; VI-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; VI-NEXT: s_movk_i32 s4, 0x7fff
+; VI-NEXT: v_bfi_b32 v0, s4, v2, v0
+; VI-NEXT: v_add_f16_e32 v0, v1, v0
+; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_round_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%round = call half @llvm.round.f16(half %a)
%fneg = fneg half %round
ret half %fneg
}
+define half @v_fneg_round_f16_nsz(half %a) #0 {
+; SI-LABEL: v_fneg_round_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_trunc_f32_e32 v1, v0
+; SI-NEXT: v_sub_f32_e32 v2, v0, v1
+; SI-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; SI-NEXT: s_brev_b32 s4, -2
+; SI-NEXT: v_bfi_b32 v0, s4, v2, v0
+; SI-NEXT: v_sub_f32_e64 v0, -v1, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_round_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_trunc_f16_e32 v1, v0
+; VI-NEXT: v_sub_f16_e32 v2, v0, v1
+; VI-NEXT: v_mov_b32_e32 v3, 0x3c00
+; VI-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; VI-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; VI-NEXT: s_movk_i32 s4, 0x7fff
+; VI-NEXT: v_bfi_b32 v0, s4, v2, v0
+; VI-NEXT: v_sub_f16_e64 v0, -v1, v0
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_round_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f16_e64 v0, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %round = call nsz half @llvm.round.f16(half %a)
+ %fneg = fneg nsz half %round
+ ret half %fneg
+}
+
; --------------------------------------------------------------------------------
; rint tests
; --------------------------------------------------------------------------------
@@ -5850,16 +4002,6 @@ define half @v_fneg_rint_f16(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rndne_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_rint_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_rndne_f16_e64 v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_rint_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_rndne_f16_e64 v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%rint = call half @llvm.rint.f16(half %a)
%fneg = fneg half %rint
ret half %fneg
@@ -5889,16 +4031,6 @@ define half @v_fneg_nearbyint_f16(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rndne_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_nearbyint_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_rndne_f16_e64 v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_nearbyint_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_rndne_f16_e64 v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%nearbyint = call half @llvm.nearbyint.f16(half %a)
%fneg = fneg half %nearbyint
ret half %fneg
@@ -5934,20 +4066,6 @@ define half @v_fneg_sin_f16(half %a) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_sin_f16_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_sin_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xb118, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_sin_f16_e32 v0.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_sin_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xb118, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sin_f16_e32 v0.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%sin = call half @llvm.sin.f16(half %a)
%fneg = fneg half %sin
ret half %fneg
@@ -5976,16 +4094,6 @@ define half @v_fneg_canonicalize_f16(half %a) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e64 v0, -v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_canonicalize_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_canonicalize_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%trunc = call half @llvm.canonicalize.f16(half %a)
%fneg = fneg half %trunc
ret half %fneg
@@ -6009,7 +4117,7 @@ define void @v_fneg_copytoreg_f16(ptr addrspace(1) %out, half %a, half %b, half
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; SI-NEXT: s_cbranch_execz .LBB81_2
+; SI-NEXT: s_cbranch_execz .LBB101_2
; SI-NEXT: ; %bb.1: ; %if
; SI-NEXT: v_cvt_f32_f16_e32 v3, v4
; SI-NEXT: v_cvt_f32_f16_e64 v4, -v2
@@ -6017,7 +4125,7 @@ define void @v_fneg_copytoreg_f16(ptr addrspace(1) %out, half %a, half %b, half
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: flat_store_short v[0:1], v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: .LBB81_2: ; %endif
+; SI-NEXT: .LBB101_2: ; %endif
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: flat_store_short v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6033,12 +4141,12 @@ define void @v_fneg_copytoreg_f16(ptr addrspace(1) %out, half %a, half %b, half
; VI-NEXT: v_mul_f16_e32 v2, v2, v3
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT: s_cbranch_execz .LBB81_2
+; VI-NEXT: s_cbranch_execz .LBB101_2
; VI-NEXT: ; %bb.1: ; %if
; VI-NEXT: v_mul_f16_e64 v3, -v2, v4
; VI-NEXT: flat_store_short v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: .LBB81_2: ; %endif
+; VI-NEXT: .LBB101_2: ; %endif
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6056,58 +4164,16 @@ define void @v_fneg_copytoreg_f16(ptr addrspace(1) %out, half %a, half %b, half
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v5
-; GFX11-NEXT: s_cbranch_execz .LBB81_2
+; GFX11-NEXT: s_cbranch_execz .LBB101_2
; GFX11-NEXT: ; %bb.1: ; %if
; GFX11-NEXT: v_mul_f16_e64 v3, -v2, v4
; GFX11-NEXT: global_store_b16 v[0:1], v3, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: .LBB81_2: ; %endif
+; GFX11-NEXT: .LBB101_2: ; %endif
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_copytoreg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 1, v6
-; GFX11-SAFE-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v6
-; GFX11-SAFE-TRUE16-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v5
-; GFX11-SAFE-TRUE16-NEXT: s_cbranch_execz .LBB81_2
-; GFX11-SAFE-TRUE16-NEXT: ; %bb.1: ; %if
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v2.h, -v2.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: global_store_d16_hi_b16 v[0:1], v2, off dlc
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SAFE-TRUE16-NEXT: .LBB81_2: ; %endif
-; GFX11-SAFE-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-SAFE-TRUE16-NEXT: global_store_b16 v[0:1], v2, off dlc
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_copytoreg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 1, v6
-; GFX11-NSZ-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v6
-; GFX11-NSZ-TRUE16-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v5
-; GFX11-NSZ-TRUE16-NEXT: s_cbranch_execz .LBB81_2
-; GFX11-NSZ-TRUE16-NEXT: ; %bb.1: ; %if
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v2.h, -v2.l, v4.l
-; GFX11-NSZ-TRUE16-NEXT: global_store_d16_hi_b16 v[0:1], v2, off dlc
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NSZ-TRUE16-NEXT: .LBB81_2: ; %endif
-; GFX11-NSZ-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NSZ-TRUE16-NEXT: global_store_b16 v[0:1], v2, off dlc
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -6161,22 +4227,6 @@ define half @v_fneg_inlineasm_f16(half %a, half %b, half %c, i32 %d) #0 {
; GFX11-NEXT: ; use v0
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_inlineasm_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-SAFE-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-SAFE-TRUE16-NEXT: ; use v0
-; GFX11-SAFE-TRUE16-NEXT: ;;#ASMEND
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_inlineasm_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
-; GFX11-NSZ-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-NSZ-TRUE16-NEXT: ; use v0
-; GFX11-NSZ-TRUE16-NEXT: ;;#ASMEND
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %a, %b
%fneg = fneg half %mul
call void asm sideeffect "; use $0", "v"(half %fneg)
@@ -6222,26 +4272,6 @@ define half @v_fneg_inlineasm_multi_use_src_f16(ptr addrspace(1) %out, half %a,
; GFX11-NEXT: ; use v1
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: v_fneg_inlineasm_multi_use_src_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v2.l, v3.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.l
-; GFX11-SAFE-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-SAFE-TRUE16-NEXT: ; use v1
-; GFX11-SAFE-TRUE16-NEXT: ;;#ASMEND
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: v_fneg_inlineasm_multi_use_src_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v2.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.l
-; GFX11-NSZ-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-NSZ-TRUE16-NEXT: ; use v1
-; GFX11-NSZ-TRUE16-NEXT: ;;#ASMEND
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -6368,22 +4398,6 @@ define { half, half } @multiuse_fneg_2_vop3_users_f16(half %a, half %b, half %c)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_2_vop3_users_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v1.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v1.l, -v0.h, v2.l, 2.0
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_2_vop3_users_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v1.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v1.l, -v0.h, v2.l, 2.0
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%fma0 = call half @llvm.fma.f16(half %fneg.a, half %b, half %c)
%fma1 = call half @llvm.fma.f16(half %fneg.a, half %c, half 2.0)
@@ -6423,22 +4437,6 @@ define { half, half } @multiuse_fneg_2_vop2_users_f16(half %a, half %b, half %c)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_2_vop2_users_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.h, v1.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_2_vop2_users_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.h, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg half %a
%mul0 = fmul half %fneg.a, %b
%mul1 = fmul half %fneg.a, %c
@@ -6518,18 +4516,6 @@ define { half, half } @multiuse_fneg_vop2_vop3_users_f16(ptr addrspace(1) %out,
; GFX11-NEXT: v_fma_f16 v0, -v2, v3, 2.0
; GFX11-NEXT: v_mul_f16_e64 v1, -v2, v4
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: multiuse_fneg_vop2_vop3_users_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v2.l, v3.l, 2.0
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v2.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: multiuse_fneg_vop2_vop3_users_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, -v2.l, v3.l, 2.0
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v2.l, v4.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -6546,175 +4532,36 @@ define { half, half } @multiuse_fneg_vop2_vop3_users_f16(ptr addrspace(1) %out,
; The use of the fneg requires a code size increase, but folding into
; the source does not
define { half, half } @free_fold_src_code_size_cost_use_f16(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {
-; SI-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v3
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-SAFE-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], 2.0
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v2, 0xffe, v3
-; SI-SAFE-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-SAFE-NEXT: v_sub_i32_e32 v6, vcc, s4, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-SAFE-NEXT: v_med3_i32 v6, v6, 0, 13
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v7, v6, v2
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, v6, v7
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v6, v2
-; SI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-SAFE-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 12, v3
-; SI-SAFE-NEXT: v_or_b32_e32 v2, v7, v2
-; SI-SAFE-NEXT: v_or_b32_e32 v6, v0, v6
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v6, 7, v2
-; SI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-SAFE-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; SI-SAFE-NEXT: v_mov_b32_e32 v6, 0x7c00
-; SI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v7, 0x7e00
-; SI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
-; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SAFE-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-SAFE-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e64 v1, -v0
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v4
-; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v5
-; SI-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_mul_f32_e32 v1, v1, v2
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: free_fold_src_code_size_cost_use_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v5
+; SI-NEXT: v_fma_f32 v0, v1, v0, 2.0
+; SI-NEXT: v_mul_f32_e64 v1, -v0, v2
+; SI-NEXT: v_mul_f32_e64 v2, -v0, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_cvt_f32_f16_e64 v0, -v3
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-NSZ-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], -2.0
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0x1ff, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v2, 0xffe, v3
-; SI-NSZ-NEXT: v_bfe_u32 v3, v1, 20, 11
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NSZ-NEXT: v_sub_i32_e32 v6, vcc, s4, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; SI-NSZ-NEXT: v_med3_i32 v6, v6, 0, 13
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v7, v6, v2
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, v6, v7
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v6, v2
-; SI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NSZ-NEXT: v_add_i32_e32 v3, vcc, s4, v3
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 12, v3
-; SI-NSZ-NEXT: v_or_b32_e32 v2, v7, v2
-; SI-NSZ-NEXT: v_or_b32_e32 v6, v0, v6
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v6, 7, v2
-; SI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; SI-NSZ-NEXT: v_or_b32_e32 v6, v6, v7
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; SI-NSZ-NEXT: v_mov_b32_e32 v6, 0x7c00
-; SI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v7, 0x7e00
-; SI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
-; SI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
-; SI-NSZ-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NSZ-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; SI-NSZ-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v4
-; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v5
-; SI-NSZ-NEXT: v_mul_f32_e32 v0, v1, v0
-; SI-NSZ-NEXT: v_mul_f32_e32 v1, v1, v2
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: free_fold_src_code_size_cost_use_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v2, v3, 2.0
+; VI-NEXT: v_mul_f16_e64 v0, -v1, v4
+; VI-NEXT: v_mul_f16_e64 v1, -v1, v5
+; VI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, v2, v3, 2.0
-; VI-SAFE-NEXT: v_mul_f16_e64 v0, -v1, v4
-; VI-SAFE-NEXT: v_mul_f16_e64 v1, -v1, v5
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v1, v2, -v3, -2.0
-; VI-NSZ-NEXT: v_mul_f16_e32 v0, v1, v4
-; VI-NSZ-NEXT: v_mul_f16_e32 v1, v1, v5
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-LABEL: free_fold_src_code_size_cost_use_f16:
-; GFX11-SAFE: ; %bb.0:
-; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-NEXT: v_fma_f16 v1, v2, v3, 2.0
-; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-NEXT: v_mul_f16_e64 v0, -v1, v4
-; GFX11-SAFE-NEXT: v_mul_f16_e64 v1, -v1, v5
-; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-LABEL: free_fold_src_code_size_cost_use_f16:
-; GFX11-NSZ: ; %bb.0:
-; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-NEXT: v_fma_f16 v1, v2, -v3, -2.0
-; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-NEXT: v_mul_f16_e32 v0, v1, v4
-; GFX11-NSZ-NEXT: v_mul_f16_e32 v1, v1, v5
-; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: free_fold_src_code_size_cost_use_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.h, v2.l, v3.l, 2.0
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.h, v4.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.h, v5.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: free_fold_src_code_size_cost_use_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.h, v2.l, -v3.l, -2.0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.h, v4.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, v0.h, v5.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: free_fold_src_code_size_cost_use_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v1, v2, v3, 2.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f16_e64 v0, -v1, v4
+; GFX11-NEXT: v_mul_f16_e64 v1, -v1, v5
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -6729,6 +4576,51 @@ define { half, half } @free_fold_src_code_size_cost_use_f16(ptr addrspace(1) %ou
ret { half, half } %insert.1
}
+define { half, half } @free_fold_src_code_size_cost_use_f16_nsz(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {
+; SI-LABEL: free_fold_src_code_size_cost_use_f16_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v5
+; SI-NEXT: v_fma_f32 v0, v1, -v0, -2.0
+; SI-NEXT: v_mul_f32_e32 v1, v0, v2
+; SI-NEXT: v_mul_f32_e32 v2, v0, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: free_fold_src_code_size_cost_use_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v2, -v3, -2.0
+; VI-NEXT: v_mul_f16_e32 v0, v1, v4
+; VI-NEXT: v_mul_f16_e32 v1, v1, v5
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: free_fold_src_code_size_cost_use_f16_nsz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_fma_f16 v1, v2, -v3, -2.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f16_e32 v0, v1, v4
+; GFX11-NEXT: v_mul_f16_e32 v1, v1, v5
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
+
+ %fma0 = call nsz half @llvm.fma.f16(half %a, half %b, half 2.0)
+ %fneg.fma0 = fneg half %fma0
+ %mul1 = fmul half %fneg.fma0, %c
+ %mul2 = fmul half %fneg.fma0, %d
+
+ %insert.0 = insertvalue { half, half } poison, half %mul1, 0
+ %insert.1 = insertvalue { half, half } %insert.0, half %mul2, 1
+ ret { half, half } %insert.1
+}
+
; %trunc.a has one fneg use, but it requires a code size increase and
; %the fneg can instead be folded for free into the fma.
define half @one_use_cost_to_fold_into_src_f16(ptr addrspace(1) %out, half %a, half %b, half %c, half %d) #0 {
@@ -6804,20 +4696,6 @@ define half @one_use_cost_to_fold_into_src_f16(ptr addrspace(1) %out, half %a, h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f16 v0, -v0, v3, v4
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: one_use_cost_to_fold_into_src_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: one_use_cost_to_fold_into_src_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v4.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -6907,22 +4785,6 @@ define { half, half } @multi_use_cost_to_fold_into_src(ptr addrspace(1) %out, ha
; GFX11-NEXT: v_fma_f16 v0, -v1, v3, v4
; GFX11-NEXT: v_mul_f16_e32 v1, v1, v5
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: multi_use_cost_to_fold_into_src:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_trunc_f16_e32 v0.h, v2.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v3.l, v4.l
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v1.l, v0.h, v5.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: multi_use_cost_to_fold_into_src:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_trunc_f16_e32 v0.h, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, -v0.h, v3.l, v4.l
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v1.l, v0.h, v5.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
@@ -7111,16 +4973,6 @@ define half @nnan_fmul_neg1_to_fneg(half %x, half %y) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: nnan_fmul_neg1_to_fneg:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: nnan_fmul_neg1_to_fneg:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul half %x, -1.0
%add = fmul nnan half %mul, %y
ret half %add
@@ -7149,16 +5001,6 @@ define half @denormal_fmul_neg1_to_fneg(half %x, half %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: denormal_fmul_neg1_to_fneg:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: denormal_fmul_neg1_to_fneg:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%mul = fmul nnan half %x, -1.0
%add = fmul half %mul, %y
ret half %add
@@ -7193,20 +5035,6 @@ define half @denorm_snan_fmul_neg1_to_fneg(half %x, half %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: denorm_snan_fmul_neg1_to_fneg:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: denorm_snan_fmul_neg1_to_fneg:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%canonical = fmul half %x, %x
%mul = fmul half %canonical, -1.0
%add = fmul half %mul, %y
@@ -7239,20 +5067,6 @@ define half @flush_snan_fmul_neg1_to_fneg(half %x, half %y) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: flush_snan_fmul_neg1_to_fneg:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: flush_snan_fmul_neg1_to_fneg:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%quiet = call half @llvm.canonicalize.f16(half %x)
%mul = fmul half %quiet, -1.0
%add = fmul half %mul, %y
@@ -7287,22 +5101,6 @@ define half @fadd_select_fneg_fneg_f16(i32 %arg0, half %x, half %y, half %z) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-SAFE-TRUE16-LABEL: fadd_select_fneg_fneg_f16:
-; GFX11-SAFE-TRUE16: ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NSZ-TRUE16-LABEL: fadd_select_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %arg0, 0
%neg.x = fneg half %x
%neg.y = fneg half %y
@@ -7376,8 +5174,4 @@ declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
-attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }
attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11-NSZ-FAKE16: {{.*}}
-; GFX11-SAFE-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
index 410316b1d4d76..4e42bf198c3a5 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
@@ -1,108 +1,60 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii -start-before=amdgpu-unify-divergent-exit-nodes -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,SI,SI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,SI,SI-NSZ %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii -start-before=amdgpu-unify-divergent-exit-nodes -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,VI,VI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,VI,VI-NSZ %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI %s
; --------------------------------------------------------------------------------
; fadd tests
; --------------------------------------------------------------------------------
define amdgpu_kernel void @v_fneg_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v5, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_add_f32_e32 v2, v5, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v5, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v5, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v5, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_add_f32_e32 v2, v5, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_endpgm
+; SI-LABEL: v_fneg_add_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v5, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_add_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v5, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v5, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_add_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v5, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -116,6 +68,65 @@ define amdgpu_kernel void @v_fneg_add_f32(ptr addrspace(1) %out, ptr addrspace(1
ret void
}
+define amdgpu_kernel void @v_fneg_add_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v5, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_sub_f32_e64 v2, -v5, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_add_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v5, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_sub_f32_e64 v2, -v5, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %add = fadd nsz float %a, %b
+ %fneg = fneg nsz float %add
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
define amdgpu_kernel void @v_fneg_add_store_use_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
; SI-LABEL: v_fneg_add_store_use_add_f32:
; SI: ; %bb.0:
@@ -183,111 +194,59 @@ define amdgpu_kernel void @v_fneg_add_store_use_add_f32(ptr addrspace(1) %out, p
}
define amdgpu_kernel void @v_fneg_add_multi_use_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_add_f32_e32 v2, v4, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; SI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_multi_use_add_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v4, v2
-; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; VI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+; SI-LABEL: v_fneg_add_multi_use_add_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_f32_e32 v2, v4, v2
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_add_multi_use_add_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v4, v2
-; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_add_multi_use_add_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; VI-NEXT: v_mul_f32_e32 v2, 4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -303,100 +262,58 @@ define amdgpu_kernel void @v_fneg_add_multi_use_add_f32(ptr addrspace(1) %out, p
ret void
}
-define amdgpu_kernel void @v_fneg_add_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_fneg_x_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_fneg_x_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_fneg_x_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_add_multi_use_add_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_multi_use_add_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_sub_f32_e64 v2, -v4, v2
+; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_add_fneg_x_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_add_multi_use_add_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_sub_f32_e64 v2, -v4, v2
+; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -404,107 +321,62 @@ define amdgpu_kernel void @v_fneg_add_fneg_x_f32(ptr addrspace(1) %out, ptr addr
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %fneg.a = fneg float %a
- %add = fadd float %fneg.a, %b
+ %add = fadd nsz float %a, %b
%fneg = fneg float %add
+ %use1 = fmul float %add, 4.0
store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_add_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_x_fneg_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_x_fneg_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_sub_f32_e32 v2, v1, v0
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_x_fneg_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_add_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_fneg_x_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_add_x_fneg_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_add_fneg_x_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -512,509 +384,58 @@ define amdgpu_kernel void @v_fneg_add_x_fneg_f32(ptr addrspace(1) %out, ptr addr
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %fneg.b = fneg float %b
- %add = fadd float %a, %fneg.b
+ %fneg.a = fneg float %a
+ %add = fadd float %fneg.a, %b
%fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_add_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_sub_f32_e64 v0, -v0, v1
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_add_f32_e32 v2, v0, v1
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_sub_f32_e64 v0, -v0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_add_f32_e32 v2, v0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %fneg.a = fneg float %a
- %fneg.b = fneg float %b
- %add = fadd float %fneg.a, %fneg.b
- %fneg = fneg float %add
- store volatile float %fneg, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; SI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; SI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; VI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; VI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %fneg.a = fneg float %a
- %add = fadd float %fneg.a, %b
- %fneg = fneg float %add
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %fneg.a, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_load_dword s2, s[4:5], 0xf
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v4, s2
-; SI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_load_dword s2, s[4:5], 0xf
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mul_f32_e64 v3, -v4, s2
-; SI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s6, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_load_dword s2, s[4:5], 0x3c
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v4, s2
-; VI-SAFE-NEXT: v_sub_f32_e32 v2, v2, v4
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s6, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_load_dword s2, s[4:5], 0x3c
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mul_f32_e64 v3, -v4, s2
-; VI-NSZ-NEXT: v_sub_f32_e32 v2, v4, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %fneg.a = fneg float %a
- %add = fadd float %fneg.a, %b
- %fneg = fneg float %add
- %use1 = fmul float %fneg.a, %c
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %use1, ptr addrspace(1) %out
- ret void
-}
-
-; This one asserted with -enable-no-signed-zeros-fp-math
-define amdgpu_ps float @fneg_fadd_0_safe(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr #0 {
-; SI-LABEL: fneg_fadd_0_safe:
-; SI: ; %bb.0: ; %.entry
-; SI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
-; SI-NEXT: v_rcp_f32_e32 v1, v0
-; SI-NEXT: v_div_scale_f32 v2, vcc, 1.0, s1, 1.0
-; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v3, -v0, v1, 1.0
-; SI-NEXT: v_fma_f32 v1, v3, v1, v1
-; SI-NEXT: v_mul_f32_e32 v3, v2, v1
-; SI-NEXT: v_fma_f32 v4, -v0, v3, v2
-; SI-NEXT: v_fma_f32 v3, v4, v1, v3
-; SI-NEXT: v_fma_f32 v0, -v0, v3, v2
-; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: v_div_fmas_f32 v0, v0, v1, v3
-; SI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0
-; SI-NEXT: v_mad_f32 v0, v0, 0, 0
-; SI-NEXT: v_mov_b32_e32 v1, s0
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
-; SI-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
-; SI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
-; SI-NEXT: ; return to shader part epilog
-;
-; VI-LABEL: fneg_fadd_0_safe:
-; VI: ; %bb.0: ; %.entry
-; VI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
-; VI-NEXT: v_div_scale_f32 v1, vcc, 1.0, s1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v2, v0
-; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v3, -v0, v2, 1.0
-; VI-NEXT: v_fma_f32 v2, v3, v2, v2
-; VI-NEXT: v_mul_f32_e32 v3, v1, v2
-; VI-NEXT: v_fma_f32 v4, -v0, v3, v1
-; VI-NEXT: v_fma_f32 v3, v4, v2, v3
-; VI-NEXT: v_fma_f32 v0, -v0, v3, v1
-; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v0, v0, v2, v3
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; VI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0
-; VI-NEXT: v_mad_f32 v0, v0, 0, 0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
-; VI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
-; VI-NEXT: ; return to shader part epilog
-.entry:
- %tmp7 = fdiv float 1.000000e+00, %tmp6
- %tmp8 = fmul float 0.000000e+00, %tmp7
- %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8
- %.i188 = fadd float %tmp9, 0.000000e+00
- %tmp10 = fcmp uge float %.i188, %tmp2
- %tmp11 = fneg float %.i188
- %.i092 = select i1 %tmp10, float %tmp2, float %tmp11
- %tmp12 = fcmp ule float %.i092, 0.000000e+00
- %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000
- ret float %.i198
-}
-
-define amdgpu_ps float @fneg_fadd_0_nsz(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr {
-; GCN-LABEL: fneg_fadd_0_nsz:
-; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: v_rcp_f32_e32 v0, s1
-; GCN-NEXT: v_mov_b32_e32 v1, s0
-; GCN-NEXT: v_mul_f32_e32 v0, 0, v0
-; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc
-; GCN-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
-; GCN-NEXT: ; return to shader part epilog
-.entry:
- %tmp7 = fdiv afn float 1.000000e+00, %tmp6
- %tmp8 = fmul float 0.000000e+00, %tmp7
- %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8
- %.i188 = fadd nsz float %tmp9, 0.000000e+00
- %tmp10 = fcmp uge float %.i188, %tmp2
- %tmp11 = fneg float %.i188
- %.i092 = select i1 %tmp10, float %tmp2, float %tmp11
- %tmp12 = fcmp ule float %.i092, 0.000000e+00
- %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000
- ret float %.i198
-}
-
-; --------------------------------------------------------------------------------
-; fmul tests
-; --------------------------------------------------------------------------------
-
-define amdgpu_kernel void @v_fneg_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_f32:
+define amdgpu_kernel void @v_fneg_add_fneg_x_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_fneg_x_f32_nsz:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v5, v[0:1] glc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_sub_f32_e32 v2, v0, v1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e64 v2, v5, -v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_f32:
+; VI-LABEL: v_fneg_add_fneg_x_f32_nsz:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v5, v[0:1] glc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e64 v2, v5, -v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
@@ -1023,14 +444,15 @@ define amdgpu_kernel void @v_fneg_mul_f32(ptr addrspace(1) %out, ptr addrspace(1
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %mul = fmul float %a, %b
- %fneg = fneg float %mul
- store float %fneg, ptr addrspace(1) %out.gep
+ %fneg.a = fneg float %a
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
+ store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_store_use_mul_f32:
+define amdgpu_kernel void @v_fneg_add_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_x_fneg_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1042,21 +464,19 @@ define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, p
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_mul_f32_e32 v2, v4, v2
-; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; SI-NEXT: flat_store_dword v[0:1], v3
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_store_use_mul_f32:
+; VI-LABEL: v_fneg_add_x_fneg_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1068,16 +488,14 @@ define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, p
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mul_f32_e32 v2, v4, v2
-; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; VI-NEXT: flat_store_dword v[0:1], v3
-; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
@@ -1088,15 +506,15 @@ define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, p
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %mul = fmul float %a, %b
- %fneg = fneg float %mul
+ %fneg.b = fneg float %b
+ %add = fadd float %a, %fneg.b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %mul, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_multi_use_mul_f32:
+define amdgpu_kernel void @v_fneg_add_x_fneg_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_x_fneg_f32_nsz:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1108,21 +526,18 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, p
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_sub_f32_e32 v2, v1, v0
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_mul_f32_e64 v2, v4, -v2
-; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_store_dword v[0:1], v3
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_multi_use_mul_f32:
+; VI-LABEL: v_fneg_add_x_fneg_f32_nsz:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1134,18 +549,15 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, p
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_sub_f32_e32 v2, v1, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mul_f32_e64 v2, v4, -v2
-; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_store_dword v[0:1], v3
-; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
@@ -1154,16 +566,15 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, p
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %mul = fmul float %a, %b
- %fneg = fneg float %mul
- %use1 = fmul float %mul, 4.0
+ %fneg.b = fneg float %b
+ %add = fadd nsz float %a, %fneg.b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_fneg_x_f32:
+define amdgpu_kernel void @v_fneg_add_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_fneg_fneg_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1179,14 +590,15 @@ define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addr
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, v0, v1
+; SI-NEXT: v_sub_f32_e64 v0, -v0, v1
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_fneg_x_f32:
+; VI-LABEL: v_fneg_add_fneg_fneg_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1202,7 +614,8 @@ define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addr
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mul_f32_e32 v2, v0, v1
+; VI-NEXT: v_sub_f32_e64 v0, -v0, v1
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -1216,14 +629,15 @@ define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addr
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%fneg.a = fneg float %a
- %mul = fmul float %fneg.a, %b
- %fneg = fneg float %mul
+ %fneg.b = fneg float %b
+ %add = fadd float %fneg.a, %fneg.b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_x_fneg_f32:
+define amdgpu_kernel void @v_fneg_add_fneg_fneg_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_fneg_fneg_f32_nsz:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1239,14 +653,14 @@ define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addr
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, v0, v1
+; SI-NEXT: v_add_f32_e32 v2, v0, v1
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_x_fneg_f32:
+; VI-LABEL: v_fneg_add_fneg_fneg_f32_nsz:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1262,7 +676,7 @@ define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addr
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mul_f32_e32 v2, v0, v1
+; VI-NEXT: v_add_f32_e32 v2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -1275,15 +689,16 @@ define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addr
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
%fneg.b = fneg float %b
- %mul = fmul float %a, %fneg.b
- %fneg = fneg float %mul
+ %add = fadd nsz float %fneg.a, %fneg.b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_fneg_fneg_f32:
+define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1295,18 +710,22 @@ define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr a
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e64 v2, v0, -v1
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
+; SI-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_fneg_fneg_f32:
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1318,15 +737,19 @@ define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr a
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mul_f32_e64 v2, v0, -v1
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
+; VI-NEXT: v_sub_f32_e32 v2, v2, v4
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
@@ -1336,15 +759,15 @@ define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr a
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%fneg.a = fneg float %a
- %fneg.b = fneg float %b
- %mul = fmul float %fneg.a, %fneg.b
- %fneg = fneg float %mul
+ %add = fadd float %fneg.a, %b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fneg.a, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_mul_store_use_fneg_x_f32:
+define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f32_nsz:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1363,14 +786,14 @@ define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; SI-NEXT: v_mul_f32_e32 v2, v4, v2
+; SI-NEXT: v_sub_f32_e32 v2, v4, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_store_dword v[0:1], v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_store_use_fneg_x_f32:
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f32_nsz:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1389,7 +812,7 @@ define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
-; VI-NEXT: v_mul_f32_e32 v2, v4, v2
+; VI-NEXT: v_sub_f32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v3
@@ -1403,15 +826,15 @@ define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%fneg.a = fneg float %a
- %mul = fmul float %fneg.a, %b
- %fneg = fneg float %mul
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
store volatile float %fneg, ptr addrspace(1) %out
store volatile float %fneg.a, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {
-; SI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:
+define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {
+; SI-LABEL: v_fneg_add_multi_use_fneg_x_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
@@ -1432,14 +855,15 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mul_f32_e64 v3, -v4, s2
-; SI-NEXT: v_mul_f32_e32 v2, v4, v2
+; SI-NEXT: v_sub_f32_e32 v2, v2, v4
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_store_dword v[0:1], v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:
+; VI-LABEL: v_fneg_add_multi_use_fneg_x_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -1460,7 +884,8 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mul_f32_e64 v3, -v4, s2
-; VI-NEXT: v_mul_f32_e32 v2, v4, v2
+; VI-NEXT: v_sub_f32_e32 v2, v2, v4
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v3
@@ -1474,20 +899,179 @@ define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%fneg.a = fneg float %a
- %mul = fmul float %fneg.a, %b
- %fneg = fneg float %mul
+ %add = fadd float %fneg.a, %b
+ %fneg = fneg float %add
+ %use1 = fmul float %fneg.a, %c
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {
+; SI-LABEL: v_fneg_add_multi_use_fneg_x_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s2, s[4:5], 0xf
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mul_f32_e64 v3, -v4, s2
+; SI-NEXT: v_sub_f32_e32 v2, v4, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_add_multi_use_fneg_x_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s2, s[4:5], 0x3c
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mul_f32_e64 v3, -v4, s2
+; VI-NEXT: v_sub_f32_e32 v2, v4, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
%use1 = fmul float %fneg.a, %c
store volatile float %fneg, ptr addrspace(1) %out
store volatile float %use1, ptr addrspace(1) %out
ret void
}
+; This one asserted with -enable-no-signed-zeros-fp-math
+define amdgpu_ps float @fneg_fadd_0_safe(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr #0 {
+; SI-LABEL: fneg_fadd_0_safe:
+; SI: ; %bb.0: ; %.entry
+; SI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
+; SI-NEXT: v_rcp_f32_e32 v1, v0
+; SI-NEXT: v_div_scale_f32 v2, vcc, 1.0, s1, 1.0
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; SI-NEXT: v_fma_f32 v1, v3, v1, v1
+; SI-NEXT: v_mul_f32_e32 v3, v2, v1
+; SI-NEXT: v_fma_f32 v4, -v0, v3, v2
+; SI-NEXT: v_fma_f32 v3, v4, v1, v3
+; SI-NEXT: v_fma_f32 v0, -v0, v3, v2
+; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; SI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0
+; SI-NEXT: v_mad_f32 v0, v0, 0, 0
+; SI-NEXT: v_mov_b32_e32 v1, s0
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
+; SI-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
+; SI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: fneg_fadd_0_safe:
+; VI: ; %bb.0: ; %.entry
+; VI-NEXT: v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
+; VI-NEXT: v_div_scale_f32 v1, vcc, 1.0, s1, 1.0
+; VI-NEXT: v_rcp_f32_e32 v2, v0
+; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT: v_fma_f32 v3, -v0, v2, 1.0
+; VI-NEXT: v_fma_f32 v2, v3, v2, v2
+; VI-NEXT: v_mul_f32_e32 v3, v1, v2
+; VI-NEXT: v_fma_f32 v4, -v0, v3, v1
+; VI-NEXT: v_fma_f32 v3, v4, v2, v3
+; VI-NEXT: v_fma_f32 v0, -v0, v3, v1
+; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT: v_div_fmas_f32 v0, v0, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; VI-NEXT: v_div_fixup_f32 v0, v0, s1, 1.0
+; VI-NEXT: v_mad_f32 v0, v0, 0, 0
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc
+; VI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-NEXT: ; return to shader part epilog
+.entry:
+ %tmp7 = fdiv float 1.000000e+00, %tmp6
+ %tmp8 = fmul float 0.000000e+00, %tmp7
+ %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8
+ %.i188 = fadd float %tmp9, 0.000000e+00
+ %tmp10 = fcmp uge float %.i188, %tmp2
+ %tmp11 = fneg float %.i188
+ %.i092 = select i1 %tmp10, float %tmp2, float %tmp11
+ %tmp12 = fcmp ule float %.i092, 0.000000e+00
+ %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000
+ ret float %.i198
+}
+
+define amdgpu_ps float @fneg_fadd_0_nsz(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) local_unnamed_addr {
+; GCN-LABEL: fneg_fadd_0_nsz:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: v_rcp_f32_e32 v0, s1
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: v_mul_f32_e32 v0, 0, v0
+; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, 0x7fc00000
+; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; GCN-NEXT: ; return to shader part epilog
+.entry:
+ %tmp7 = fdiv afn float 1.000000e+00, %tmp6
+ %tmp8 = fmul float 0.000000e+00, %tmp7
+ %tmp9 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp8
+ %.i188 = fadd nsz float %tmp9, 0.000000e+00
+ %tmp10 = fcmp uge float %.i188, %tmp2
+ %tmp11 = fneg float %.i188
+ %.i092 = select i1 %tmp10, float %tmp2, float %tmp11
+ %tmp12 = fcmp ule float %.i092, 0.000000e+00
+ %.i198 = select i1 %tmp12, float 0.000000e+00, float 0x7FF8000000000000
+ ret float %.i198
+}
+
; --------------------------------------------------------------------------------
-; fminnum tests
+; fmul tests
; --------------------------------------------------------------------------------
-define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1506,13 +1090,11 @@ define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr add
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v3, -1.0, v5
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; SI-NEXT: v_max_f32_e32 v2, v3, v2
+; SI-NEXT: v_mul_f32_e64 v2, v5, -v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_minnum_f32_ieee:
+; VI-LABEL: v_fneg_mul_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1531,9 +1113,7 @@ define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr add
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v3, -1.0, v5
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; VI-NEXT: v_max_f32_e32 v2, v3, v2
+; VI-NEXT: v_mul_f32_e64 v2, v5, -v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1543,1167 +1123,1174 @@ define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr add
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %min = call float @llvm.minnum.f32(float %a, float %b)
- %fneg = fneg float %min
+ %mul = fmul float %a, %b
+ %fneg = fneg float %mul
store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_minnum_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_minnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float %a, float %b)
- %fneg = fneg float %min
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_self_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_self_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_mul_store_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_store_use_mul_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, v2, v2
+; SI-NEXT: v_mul_f32_e32 v2, v4, v2
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_self_minnum_f32_ieee:
+; VI-LABEL: v_fneg_mul_store_use_mul_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_max_f32_e32 v2, v2, v2
+; VI-NEXT: v_mul_f32_e32 v2, v4, v2
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float %a, float %a)
- %min.fneg = fneg float %min
- store float %min.fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %mul = fmul float %a, %b
+ %fneg = fneg float %mul
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %mul, ptr addrspace(1) %out
ret void
}
-define amdgpu_ps float @v_fneg_self_minnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_self_minnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, -v0
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float %a, float %a)
- %min.fneg = fneg float %min
- ret float %min.fneg
-}
-
-define amdgpu_kernel void @v_fneg_posk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_posk_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_multi_use_mul_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, -4.0, v2
+; SI-NEXT: v_mul_f32_e64 v2, v4, -v2
+; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_posk_minnum_f32_ieee:
+; VI-LABEL: v_fneg_mul_multi_use_mul_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_max_f32_e32 v2, -4.0, v2
+; VI-NEXT: v_mul_f32_e64 v2, v4, -v2
+; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float 4.0, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %mul = fmul float %a, %b
+ %fneg = fneg float %mul
+ %use1 = fmul float %mul, 4.0
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_ps float @v_fneg_posk_minnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_posk_minnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, -4.0
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float 4.0, float %a)
- %fneg = fneg float %min
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_negk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_negk_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_mul_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_fneg_x_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, v0, v1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, 4.0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_negk_minnum_f32_ieee:
+; VI-LABEL: v_fneg_mul_fneg_x_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mul_f32_e32 v2, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_max_f32_e32 v2, 4.0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float -4.0, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
+ %mul = fmul float %fneg.a, %b
+ %fneg = fneg float %mul
+ store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_ps float @v_fneg_negk_minnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_negk_minnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, 4.0
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float -4.0, float %a)
- %fneg = fneg float %min
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_0_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_0_minnum_f32:
+define amdgpu_kernel void @v_fneg_mul_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_x_fneg_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, v0, v1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_min_f32_e32 v2, 0, v3
-; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_0_minnum_f32:
+; VI-LABEL: v_fneg_mul_x_fneg_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mul_f32_e32 v2, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_min_f32_e32 v2, 0, v3
-; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call nnan float @llvm.minnum.f32(float 0.0, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.b = fneg float %b
+ %mul = fmul float %a, %fneg.b
+ %fneg = fneg float %mul
+ store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_neg0_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_neg0_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_mul_fneg_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_fneg_fneg_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e64 v2, v0, -v1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, 0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_neg0_minnum_f32_ieee:
+; VI-LABEL: v_fneg_mul_fneg_fneg_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mul_f32_e64 v2, v0, -v1
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_max_f32_e32 v2, 0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float -0.0, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
+ %fneg.b = fneg float %b
+ %mul = fmul float %fneg.a, %fneg.b
+ %fneg = fneg float %mul
+ store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_inv2pi_minnum_f32:
+define amdgpu_kernel void @v_fneg_mul_store_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_mul_store_use_fneg_x_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v2
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
+; SI-NEXT: v_mul_f32_e32 v2, v4, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_inv2pi_minnum_f32:
+; VI-LABEL: v_fneg_mul_store_use_fneg_x_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
-; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v4
+; VI-NEXT: v_mul_f32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
+ %mul = fmul float %fneg.a, %b
+ %fneg = fneg float %mul
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fneg.a, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_neg_inv2pi_minnum_f32:
+define amdgpu_kernel void @v_fneg_mul_multi_use_fneg_x_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, float %c) #0 {
+; SI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s2, s[4:5], 0xf
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_max_f32_e32 v2, 0x3e22f983, v2
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mul_f32_e64 v3, -v4, s2
+; SI-NEXT: v_mul_f32_e32 v2, v4, v2
; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_neg_inv2pi_minnum_f32:
+; VI-LABEL: v_fneg_mul_multi_use_fneg_x_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s2, s[4:5], 0x3c
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_max_f32_e32 v2, 0.15915494, v2
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mul_f32_e64 v3, -v4, s2
+; VI-NEXT: v_mul_f32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %min = call float @llvm.minnum.f32(float 0xBFC45F3060000000, float %a)
- %fneg = fneg float %min
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %fneg.a = fneg float %a
+ %mul = fmul float %fneg.a, %b
+ %fneg = fneg float %mul
+ %use1 = fmul float %fneg.a, %c
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_inv2pi_minnum_f16:
+; --------------------------------------------------------------------------------
+; fminnum tests
+; --------------------------------------------------------------------------------
+
+define amdgpu_kernel void @v_fneg_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_ushort v0, v[0:1] glc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v5, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NEXT: v_max_f32_e32 v0, 0xbe230000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_store_short v[0:1], v3
+; SI-NEXT: v_mul_f32_e32 v3, -1.0, v5
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; SI-NEXT: v_max_f32_e32 v2, v3, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_inv2pi_minnum_f16:
+; VI-LABEL: v_fneg_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_ushort v3, v[0:1] glc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v5, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_max_f16_e32 v2, v3, v3
-; VI-NEXT: v_min_f16_e32 v2, 0.15915494, v2
-; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; VI-NEXT: v_mul_f32_e32 v3, -1.0, v5
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; VI-NEXT: v_max_f32_e32 v2, v3, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile half, ptr addrspace(1) %a.gep
- %min = call half @llvm.minnum.f16(half 0xH3118, half %a)
- %fneg = fsub half -0.000000e+00, %min
- store half %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %min = call float @llvm.minnum.f32(float %a, float %b)
+ %fneg = fneg float %min
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_neg_inv2pi_minnum_f16:
+define amdgpu_ps float @v_fneg_minnum_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_minnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
+; GCN-NEXT: ; return to shader part epilog
+ %min = call float @llvm.minnum.f32(float %a, float %b)
+ %fneg = fneg float %min
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_self_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_self_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_ushort v0, v[0:1] glc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NEXT: v_max_f32_e32 v0, 0x3e230000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_store_short v[0:1], v3
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, v2, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_neg_inv2pi_minnum_f16:
+; VI-LABEL: v_fneg_self_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_ushort v3, v[0:1] glc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_max_f16_e64 v2, -v3, -v3
-; VI-NEXT: v_max_f16_e32 v2, 0.15915494, v2
-; VI-NEXT: flat_store_short v[0:1], v2
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_max_f32_e32 v2, v2, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile half, ptr addrspace(1) %a.gep
- %min = call half @llvm.minnum.f16(half 0xHB118, half %a)
- %fneg = fsub half -0.000000e+00, %min
- store half %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %min = call float @llvm.minnum.f32(float %a, float %a)
+ %min.fneg = fneg float %min
+ store float %min.fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_inv2pi_minnum_f64:
+define amdgpu_ps float @v_fneg_self_minnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_self_minnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_max_f32_e64 v0, -v0, -v0
+; GCN-NEXT: ; return to shader part epilog
+ %min = call float @llvm.minnum.f32(float %a, float %a)
+ %min.fneg = fneg float %min
+ ret float %min.fneg
+}
+
+define amdgpu_kernel void @v_fneg_posk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_posk_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: s_mov_b32 s2, 0x6dc9c882
-; SI-NEXT: s_mov_b32 s3, 0xbfc45f30
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
-; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
-; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, -4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_inv2pi_minnum_f64:
+; VI-LABEL: v_fneg_posk_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; VI-NEXT: v_min_f64 v[0:1], v[0:1], 0.15915494309189532
-; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: s_endpgm
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_max_f32_e32 v2, -4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile double, ptr addrspace(1) %a.gep
- %min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a)
- %fneg = fsub double -0.000000e+00, %min
- store double %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %min = call float @llvm.minnum.f32(float 4.0, float %a)
+ %fneg = fneg float %min
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_neg_inv2pi_minnum_f64:
+define amdgpu_ps float @v_fneg_posk_minnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_posk_minnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_max_f32_e64 v0, -v0, -4.0
+; GCN-NEXT: ; return to shader part epilog
+ %min = call float @llvm.minnum.f32(float 4.0, float %a)
+ %fneg = fneg float %min
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_negk_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_negk_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: s_mov_b32 s2, 0x6dc9c882
-; SI-NEXT: s_mov_b32 s3, 0x3fc45f30
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
-; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
-; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, 4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_neg_inv2pi_minnum_f64:
+; VI-LABEL: v_fneg_negk_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
-; VI-NEXT: v_max_f64 v[0:1], v[0:1], 0.15915494309189532
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_max_f32_e32 v2, 4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile double, ptr addrspace(1) %a.gep
- %min = call double @llvm.minnum.f64(double 0xbfc45f306dc9c882, double %a)
- %fneg = fsub double -0.000000e+00, %min
- store double %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %min = call float @llvm.minnum.f32(float -4.0, float %a)
+ %fneg = fneg float %min
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_neg0_minnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_neg0_minnum_f32_no_ieee:
+define amdgpu_ps float @v_fneg_negk_minnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_negk_minnum_f32_no_ieee:
; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, 0
+; GCN-NEXT: v_max_f32_e64 v0, -v0, 4.0
; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float -0.0, float %a)
+ %min = call float @llvm.minnum.f32(float -4.0, float %a)
%fneg = fneg float %min
ret float %fneg
}
-define amdgpu_kernel void @v_fneg_0_minnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:
+define amdgpu_kernel void @v_fneg_0_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_0_minnum_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; SI-NEXT: v_min_f32_e32 v2, 0, v2
-; SI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; SI-NEXT: v_min_f32_e32 v2, 0, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:
+; VI-LABEL: v_fneg_0_minnum_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; VI-NEXT: v_min_f32_e32 v2, 0, v2
-; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; VI-NEXT: v_min_f32_e32 v2, 0, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %min = call float @llvm.minnum.f32(float 0.0, float %a)
+ %min = call nnan float @llvm.minnum.f32(float 0.0, float %a)
%fneg = fneg float %min
- %mul = fmul float %fneg, %b
- store float %mul, ptr addrspace(1) %out.gep
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_inv2pi_minnum_foldable_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:
+define amdgpu_kernel void @v_fneg_neg0_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_neg0_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v4
-; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v2
-; SI-NEXT: v_mul_f32_e32 v2, v2, v3
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, 0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:
+; VI-LABEL: v_fneg_neg0_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
-; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_max_f32_e32 v2, 0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)
+ %min = call float @llvm.minnum.f32(float -0.0, float %a)
%fneg = fneg float %min
- %mul = fmul float %fneg, %b
- store float %mul, ptr addrspace(1) %out.gep
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_0_minnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_0_minnum_foldable_use_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e32 v0, 0, v0
-; GCN-NEXT: v_mul_f32_e64 v0, -v0, v1
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float 0.0, float %a)
- %fneg = fneg float %min
- %mul = fmul float %fneg, %b
- ret float %mul
-}
-
-define amdgpu_kernel void @v_fneg_minnum_multi_use_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_inv2pi_minnum_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v4, v[0:1] glc
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_mul_f32_e32 v3, -1.0, v4
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; SI-NEXT: v_max_f32_e32 v2, v3, v2
-; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v2
; SI-NEXT: flat_store_dword v[0:1], v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_store_dword v[0:1], v3
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:
+; VI-LABEL: v_fneg_inv2pi_minnum_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
-; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v4, v[0:1] glc
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mul_f32_e32 v3, -1.0, v4
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; VI-NEXT: v_max_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, 1.0, v3
+; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_store_dword v[0:1], v3
-; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %min = call float @llvm.minnum.f32(float %a, float %b)
+ %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)
%fneg = fneg float %min
- %use1 = fmul float %min, 4.0
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %use1, ptr addrspace(1) %out
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_minnum_multi_use_minnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
-; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
-; GCN-NEXT: ; return to shader part epilog
- %min = call float @llvm.minnum.f32(float %a, float %b)
- %fneg = fneg float %min
- %use1 = fmul float %min, 4.0
- %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
- %ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
- ret <2 x float> %ins1
-}
-
-; --------------------------------------------------------------------------------
-; fmaxnum tests
-; --------------------------------------------------------------------------------
-
-define amdgpu_kernel void @v_fneg_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_maxnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_neg_inv2pi_minnum_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: flat_load_dword v5, v[0:1] glc
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v3, -1.0, v5
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; SI-NEXT: v_min_f32_e32 v2, v3, v2
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_max_f32_e32 v2, 0x3e22f983, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_neg_inv2pi_minnum_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: flat_load_dword v5, v[0:1] glc
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v3, -1.0, v5
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; VI-NEXT: v_min_f32_e32 v2, v3, v2
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_max_f32_e32 v2, 0.15915494, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %max = call float @llvm.maxnum.f32(float %a, float %b)
- %fneg = fneg float %max
+ %min = call float @llvm.minnum.f32(float 0xBFC45F3060000000, float %a)
+ %fneg = fneg float %min
store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_maxnum_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_maxnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
-; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float %a, float %b)
- %fneg = fneg float %max
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_self_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_self_maxnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_inv2pi_minnum_f16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: flat_load_ushort v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_max_f32_e32 v0, 0xbe230000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_min_f32_e32 v2, v2, v2
-; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: flat_store_short v[0:1], v3
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_self_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_inv2pi_minnum_f16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: flat_load_ushort v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_min_f32_e32 v2, v2, v2
-; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: v_max_f16_e32 v2, v3, v3
+; VI-NEXT: v_min_f16_e32 v2, 0.15915494, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v2
+; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %max = call float @llvm.maxnum.f32(float %a, float %a)
- %max.fneg = fneg float %max
- store float %max.fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile half, ptr addrspace(1) %a.gep
+ %min = call half @llvm.minnum.f16(half 0xH3118, half %a)
+ %fneg = fsub half -0.000000e+00, %min
+ store half %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_self_maxnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_self_maxnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, -v0
-; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float %a, float %a)
- %max.fneg = fneg float %max
- ret float %max.fneg
-}
-
-define amdgpu_kernel void @v_fneg_posk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_posk_maxnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_neg_inv2pi_minnum_f16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: flat_load_ushort v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_max_f32_e32 v0, 0x3e230000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_min_f32_e32 v2, -4.0, v2
-; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: flat_store_short v[0:1], v3
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_posk_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_neg_inv2pi_minnum_f16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: flat_load_ushort v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_min_f32_e32 v2, -4.0, v2
-; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: v_max_f16_e64 v2, -v3, -v3
+; VI-NEXT: v_max_f16_e32 v2, 0.15915494, v2
+; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %max = call float @llvm.maxnum.f32(float 4.0, float %a)
- %fneg = fneg float %max
- store float %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds half, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile half, ptr addrspace(1) %a.gep
+ %min = call half @llvm.minnum.f16(half 0xHB118, half %a)
+ %fneg = fsub half -0.000000e+00, %min
+ store half %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_posk_maxnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_posk_maxnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, -4.0
-; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float 4.0, float %a)
- %fneg = fneg float %max
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_negk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_negk_maxnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_inv2pi_minnum_f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; SI-NEXT: v_min_f32_e32 v2, 4.0, v2
-; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_mov_b32 s2, 0x6dc9c882
+; SI-NEXT: s_mov_b32 s3, 0xbfc45f30
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
+; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
+; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_negk_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_inv2pi_minnum_f64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
-; VI-NEXT: v_min_f32_e32 v2, 4.0, v2
-; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; VI-NEXT: v_min_f64 v[0:1], v[0:1], 0.15915494309189532
+; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %max = call float @llvm.maxnum.f32(float -4.0, float %a)
- %fneg = fneg float %max
- store float %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile double, ptr addrspace(1) %a.gep
+ %min = call double @llvm.minnum.f64(double 0x3fc45f306dc9c882, double %a)
+ %fneg = fsub double -0.000000e+00, %min
+ store double %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_negk_maxnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_negk_maxnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, 4.0
-; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float -4.0, float %a)
- %fneg = fneg float %max
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_0_maxnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_0_maxnum_f32:
+define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_neg_inv2pi_minnum_f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_max_f32_e32 v2, 0, v3
-; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_mov_b32 s2, 0x6dc9c882
+; SI-NEXT: s_mov_b32 s3, 0x3fc45f30
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
+; SI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
+; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_0_maxnum_f32:
+; VI-LABEL: v_fneg_neg_inv2pi_minnum_f64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_max_f32_e32 v2, 0, v3
-; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
+; VI-NEXT: v_max_f64 v[0:1], v[0:1], 0.15915494309189532
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %max = call nnan float @llvm.maxnum.f32(float 0.0, float %a)
- %fneg = fneg float %max
- store float %fneg, ptr addrspace(1) %out.gep
+ %a.gep = getelementptr inbounds double, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile double, ptr addrspace(1) %a.gep
+ %min = call double @llvm.minnum.f64(double 0xbfc45f306dc9c882, double %a)
+ %fneg = fsub double -0.000000e+00, %min
+ store double %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_neg0_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-LABEL: v_fneg_neg0_maxnum_f32_ieee:
+define amdgpu_ps float @v_fneg_neg0_minnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_neg0_minnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_max_f32_e64 v0, -v0, 0
+; GCN-NEXT: ; return to shader part epilog
+ %min = call float @llvm.minnum.f32(float -0.0, float %a)
+ %fneg = fneg float %min
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_0_minnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; SI-NEXT: flat_load_dword v3, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
; SI-NEXT: v_min_f32_e32 v2, 0, v2
+; SI-NEXT: v_mul_f32_e64 v2, -v2, v3
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_neg0_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_0_minnum_foldable_use_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
; VI-NEXT: v_min_f32_e32 v2, 0, v2
+; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
- %max = call float @llvm.maxnum.f32(float -0.0, float %a)
- %fneg = fneg float %max
- store float %fneg, ptr addrspace(1) %out.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %min = call float @llvm.minnum.f32(float 0.0, float %a)
+ %fneg = fneg float %min
+ %mul = fmul float %fneg, %b
+ store float %mul, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_neg0_maxnum_f32_no_ieee(float %a) #0 {
-; GCN-LABEL: v_fneg_neg0_maxnum_f32_no_ieee:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, 0
-; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float -0.0, float %a)
- %fneg = fneg float %max
- ret float %fneg
-}
-
-define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:
+define amdgpu_kernel void @v_fneg_inv2pi_minnum_foldable_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -2722,13 +2309,13 @@ define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; SI-NEXT: v_max_f32_e32 v2, 0, v2
-; SI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v4
+; SI-NEXT: v_max_f32_e32 v2, 0xbe22f983, v2
+; SI-NEXT: v_mul_f32_e32 v2, v2, v3
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:
+; VI-LABEL: v_fneg_inv2pi_minnum_foldable_use_f32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -2748,7 +2335,7 @@ define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; VI-NEXT: v_max_f32_e32 v2, 0, v2
+; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -2759,27 +2346,27 @@ define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %max = call float @llvm.maxnum.f32(float 0.0, float %a)
- %fneg = fneg float %max
+ %min = call float @llvm.minnum.f32(float 0x3FC45F3060000000, float %a)
+ %fneg = fneg float %min
%mul = fmul float %fneg, %b
store float %mul, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_ps float @v_fneg_0_maxnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_0_maxnum_foldable_use_f32_no_ieee:
+define amdgpu_ps float @v_fneg_0_minnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_0_minnum_foldable_use_f32_no_ieee:
; GCN: ; %bb.0:
-; GCN-NEXT: v_max_f32_e32 v0, 0, v0
+; GCN-NEXT: v_min_f32_e32 v0, 0, v0
; GCN-NEXT: v_mul_f32_e64 v0, -v0, v1
; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float 0.0, float %a)
- %fneg = fneg float %max
+ %min = call float @llvm.minnum.f32(float 0.0, float %a)
+ %fneg = fneg float %min
%mul = fmul float %fneg, %b
ret float %mul
}
-define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
-; SI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:
+define amdgpu_kernel void @v_fneg_minnum_multi_use_minnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -2799,7 +2386,7 @@ define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_mul_f32_e32 v3, -1.0, v4
; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; SI-NEXT: v_min_f32_e32 v2, v3, v2
+; SI-NEXT: v_max_f32_e32 v2, v3, v2
; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -2807,7 +2394,7 @@ define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:
+; VI-LABEL: v_fneg_minnum_multi_use_minnum_f32_ieee:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -2827,7 +2414,7 @@ define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mul_f32_e32 v3, -1.0, v4
; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
-; VI-NEXT: v_min_f32_e32 v2, v3, v2
+; VI-NEXT: v_max_f32_e32 v2, v3, v2
; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -2841,161 +2428,37 @@ define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %max = call float @llvm.maxnum.f32(float %a, float %b)
- %fneg = fneg float %max
- %use1 = fmul float %max, 4.0
+ %min = call float @llvm.minnum.f32(float %a, float %b)
+ %fneg = fneg float %min
+ %use1 = fmul float %min, 4.0
store volatile float %fneg, ptr addrspace(1) %out
store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_ps <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %a, float %b) #0 {
-; GCN-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_no_ieee:
+define amdgpu_ps <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_minnum_multi_use_minnum_f32_no_ieee:
; GCN: ; %bb.0:
-; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
+; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
; GCN-NEXT: ; return to shader part epilog
- %max = call float @llvm.maxnum.f32(float %a, float %b)
- %fneg = fneg float %max
- %use1 = fmul float %max, 4.0
+ %min = call float @llvm.minnum.f32(float %a, float %b)
+ %fneg = fneg float %min
+ %use1 = fmul float %min, 4.0
%ins0 = insertelement <2 x float> poison, float %fneg, i32 0
%ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
ret <2 x float> %ins1
}
; --------------------------------------------------------------------------------
-; fma tests
+; fmaxnum tests
; --------------------------------------------------------------------------------
-define amdgpu_kernel void @v_fneg_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_fma_f32 v2, v7, v2, v3
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_fma_f32 v2, v7, -v2, -v3
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_fma_f32 v2, v7, v2, v3
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_fma_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_fma_f32 v2, v7, -v2, -v3
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %c = load volatile float, ptr addrspace(1) %c.gep
- %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
- %fneg = fneg float %fma
- store float %fneg, ptr addrspace(1) %out.gep
- ret void
-}
-
-define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-LABEL: v_fneg_fma_store_use_fma_f32:
+define amdgpu_kernel void @v_fneg_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_maxnum_f32_ieee:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s3
@@ -3004,28 +2467,23 @@ define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(ptr addrspace(1) %out, p
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s7
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: flat_load_dword v5, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: v_fma_f32 v2, v6, v2, v3
-; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; SI-NEXT: flat_store_dword v[0:1], v3
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v3, -1.0, v5
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; SI-NEXT: v_min_f32_e32 v2, v3, v2
; SI-NEXT: flat_store_dword v[0:1], v2
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
;
-; VI-LABEL: v_fneg_fma_store_use_fma_f32:
+; VI-LABEL: v_fneg_maxnum_f32_ieee:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
@@ -3034,541 +2492,1627 @@ define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(ptr addrspace(1) %out, p
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT: v_mov_b32_e32 v5, s7
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: flat_load_dword v5, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_fma_f32 v2, v6, v2, v3
-; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; VI-NEXT: flat_store_dword v[0:1], v3
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v3, -1.0, v5
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; VI-NEXT: v_min_f32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
- %c = load volatile float, ptr addrspace(1) %c.gep
- %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
- %fneg = fneg float %fma
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %fma, ptr addrspace(1) %out
+ %max = call float @llvm.maxnum.f32(float %a, float %b)
+ %fneg = fneg float %max
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_fma_f32 v2, v6, v2, v3
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; SI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_fma_f32 v2, v6, -v2, -v3
-; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_fma_f32 v2, v6, v2, v3
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
-; VI-SAFE-NEXT: v_mul_f32_e32 v2, 4.0, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_fma_f32 v2, v6, -v2, -v3
-; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %c = load volatile float, ptr addrspace(1) %c.gep
- %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
- %fneg = fneg float %fma
- %use1 = fmul float %fma, 4.0
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %use1, ptr addrspace(1) %out
- ret void
+define amdgpu_ps float @v_fneg_maxnum_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float %a, float %b)
+ %fneg = fneg float %max
+ ret float %fneg
}
-define amdgpu_kernel void @v_fneg_fma_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
-;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %tid.ext = sext i32 %tid to i64
- %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
- %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
- %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
- %a = load volatile float, ptr addrspace(1) %a.gep
- %b = load volatile float, ptr addrspace(1) %b.gep
- %c = load volatile float, ptr addrspace(1) %c.gep
- %fneg.a = fneg float %a
- %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
- %fneg = fneg float %fma
- store volatile float %fneg, ptr addrspace(1) %out
- ret void
+define amdgpu_kernel void @v_fneg_self_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_self_maxnum_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_min_f32_e32 v2, v2, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_self_maxnum_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_min_f32_e32 v2, v2, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %max = call float @llvm.maxnum.f32(float %a, float %a)
+ %max.fneg = fneg float %max
+ store float %max.fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_ps float @v_fneg_self_maxnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_self_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, -v0
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float %a, float %a)
+ %max.fneg = fneg float %max
+ ret float %max.fneg
+}
+
+define amdgpu_kernel void @v_fneg_posk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_posk_maxnum_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_min_f32_e32 v2, -4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_posk_maxnum_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_min_f32_e32 v2, -4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %max = call float @llvm.maxnum.f32(float 4.0, float %a)
+ %fneg = fneg float %max
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_ps float @v_fneg_posk_maxnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_posk_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, -4.0
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float 4.0, float %a)
+ %fneg = fneg float %max
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_negk_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_negk_maxnum_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_min_f32_e32 v2, 4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_negk_maxnum_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_min_f32_e32 v2, 4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %max = call float @llvm.maxnum.f32(float -4.0, float %a)
+ %fneg = fneg float %max
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_ps float @v_fneg_negk_maxnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_negk_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, 4.0
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float -4.0, float %a)
+ %fneg = fneg float %max
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_0_maxnum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_0_maxnum_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_max_f32_e32 v2, 0, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_0_maxnum_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_max_f32_e32 v2, 0, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %max = call nnan float @llvm.maxnum.f32(float 0.0, float %a)
+ %fneg = fneg float %max
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_neg0_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_neg0_maxnum_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; SI-NEXT: v_min_f32_e32 v2, 0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_neg0_maxnum_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
+; VI-NEXT: v_min_f32_e32 v2, 0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %max = call float @llvm.maxnum.f32(float -0.0, float %a)
+ %fneg = fneg float %max
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_ps float @v_fneg_neg0_maxnum_f32_no_ieee(float %a) #0 {
+; GCN-LABEL: v_fneg_neg0_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, 0
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float -0.0, float %a)
+ %fneg = fneg float %max
+ ret float %fneg
+}
+
+define amdgpu_kernel void @v_fneg_0_maxnum_foldable_use_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; SI-NEXT: v_max_f32_e32 v2, 0, v2
+; SI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_0_maxnum_foldable_use_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
+; VI-NEXT: v_max_f32_e32 v2, 0, v2
+; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %max = call float @llvm.maxnum.f32(float 0.0, float %a)
+ %fneg = fneg float %max
+ %mul = fmul float %fneg, %b
+ store float %mul, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_ps float @v_fneg_0_maxnum_foldable_use_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_0_maxnum_foldable_use_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_max_f32_e32 v0, 0, v0
+; GCN-NEXT: v_mul_f32_e64 v0, -v0, v1
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float 0.0, float %a)
+ %fneg = fneg float %max
+ %mul = fmul float %fneg, %b
+ ret float %mul
+}
+
+define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
+; SI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: flat_load_dword v4, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_mul_f32_e32 v3, -1.0, v4
+; SI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; SI-NEXT: v_min_f32_e32 v2, v3, v2
+; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_ieee:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mul_f32_e32 v3, -1.0, v4
+; VI-NEXT: v_mul_f32_e32 v2, -1.0, v2
+; VI-NEXT: v_min_f32_e32 v2, v3, v2
+; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %max = call float @llvm.maxnum.f32(float %a, float %b)
+ %fneg = fneg float %max
+ %use1 = fmul float %max, 4.0
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_maxnum_multi_use_maxnum_f32_no_ieee:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
+; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; GCN-NEXT: ; return to shader part epilog
+ %max = call float @llvm.maxnum.f32(float %a, float %b)
+ %fneg = fneg float %max
+ %use1 = fmul float %max, 4.0
+ %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
+ %ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
+ ret <2 x float> %ins1
+}
+
+; --------------------------------------------------------------------------------
+; fma tests
+; --------------------------------------------------------------------------------
+
+define amdgpu_kernel void @v_fneg_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v7, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_fma_f32 v2, v7, v2, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v7, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_fma_f32 v2, v7, v2, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v7, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_fma_f32 v2, v7, -v2, -v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v7, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_fma_f32 v2, v7, -v2, -v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_store_use_fma_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_fma_f32 v2, v6, v2, v3
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_store_use_fma_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_fma_f32 v2, v6, v2, v3
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fma, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_store_use_fma_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_fma_f32 v2, v6, v2, v3
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_store_use_fma_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_fma_f32 v2, v6, v2, v3
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fma, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fma_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_fma_f32 v2, v6, v2, v3
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; SI-NEXT: v_mul_f32_e32 v2, 4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_multi_use_fma_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_fma_f32 v2, v6, v2, v3
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v2
+; VI-NEXT: v_mul_f32_e32 v2, 4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fma, 4.0
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fma_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_fma_f32 v2, v6, -v2, -v3
+; SI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_multi_use_fma_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_fma_f32 v2, v6, -v2, -v3
+; VI-NEXT: v_mul_f32_e32 v3, -4.0, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fma, 4.0
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_y_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v0, -v0, v1, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_fneg_x_y_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v0, -v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_fneg_x_y_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_y_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v2, v0, v1, -v2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_fneg_x_y_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v2, v0, v1, -v2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_x_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_x_fneg_y_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s5
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v0, v0, -v1, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_x_fneg_y_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v0, v0, -v1, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.b = fneg float %b
+ %fma = call float @llvm.fma.f32(float %a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_x_fneg_y_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_x_fneg_y_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s5
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v2, v0, v1, -v2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_x_fneg_y_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v2, v0, v1, -v2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.b = fneg float %b
+ %fma = call nsz float @llvm.fma.f32(float %a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_fneg_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_fneg_y_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v0, v0, v1, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_fneg_fneg_y_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v0, v0, v1, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fneg.b = fneg float %b
+ %fma = call float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
}
-define amdgpu_kernel void @v_fneg_fma_x_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_fma_f32 v0, v0, -v1, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fma_fneg_fneg_y_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_fneg_y_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v2, v0, -v1, -v2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_fma_fneg_fneg_y_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v2, v0, -v1, -v2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fneg.b = fneg float %b
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_fneg_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v0, -v0, v1, -v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; SI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_fneg_x_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v0, -v0, v1, -v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fneg.c = fneg float %c
+ %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_fneg_x_fneg_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_fneg_x_fneg_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v2, v0, v1, v2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_fma_f32 v0, v0, -v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_fneg_x_fneg_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v2, v0, v1, v2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fneg.a = fneg float %a
+ %fneg.c = fneg float %c
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)
+ %fneg = fneg float %fma
+ store volatile float %fneg, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fma_x_y_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_x_y_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_x_y_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v0, v0, v1, -v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
- %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
- %fneg.b = fneg float %b
- %fma = call float @llvm.fma.f32(float %a, float %fneg.b, float %c)
+ %fneg.c = fneg float %c
+ %fma = call float @llvm.fma.f32(float %a, float %b, float %fneg.c)
%fneg = fneg float %fma
store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_fma_fneg_fneg_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_fma_f32 v0, v0, v1, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, -v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_fma_f32 v0, v0, v1, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fma_x_y_fneg_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_x_y_fneg_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v0, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v1, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_fma_f32 v2, v0, -v1, v2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_x_y_fneg_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v1, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_fma_f32 v2, v0, -v1, v2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -3578,124 +4122,75 @@ define amdgpu_kernel void @v_fneg_fma_fneg_fneg_y_f32(ptr addrspace(1) %out, ptr
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
- %fneg.a = fneg float %a
- %fneg.b = fneg float %b
- %fma = call float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)
+ %fneg.c = fneg float %c
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %fneg.c)
%fneg = fneg float %fma
store volatile float %fneg, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_fma_fneg_x_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, -v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_fma_f32 v2, v0, v1, v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_fma_f32 v0, -v0, v1, -v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
+; SI-NEXT: v_fma_f32 v2, -v6, v2, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_fma_f32 v2, v0, v1, v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
+; VI-NEXT: v_fma_f32 v2, -v6, v2, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -3706,123 +4201,73 @@ define amdgpu_kernel void @v_fneg_fma_fneg_x_fneg_f32(ptr addrspace(1) %out, ptr
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
%fneg.a = fneg float %a
- %fneg.c = fneg float %c
- %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)
+ %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fneg.a, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_fma_x_y_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_fma_f32 v0, v0, v1, -v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_fma_f32 v0, v0, v1, -v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fma_store_use_fneg_x_y_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
+; SI-NEXT: v_fma_f32 v2, v6, v2, -v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v0, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v1, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_fma_f32 v2, v0, -v1, v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_store_use_fneg_x_y_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
+; VI-NEXT: v_fma_f32 v2, v6, v2, -v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -3832,135 +4277,78 @@ define amdgpu_kernel void @v_fneg_fma_x_y_fneg_f32(ptr addrspace(1) %out, ptr ad
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
- %fneg.c = fneg float %c
- %fma = call float @llvm.fma.f32(float %a, float %b, float %fneg.c)
+ %fneg.a = fneg float %a
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %fneg.a, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
-; SI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v3
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v4
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
-; SI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v3
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v4
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
-; VI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v3
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v4
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, float %d) #0 {
+; SI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_load_dword s0, s[4:5], 0x11
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s13
+; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s15
+; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_fma_f32 v2, -v6, v2, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: v_mul_f32_e64 v3, -v6, s0
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_xor_b32_e32 v4, 0x80000000, v6
-; VI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v3
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v4
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_load_dword s0, s[4:5], 0x44
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s13
+; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s15
+; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_fma_f32 v2, -v6, v2, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: v_mul_f32_e64 v3, -v6, s0
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -3973,137 +4361,72 @@ define amdgpu_kernel void @v_fneg_fma_store_use_fneg_x_y_f32(ptr addrspace(1) %o
%fneg.a = fneg float %a
%fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
+ %use1 = fmul float %fneg.a, %d
store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %fneg.a, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
ret void
}
-define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, float %d) #0 {
-; SI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_load_dword s0, s[4:5], 0x11
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s11
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s10, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s13
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s12, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s15
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s14, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s8
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s9
-; SI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v3
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v6, s0
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_load_dword s0, s[4:5], 0x11
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s11
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s10, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s13
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s12, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s15
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s14, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s8
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s9
-; SI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v3
-; SI-NSZ-NEXT: v_mul_f32_e64 v3, -v6, s0
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_load_dword s0, s[4:5], 0x44
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s11
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s10, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s13
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s12, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s15
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s14, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s8
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s9
-; VI-SAFE-NEXT: v_fma_f32 v2, -v6, v2, v3
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v6, s0
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+; --------------------------------------------------------------------------------
+; fmad tests
+; --------------------------------------------------------------------------------
+
+define amdgpu_kernel void @v_fneg_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fmad_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v7, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mac_f32_e32 v3, v7, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_load_dword s0, s[4:5], 0x44
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s11
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s10, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s13
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s12, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s15
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s14, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s8
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s9
-; VI-NSZ-NEXT: v_fma_f32 v2, v6, v2, -v3
-; VI-NSZ-NEXT: v_mul_f32_e64 v3, -v6, s0
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v7, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mac_f32_e32 v3, v7, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -4113,129 +4436,66 @@ define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(ptr addrspace(1) %o
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
- %fneg.a = fneg float %a
- %fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
- %use1 = fmul float %fneg.a, %d
- store volatile float %fneg, ptr addrspace(1) %out
- store volatile float %use1, ptr addrspace(1) %out
+ store float %fneg, ptr addrspace(1) %out.gep
ret void
}
-; --------------------------------------------------------------------------------
-; fmad tests
-; --------------------------------------------------------------------------------
-
-define amdgpu_kernel void @v_fneg_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mac_f32_e32 v3, v7, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fmad_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mad_f32 v2, v7, -v2, -v3
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fmad_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v7, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mac_f32_e32 v3, v7, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fmad_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fmad_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v7, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mad_f32 v2, v7, -v2, -v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fmad_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v7, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mad_f32 v2, v7, -v2, -v3
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v7, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mad_f32 v2, v7, -v2, -v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -4245,140 +4505,80 @@ define amdgpu_kernel void @v_fneg_fmad_f32(ptr addrspace(1) %out, ptr addrspace(
%a = load volatile float, ptr addrspace(1) %a.gep
%b = load volatile float, ptr addrspace(1) %b.gep
%c = load volatile float, ptr addrspace(1) %c.gep
- %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
+ %fma = call nsz float @llvm.fmuladd.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
store float %fneg, ptr addrspace(1) %out.gep
ret void
}
define amdgpu_kernel void @v_fneg_fmad_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_v4f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v12, 4, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v12
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v2, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v12
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v2, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v8, vcc, s6, v12
-; SI-SAFE-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
-; SI-SAFE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v13, s1
-; SI-SAFE-NEXT: v_add_i32_e32 v12, vcc, s0, v12
-; SI-SAFE-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; SI-SAFE-NEXT: v_mad_f32 v0, v0, v4, v8
-; SI-SAFE-NEXT: v_mad_f32 v1, v1, v5, v9
-; SI-SAFE-NEXT: v_mad_f32 v2, v2, v6, v10
-; SI-SAFE-NEXT: v_mac_f32_e32 v11, v3, v7
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; SI-SAFE-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_fmad_v4f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v12, 4, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v12
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v2, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v12
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v2, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v8, vcc, s6, v12
-; SI-NSZ-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
-; SI-NSZ-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v13, s1
-; SI-NSZ-NEXT: v_add_i32_e32 v12, vcc, s0, v12
-; SI-NSZ-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; SI-NSZ-NEXT: v_mad_f32 v3, v3, -v7, -v11
-; SI-NSZ-NEXT: v_mad_f32 v2, v2, -v6, -v10
-; SI-NSZ-NEXT: v_mad_f32 v1, v1, -v5, -v9
-; SI-NSZ-NEXT: v_mad_f32 v0, v0, -v4, -v8
-; SI-NSZ-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_fmad_v4f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v12, 4, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v12
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s4, v12
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v8, vcc, s6, v12
-; VI-SAFE-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
-; VI-SAFE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v13, s1
-; VI-SAFE-NEXT: v_add_u32_e32 v12, vcc, s0, v12
-; VI-SAFE-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; VI-SAFE-NEXT: v_mad_f32 v0, v0, v4, v8
-; VI-SAFE-NEXT: v_mad_f32 v1, v1, v5, v9
-; VI-SAFE-NEXT: v_mad_f32 v2, v2, v6, v10
-; VI-SAFE-NEXT: v_mac_f32_e32 v11, v3, v7
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; VI-SAFE-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; VI-SAFE-NEXT: s_endpgm
+; SI-LABEL: v_fneg_fmad_v4f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v12, 4, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v12
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v12
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v12
+; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
+; SI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v13, s1
+; SI-NEXT: v_add_i32_e32 v12, vcc, s0, v12
+; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; SI-NEXT: v_mad_f32 v0, v0, v4, v8
+; SI-NEXT: v_mad_f32 v1, v1, v5, v9
+; SI-NEXT: v_mad_f32 v2, v2, v6, v10
+; SI-NEXT: v_mac_f32_e32 v11, v3, v7
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; SI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; SI-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fmad_v4f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v12, 4, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v12
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s4, v12
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v8, vcc, s6, v12
-; VI-NSZ-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
-; VI-NSZ-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v13, s1
-; VI-NSZ-NEXT: v_add_u32_e32 v12, vcc, s0, v12
-; VI-NSZ-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; VI-NSZ-NEXT: v_mad_f32 v3, v3, -v7, -v11
-; VI-NSZ-NEXT: v_mad_f32 v2, v2, -v6, -v10
-; VI-NSZ-NEXT: v_mad_f32 v1, v1, -v5, -v9
-; VI-NSZ-NEXT: v_mad_f32 v0, v0, -v4, -v8
-; VI-NSZ-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_v4f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v12, 4, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v12
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v12
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
+; VI-NEXT: v_mov_b32_e32 v2, s7
+; VI-NEXT: v_add_u32_e32 v8, vcc, s6, v12
+; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
+; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v13, s1
+; VI-NEXT: v_add_u32_e32 v12, vcc, s0, v12
+; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; VI-NEXT: v_mad_f32 v0, v0, v4, v8
+; VI-NEXT: v_mad_f32 v1, v1, v5, v9
+; VI-NEXT: v_mad_f32 v2, v2, v6, v10
+; VI-NEXT: v_mac_f32_e32 v11, v3, v7
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; VI-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; VI-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -4394,128 +4594,222 @@ define amdgpu_kernel void @v_fneg_fmad_v4f32(ptr addrspace(1) %out, ptr addrspac
ret void
}
-define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_mac_f32_e32 v3, v6, v2
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
-; SI-SAFE-NEXT: v_mul_f32_e32 v3, 4.0, v3
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
+define amdgpu_kernel void @v_fneg_fmad_v4f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fmad_v4f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v12, 4, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v12
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v2, s5
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v12
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
+; SI-NEXT: v_mov_b32_e32 v2, s7
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v12
+; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
+; SI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v13, s1
+; SI-NEXT: v_add_i32_e32 v12, vcc, s0, v12
+; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; SI-NEXT: v_mad_f32 v3, v3, -v7, -v11
+; SI-NEXT: v_mad_f32 v2, v2, -v6, -v10
+; SI-NEXT: v_mad_f32 v1, v1, -v5, -v9
+; SI-NEXT: v_mad_f32 v0, v0, -v4, -v8
+; SI-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; SI-NEXT: s_endpgm
;
-; SI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s4, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_mad_f32 v2, v6, -v2, -v3
-; SI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_v4f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v12, 4, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v12
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v12
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
+; VI-NEXT: v_mov_b32_e32 v2, s7
+; VI-NEXT: v_add_u32_e32 v8, vcc, s6, v12
+; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
+; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dwordx4 v[8:11], v[8:9] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v13, s1
+; VI-NEXT: v_add_u32_e32 v12, vcc, s0, v12
+; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; VI-NEXT: v_mad_f32 v3, v3, -v7, -v11
+; VI-NEXT: v_mad_f32 v2, v2, -v6, -v10
+; VI-NEXT: v_mad_f32 v1, v1, -v5, -v9
+; VI-NEXT: v_mad_f32 v0, v0, -v4, -v8
+; VI-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile <4 x float>, ptr addrspace(1) %a.gep
+ %b = load volatile <4 x float>, ptr addrspace(1) %b.gep
+ %c = load volatile <4 x float>, ptr addrspace(1) %c.gep
+ %fma = call nsz <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
+ %fneg = fneg <4 x float> %fma
+ store <4 x float> %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fmad_multi_use_fmad_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_mac_f32_e32 v3, v6, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 4.0, v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s5
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s7
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s0
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_mac_f32_e32 v3, v6, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
-; VI-SAFE-NEXT: v_mul_f32_e32 v3, 4.0, v3
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_multi_use_fmad_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mac_f32_e32 v3, v6, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; VI-NEXT: v_mul_f32_e32 v3, 4.0, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fma, 4.0
+ store volatile float %fneg, ptr addrspace(1) %out
+ store volatile float %use1, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr) #0 {
+; SI-LABEL: v_fneg_fmad_multi_use_fmad_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s7
+; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: flat_load_dword v6, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_mac_f32_e32 v3, v6, v2
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; SI-NEXT: v_mul_f32_e32 v3, 4.0, v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v4, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s5
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s4, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s7
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s6, v4
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: flat_load_dword v6, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s0
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_mad_f32 v2, v6, -v2, -v3
-; VI-NSZ-NEXT: v_mul_f32_e32 v3, -4.0, v2
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_fmad_multi_use_fmad_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v4
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dword v6, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mac_f32_e32 v3, v6, v2
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v3
+; VI-NEXT: v_mul_f32_e32 v3, 4.0, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -6283,99 +6577,53 @@ define amdgpu_kernel void @v_fneg_trunc_f32(ptr addrspace(1) %out, ptr addrspace
; --------------------------------------------------------------------------------
define amdgpu_kernel void @v_fneg_round_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
-; SI-SAFE-LABEL: v_fneg_round_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: flat_load_dword v3, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_trunc_f32_e32 v2, v3
-; SI-SAFE-NEXT: v_sub_f32_e32 v4, v3, v2
-; SI-SAFE-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
-; SI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
-; SI-SAFE-NEXT: s_brev_b32 s0, -2
-; SI-SAFE-NEXT: v_bfi_b32 v3, s0, v4, v3
-; SI-SAFE-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: v_fneg_round_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s2, v2
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: flat_load_dword v3, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_trunc_f32_e32 v2, v3
-; SI-NSZ-NEXT: v_sub_f32_e32 v4, v3, v2
-; SI-NSZ-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
-; SI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
-; SI-NSZ-NEXT: s_brev_b32 s0, -2
-; SI-NSZ-NEXT: v_bfi_b32 v3, s0, v4, v3
-; SI-NSZ-NEXT: v_sub_f32_e64 v2, -v2, v3
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: v_fneg_round_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s3
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: flat_load_dword v3, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s1
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_trunc_f32_e32 v2, v3
-; VI-SAFE-NEXT: v_sub_f32_e32 v4, v3, v2
-; VI-SAFE-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
-; VI-SAFE-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
-; VI-SAFE-NEXT: s_brev_b32 s0, -2
-; VI-SAFE-NEXT: v_bfi_b32 v3, s0, v4, v3
-; VI-SAFE-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_endpgm
+; SI-LABEL: v_fneg_round_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_trunc_f32_e32 v2, v3
+; SI-NEXT: v_sub_f32_e32 v4, v3, v2
+; SI-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
+; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_bfi_b32 v3, s0, v4, v3
+; SI-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: v_fneg_round_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s3
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: flat_load_dword v3, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s1
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_trunc_f32_e32 v2, v3
-; VI-NSZ-NEXT: v_sub_f32_e32 v4, v3, v2
-; VI-NSZ-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
-; VI-NSZ-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
-; VI-NSZ-NEXT: s_brev_b32 s0, -2
-; VI-NSZ-NEXT: v_bfi_b32 v3, s0, v4, v3
-; VI-NSZ-NEXT: v_sub_f32_e64 v2, -v2, v3
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: v_fneg_round_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_trunc_f32_e32 v2, v3
+; VI-NEXT: v_sub_f32_e32 v4, v3, v2
+; VI-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
+; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
+; VI-NEXT: s_brev_b32 s0, -2
+; VI-NEXT: v_bfi_b32 v3, s0, v4, v3
+; VI-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -6387,6 +6635,63 @@ define amdgpu_kernel void @v_fneg_round_f32(ptr addrspace(1) %out, ptr addrspace
ret void
}
+define amdgpu_kernel void @v_fneg_round_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #0 {
+; SI-LABEL: v_fneg_round_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s3
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: flat_load_dword v3, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v2
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_trunc_f32_e32 v2, v3
+; SI-NEXT: v_sub_f32_e32 v4, v3, v2
+; SI-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
+; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_bfi_b32 v3, s0, v4, v3
+; SI-NEXT: v_sub_f32_e64 v2, -v2, v3
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_fneg_round_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v3, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_trunc_f32_e32 v2, v3
+; VI-NEXT: v_sub_f32_e32 v4, v3, v2
+; VI-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
+; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
+; VI-NEXT: s_brev_b32 s0, -2
+; VI-NEXT: v_bfi_b32 v3, s0, v4, v3
+; VI-NEXT: v_sub_f32_e64 v2, -v2, v3
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %round = call nsz float @llvm.round.f32(float %a)
+ %fneg = fneg float %round
+ store float %fneg, ptr addrspace(1) %out.gep
+ ret void
+}
+
; --------------------------------------------------------------------------------
; rint tests
; --------------------------------------------------------------------------------
@@ -6721,12 +7026,12 @@ define amdgpu_kernel void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, ptr addrs
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: v_mul_f32_e32 v3, v7, v3
-; SI-NEXT: s_cbranch_scc0 .LBB105_2
+; SI-NEXT: s_cbranch_scc0 .LBB125_2
; SI-NEXT: ; %bb.1: ; %endif
; SI-NEXT: flat_store_dword v[0:1], v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
-; SI-NEXT: .LBB105_2: ; %if
+; SI-NEXT: .LBB125_2: ; %if
; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v3
; SI-NEXT: v_mul_f32_e32 v2, v4, v2
; SI-NEXT: flat_store_dword v[0:1], v2
@@ -6761,12 +7066,12 @@ define amdgpu_kernel void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, ptr addrs
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_cmp_lg_u32 s0, 0
; VI-NEXT: v_mul_f32_e32 v3, v7, v3
-; VI-NEXT: s_cbranch_scc0 .LBB105_2
+; VI-NEXT: s_cbranch_scc0 .LBB125_2
; VI-NEXT: ; %bb.1: ; %endif
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
-; VI-NEXT: .LBB105_2: ; %if
+; VI-NEXT: .LBB125_2: ; %if
; VI-NEXT: v_xor_b32_e32 v4, 0x80000000, v3
; VI-NEXT: v_mul_f32_e32 v2, v4, v2
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -7215,153 +7520,79 @@ define amdgpu_kernel void @multiuse_fneg_vop2_vop3_users_f32(ptr addrspace(1) %o
; The use of the fneg requires a code size increase, but folding into
; the source does not
define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {
-; SI-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
-; SI-SAFE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x11
-; SI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s11
-; SI-SAFE-NEXT: v_add_i32_e32 v0, vcc, s10, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s13
-; SI-SAFE-NEXT: v_add_i32_e32 v2, vcc, s12, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, s15
-; SI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s14, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-SAFE-NEXT: v_mov_b32_e32 v7, s1
-; SI-SAFE-NEXT: v_add_i32_e32 v6, vcc, s0, v6
-; SI-SAFE-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; SI-SAFE-NEXT: flat_load_dword v8, v[0:1] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_load_dword v4, v[6:7] glc
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, s8
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, s9
-; SI-SAFE-NEXT: v_fma_f32 v2, v8, v2, 2.0
-; SI-SAFE-NEXT: v_mul_f32_e64 v3, -v2, v3
-; SI-SAFE-NEXT: v_mul_f32_e64 v2, -v2, v4
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; SI-SAFE-NEXT: s_endpgm
-;
-; SI-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
-; SI-NSZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x11
-; SI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; SI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s11
-; SI-NSZ-NEXT: v_add_i32_e32 v0, vcc, s10, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s13
-; SI-NSZ-NEXT: v_add_i32_e32 v2, vcc, s12, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, s15
-; SI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s14, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; SI-NSZ-NEXT: v_mov_b32_e32 v7, s1
-; SI-NSZ-NEXT: v_add_i32_e32 v6, vcc, s0, v6
-; SI-NSZ-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; SI-NSZ-NEXT: flat_load_dword v8, v[0:1] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_load_dword v4, v[6:7] glc
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v0, s8
-; SI-NSZ-NEXT: v_mov_b32_e32 v1, s9
-; SI-NSZ-NEXT: v_fma_f32 v2, v8, -v2, -2.0
-; SI-NSZ-NEXT: v_mul_f32_e32 v3, v2, v3
-; SI-NSZ-NEXT: v_mul_f32_e32 v2, v2, v4
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; SI-NSZ-NEXT: s_endpgm
-;
-; VI-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; VI-SAFE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
-; VI-SAFE-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s11
-; VI-SAFE-NEXT: v_add_u32_e32 v0, vcc, s10, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v3, s13
-; VI-SAFE-NEXT: v_add_u32_e32 v2, vcc, s12, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v5, s15
-; VI-SAFE-NEXT: v_add_u32_e32 v4, vcc, s14, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-SAFE-NEXT: v_mov_b32_e32 v7, s1
-; VI-SAFE-NEXT: v_add_u32_e32 v6, vcc, s0, v6
-; VI-SAFE-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; VI-SAFE-NEXT: flat_load_dword v8, v[0:1] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_load_dword v4, v[6:7] glc
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, s8
-; VI-SAFE-NEXT: v_mov_b32_e32 v1, s9
-; VI-SAFE-NEXT: v_fma_f32 v2, v8, v2, 2.0
-; VI-SAFE-NEXT: v_mul_f32_e64 v3, -v2, v3
-; VI-SAFE-NEXT: v_mul_f32_e64 v2, -v2, v4
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v3
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: flat_store_dword v[0:1], v2
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0)
-; VI-SAFE-NEXT: s_endpgm
+; SI-LABEL: free_fold_src_code_size_cost_use_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x11
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s13
+; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s15
+; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v7, s1
+; SI-NEXT: v_add_i32_e32 v6, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; SI-NEXT: flat_load_dword v8, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v4, v[6:7] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_fma_f32 v2, v8, v2, 2.0
+; SI-NEXT: v_mul_f32_e64 v3, -v2, v3
+; SI-NEXT: v_mul_f32_e64 v2, -v2, v4
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
;
-; VI-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; VI-NSZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
-; VI-NSZ-NEXT: v_lshlrev_b32_e32 v6, 2, v0
-; VI-NSZ-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s11
-; VI-NSZ-NEXT: v_add_u32_e32 v0, vcc, s10, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s13
-; VI-NSZ-NEXT: v_add_u32_e32 v2, vcc, s12, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v5, s15
-; VI-NSZ-NEXT: v_add_u32_e32 v4, vcc, s14, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NSZ-NEXT: v_mov_b32_e32 v7, s1
-; VI-NSZ-NEXT: v_add_u32_e32 v6, vcc, s0, v6
-; VI-NSZ-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; VI-NSZ-NEXT: flat_load_dword v8, v[0:1] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v2, v[2:3] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v3, v[4:5] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_load_dword v4, v[6:7] glc
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, s8
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, s9
-; VI-NSZ-NEXT: v_fma_f32 v2, v8, -v2, -2.0
-; VI-NSZ-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NSZ-NEXT: v_mul_f32_e32 v2, v2, v4
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v3
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: flat_store_dword v[0:1], v2
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0)
-; VI-NSZ-NEXT: s_endpgm
+; VI-LABEL: free_fold_src_code_size_cost_use_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s13
+; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s15
+; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: v_mov_b32_e32 v7, s1
+; VI-NEXT: v_add_u32_e32 v6, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; VI-NEXT: flat_load_dword v8, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v4, v[6:7] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_fma_f32 v2, v8, v2, 2.0
+; VI-NEXT: v_mul_f32_e64 v3, -v2, v3
+; VI-NEXT: v_mul_f32_e64 v2, -v2, v4
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
@@ -7384,6 +7615,102 @@ define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32(ptr addrspace(1)
ret void
}
+define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32_nsz(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {
+; SI-LABEL: free_fold_src_code_size_cost_use_f32_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x11
+; SI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_add_i32_e32 v0, vcc, s10, v6
+; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v3, s13
+; SI-NEXT: v_add_i32_e32 v2, vcc, s12, v6
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s15
+; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v6
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v7, s1
+; SI-NEXT: v_add_i32_e32 v6, vcc, s0, v6
+; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; SI-NEXT: flat_load_dword v8, v[0:1] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v2, v[2:3] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v3, v[4:5] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_load_dword v4, v[6:7] glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s8
+; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_fma_f32 v2, v8, -v2, -2.0
+; SI-NEXT: v_mul_f32_e32 v3, v2, v3
+; SI-NEXT: v_mul_f32_e32 v2, v2, v4
+; SI-NEXT: flat_store_dword v[0:1], v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: flat_store_dword v[0:1], v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: free_fold_src_code_size_cost_use_f32_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
+; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: v_add_u32_e32 v0, vcc, s10, v6
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: v_mov_b32_e32 v3, s13
+; VI-NEXT: v_add_u32_e32 v2, vcc, s12, v6
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, s15
+; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v6
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: v_mov_b32_e32 v7, s1
+; VI-NEXT: v_add_u32_e32 v6, vcc, s0, v6
+; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; VI-NEXT: flat_load_dword v8, v[0:1] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v2, v[2:3] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v3, v[4:5] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_load_dword v4, v[6:7] glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_fma_f32 v2, v8, -v2, -2.0
+; VI-NEXT: v_mul_f32_e32 v3, v2, v3
+; VI-NEXT: v_mul_f32_e32 v2, v2, v4
+; VI-NEXT: flat_store_dword v[0:1], v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext
+ %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext
+ %c.gep = getelementptr inbounds float, ptr addrspace(1) %c.ptr, i64 %tid.ext
+ %d.gep = getelementptr inbounds float, ptr addrspace(1) %d.ptr, i64 %tid.ext
+ %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext
+ %a = load volatile float, ptr addrspace(1) %a.gep
+ %b = load volatile float, ptr addrspace(1) %b.gep
+ %c = load volatile float, ptr addrspace(1) %c.gep
+ %d = load volatile float, ptr addrspace(1) %d.gep
+
+ %fma0 = call nsz float @llvm.fma.f32(float %a, float %b, float 2.0)
+ %fneg.fma0 = fneg float %fma0
+ %mul1 = fmul float %fneg.fma0, %c
+ %mul2 = fmul float %fneg.fma0, %d
+
+ store volatile float %mul1, ptr addrspace(1) %out
+ store volatile float %mul2, ptr addrspace(1) %out
+ ret void
+}
+
define amdgpu_kernel void @free_fold_src_code_size_cost_use_f64(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, ptr addrspace(1) %c.ptr, ptr addrspace(1) %d.ptr) #0 {
; SI-LABEL: free_fold_src_code_size_cost_use_f64:
; SI: ; %bb.0:
@@ -7999,7 +8326,3 @@ declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
-attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GCN-NSZ: {{.*}}
-; GCN-SAFE: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index ca2aa47fbcf5b..38b7ae8cf824f 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -1,32 +1,36 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,SI,SI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global -fp-contract=fast < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,SI,SI-NSZ %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI %s
+
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,VI,VI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji -fp-contract=fast < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,VI,VI-NSZ %s
; --------------------------------------------------------------------------------
; fadd tests
; --------------------------------------------------------------------------------
define float @v_fneg_add_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v0, v1
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f32_e32 v0, v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%add = fadd float %a, %b
%fneg = fneg float %add
ret float %fneg
}
+define float @v_fneg_add_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e64 v0, -v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd nsz float %a, %b
+ %fneg = fneg float %add
+ ret float %fneg
+}
+
define { float, float } @v_fneg_add_store_use_add_f32(float %a, float %b) #0 {
; GCN-LABEL: v_fneg_add_store_use_add_f32:
; GCN: ; %bb.0:
@@ -42,20 +46,13 @@ define { float, float } @v_fneg_add_store_use_add_f32(float %a, float %b) #0 {
}
define { float, float } @v_fneg_add_multi_use_add_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_multi_use_add_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f32_e32 v1, v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
-; GCN-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_multi_use_add_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v0, v1
-; GCN-NSZ-NEXT: v_mul_f32_e32 v1, -4.0, v0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_multi_use_add_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f32_e32 v1, v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 4.0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%add = fadd float %a, %b
%fneg = fneg float %add
%use1 = fmul float %add, 4.0
@@ -65,57 +62,79 @@ define { float, float } @v_fneg_add_multi_use_add_f32(float %a, float %b) #0 {
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_add_multi_use_add_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_multi_use_add_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e64 v0, -v0, v1
+; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd contract nsz float %a, %b
+ %fneg = fneg float %add
+ %use1 = fmul contract float %add, 4.0
+
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1
+ ret { float, float } %insert.1
+}
+
define float @v_fneg_add_fneg_x_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_fneg_x_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_fneg_x_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_fneg_x_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%add = fadd float %fneg.a, %b
%fneg = fneg float %add
ret float %fneg
}
+define float @v_fneg_add_fneg_x_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_fneg_x_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v0, v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
+ ret float %fneg
+}
+
define float @v_fneg_add_x_fneg_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_x_fneg_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_sub_f32_e32 v0, v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_x_fneg_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_sub_f32_e32 v0, v1, v0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_x_fneg_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v0, v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg float %b
%add = fadd float %a, %fneg.b
%fneg = fneg float %add
ret float %fneg
}
+define float @v_fneg_add_x_fneg_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_x_fneg_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.b = fneg float %b
+ %add = fadd nsz float %a, %fneg.b
+ %fneg = fneg float %add
+ ret float %fneg
+}
+
define float @v_fneg_add_fneg_fneg_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_fneg_fneg_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_sub_f32_e64 v0, -v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_fneg_fneg_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f32_e32 v0, v0, v1
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_fneg_fneg_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e64 v0, -v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fneg.b = fneg float %b
%add = fadd float %fneg.a, %fneg.b
@@ -123,23 +142,28 @@ define float @v_fneg_add_fneg_fneg_f32(float %a, float %b) #0 {
ret float %fneg
}
+define float @v_fneg_add_fneg_fneg_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_fneg_fneg_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f32_e32 v0, v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fneg.b = fneg float %b
+ %add = fadd nsz float %fneg.a, %fneg.b
+ %fneg = fneg float %add
+ ret float %fneg
+}
+
define { float, float } @v_fneg_add_store_use_fneg_x_f32(float %a, float %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; GCN-SAFE-NEXT: v_sub_f32_e32 v0, v1, v0
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: v_mov_b32_e32 v1, v2
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
-; GCN-NSZ-NEXT: v_sub_f32_e32 v0, v0, v1
-; GCN-NSZ-NEXT: v_mov_b32_e32 v1, v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_store_use_fneg_x_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; GCN-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%add = fadd float %fneg.a, %b
%fneg = fneg float %add
@@ -148,23 +172,31 @@ define { float, float } @v_fneg_add_store_use_fneg_x_f32(float %a, float %b) #0
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_add_store_use_fneg_x_f32_nsz(float %a, float %b) #0 {
+; GCN-LABEL: v_fneg_add_store_use_fneg_x_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
+; GCN-NEXT: v_sub_f32_e32 v0, v0, v1
+; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 1
+ ret { float, float } %insert.1
+}
+
define { float, float } @v_fneg_add_multi_use_fneg_x_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_sub_f32_e32 v1, v1, v0
-; GCN-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
-; GCN-SAFE-NEXT: v_mul_f32_e64 v1, -v0, v2
-; GCN-SAFE-NEXT: v_mov_b32_e32 v0, v3
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_sub_f32_e32 v3, v0, v1
-; GCN-NSZ-NEXT: v_mul_f32_e64 v1, -v0, v2
-; GCN-NSZ-NEXT: v_mov_b32_e32 v0, v3
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_multi_use_fneg_x_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v1, v1, v0
+; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
+; GCN-NEXT: v_mul_f32_e64 v1, -v0, v2
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%add = fadd float %fneg.a, %b
%fneg = fneg float %add
@@ -175,6 +207,24 @@ define { float, float } @v_fneg_add_multi_use_fneg_x_f32(float %a, float %b, flo
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_add_multi_use_fneg_x_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_add_multi_use_fneg_x_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_sub_f32_e32 v3, v0, v1
+; GCN-NEXT: v_mul_f32_e64 v1, -v0, v2
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %add = fadd nsz float %fneg.a, %b
+ %fneg = fneg float %add
+ %use1 = fmul float %fneg.a, %c
+
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1
+ ret { float, float } %insert.1
+}
+
define amdgpu_ps float @fneg_fadd_0_safe_f32(float inreg %tmp2, float inreg %tmp6, <4 x i32> %arg) #0 {
; SI-LABEL: fneg_fadd_0_safe_f32:
; SI: ; %bb.0: ; %.entry
@@ -265,23 +315,28 @@ define amdgpu_ps float @fneg_fadd_0_nsz_f32(float inreg %tmp2, float inreg %tmp6
}
define double @v_fneg_add_f64(double %a, double %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_f64:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GCN-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%add = fadd double %a, %b
%fneg = fneg double %add
ret double %fneg
}
+define double @v_fneg_add_f64_nsz(double %a, double %b) #0 {
+; GCN-LABEL: v_fneg_add_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd nsz double %a, %b
+ %fneg = fneg double %add
+ ret double %fneg
+}
+
define { double, double } @v_fneg_add_store_use_add_f64(double %a, double %b) #0 {
; GCN-LABEL: v_fneg_add_store_use_add_f64:
; GCN: ; %bb.0:
@@ -298,29 +353,22 @@ define { double, double } @v_fneg_add_store_use_add_f64(double %a, double %b) #0
}
define { double, double } @v_fneg_add_multi_use_add_f64(double %a, double %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_add_f64:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; SI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
-; SI-SAFE-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, v4
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_multi_use_add_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
-; GCN-NSZ-NEXT: v_mul_f64 v[2:3], v[0:1], -4.0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_multi_use_add_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
+; SI-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
+; SI-NEXT: v_mov_b32_e32 v1, v4
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_add_f64:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; VI-SAFE-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_multi_use_add_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; VI-NEXT: v_mul_f64 v[2:3], v[0:1], 4.0
+; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
%add = fadd double %a, %b
%fneg = fneg double %add
%use1 = fmul double %add, 4.0
@@ -330,57 +378,79 @@ define { double, double } @v_fneg_add_multi_use_add_f64(double %a, double %b) #0
ret { double, double } %insert.1
}
+define { double, double } @v_fneg_add_multi_use_add_f64_nsz(double %a, double %b) #0 {
+; GCN-LABEL: v_fneg_add_multi_use_add_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
+; GCN-NEXT: v_mul_f64 v[2:3], v[0:1], -4.0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %add = fadd nsz double %a, %b
+ %fneg = fneg double %add
+ %use1 = fmul double %add, 4.0
+
+ %insert.0 = insertvalue { double, double } poison, double %fneg, 0
+ %insert.1 = insertvalue { double, double } %insert.0, double %use1, 1
+ ret { double, double } %insert.1
+}
+
define double @v_fneg_add_fneg_x_f64(double %a, double %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_fneg_x_f64:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f64 v[0:1], v[2:3], -v[0:1]
-; GCN-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_fneg_x_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_fneg_x_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[2:3], -v[0:1]
+; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg double %a
%add = fadd double %fneg.a, %b
%fneg = fneg double %add
ret double %fneg
}
+define double @v_fneg_add_fneg_x_f64_nsz(double %a, double %b) #0 {
+; GCN-LABEL: v_fneg_add_fneg_x_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg double %a
+ %add = fadd nsz double %fneg.a, %b
+ %fneg = fneg double %add
+ ret double %fneg
+}
+
define double @v_fneg_add_x_fneg_f64(double %a, double %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_x_fneg_f64:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
-; GCN-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_x_fneg_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[0:1], v[2:3], -v[0:1]
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_x_fneg_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
+; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg double %b
%add = fadd double %a, %fneg.b
%fneg = fneg double %add
ret double %fneg
}
+define double @v_fneg_add_x_fneg_f64_nsz(double %a, double %b) #0 {
+; GCN-LABEL: v_fneg_add_x_fneg_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[2:3], -v[0:1]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.b = fneg double %b
+ %add = fadd nsz double %a, %fneg.b
+ %fneg = fneg double %add
+ ret double %fneg
+}
+
define double @v_fneg_add_fneg_fneg_f64(double %a, double %b) #0 {
-; GCN-SAFE-LABEL: v_fneg_add_fneg_fneg_f64:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
-; GCN-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_add_fneg_fneg_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_add_fneg_fneg_f64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
+; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg double %a
%fneg.b = fneg double %b
%add = fadd double %fneg.a, %fneg.b
@@ -388,47 +458,40 @@ define double @v_fneg_add_fneg_fneg_f64(double %a, double %b) #0 {
ret double %fneg
}
+define double @v_fneg_add_fneg_fneg_f64_nsz(double %a, double %b) #0 {
+; GCN-LABEL: v_fneg_add_fneg_fneg_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg double %a
+ %fneg.b = fneg double %b
+ %add = fadd nsz double %fneg.a, %fneg.b
+ %fneg = fneg double %add
+ ret double %fneg
+}
+
define { double, double } @v_fneg_add_store_use_fneg_x_f64(double %a, double %b) #0 {
-; SI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f64:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_mov_b32_e32 v5, v1
-; SI-SAFE-NEXT: v_mov_b32_e32 v4, v0
-; SI-SAFE-NEXT: v_add_f64 v[0:1], v[2:3], -v[4:5]
-; SI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v5
-; SI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
-; SI-SAFE-NEXT: v_mov_b32_e32 v2, v4
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f64:
-; SI-NSZ: ; %bb.0:
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: v_mov_b32_e32 v5, v1
-; SI-NSZ-NEXT: v_mov_b32_e32 v4, v0
-; SI-NSZ-NEXT: v_add_f64 v[0:1], v[4:5], -v[2:3]
-; SI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v5
-; SI-NSZ-NEXT: v_mov_b32_e32 v2, v4
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: v_fneg_add_store_use_fneg_x_f64:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f64 v[4:5], v[2:3], -v[0:1]
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, v0
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v5
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, v4
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v5, v1
+; SI-NEXT: v_mov_b32_e32 v4, v0
+; SI-NEXT: v_add_f64 v[0:1], v[2:3], -v[4:5]
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v5
+; SI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
+; SI-NEXT: v_mov_b32_e32 v2, v4
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-NSZ-LABEL: v_fneg_add_store_use_fneg_x_f64:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; VI-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, v0
-; VI-NSZ-NEXT: v_mov_b32_e32 v0, v4
-; VI-NSZ-NEXT: v_mov_b32_e32 v1, v5
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f64 v[4:5], v[2:3], -v[0:1]
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
+; VI-NEXT: v_mov_b32_e32 v2, v0
+; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v5
+; VI-NEXT: v_mov_b32_e32 v0, v4
+; VI-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg double %a
%add = fadd double %fneg.a, %b
%fneg = fneg double %add
@@ -437,34 +500,53 @@ define { double, double } @v_fneg_add_store_use_fneg_x_f64(double %a, double %b)
ret { double, double } %insert.1
}
-define { double, double } @v_fneg_add_multi_use_fneg_x_f64(double %a, double %b, double %c) #0 {
-; SI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f64:
-; SI-SAFE: ; %bb.0:
-; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT: v_add_f64 v[6:7], v[2:3], -v[0:1]
-; SI-SAFE-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
-; SI-SAFE-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
-; SI-SAFE-NEXT: v_mov_b32_e32 v0, v6
-; SI-SAFE-NEXT: v_mov_b32_e32 v1, v7
-; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
+define { double, double } @v_fneg_add_store_use_fneg_x_f64_nsz(double %a, double %b) #0 {
+; SI-LABEL: v_fneg_add_store_use_fneg_x_f64_nsz:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v5, v1
+; SI-NEXT: v_mov_b32_e32 v4, v0
+; SI-NEXT: v_add_f64 v[0:1], v[4:5], -v[2:3]
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v5
+; SI-NEXT: v_mov_b32_e32 v2, v4
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; GCN-NSZ-LABEL: v_fneg_add_multi_use_fneg_x_f64:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_add_f64 v[6:7], v[0:1], -v[2:3]
-; GCN-NSZ-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
-; GCN-NSZ-NEXT: v_mov_b32_e32 v0, v6
-; GCN-NSZ-NEXT: v_mov_b32_e32 v1, v7
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_store_use_fneg_x_f64_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
+; VI-NEXT: v_mov_b32_e32 v2, v0
+; VI-NEXT: v_mov_b32_e32 v0, v4
+; VI-NEXT: v_mov_b32_e32 v1, v5
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg double %a
+ %add = fadd nsz double %fneg.a, %b
+ %fneg = fneg double %add
+ %insert.0 = insertvalue { double, double } poison, double %fneg, 0
+ %insert.1 = insertvalue { double, double } %insert.0, double %fneg.a, 1
+ ret { double, double } %insert.1
+}
+
+define { double, double } @v_fneg_add_multi_use_fneg_x_f64(double %a, double %b, double %c) #0 {
+; SI-LABEL: v_fneg_add_multi_use_fneg_x_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_add_f64 v[6:7], v[2:3], -v[0:1]
+; SI-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
+; SI-NEXT: v_xor_b32_e32 v7, 0x80000000, v7
+; SI-NEXT: v_mov_b32_e32 v0, v6
+; SI-NEXT: v_mov_b32_e32 v1, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SAFE-LABEL: v_fneg_add_multi_use_fneg_x_f64:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f64 v[6:7], v[2:3], -v[0:1]
-; VI-SAFE-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v7
-; VI-SAFE-NEXT: v_mov_b32_e32 v0, v6
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: v_fneg_add_multi_use_fneg_x_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f64 v[6:7], v[2:3], -v[0:1]
+; VI-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
+; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v7
+; VI-NEXT: v_mov_b32_e32 v0, v6
+; VI-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg double %a
%add = fadd double %fneg.a, %b
%fneg = fneg double %add
@@ -475,117 +557,80 @@ define { double, double } @v_fneg_add_multi_use_fneg_x_f64(double %a, double %b,
ret { double, double } %insert.1
}
+define { double, double } @v_fneg_add_multi_use_fneg_x_f64_nsz(double %a, double %b, double %c) #0 {
+; GCN-LABEL: v_fneg_add_multi_use_fneg_x_f64_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f64 v[6:7], v[0:1], -v[2:3]
+; GCN-NEXT: v_mul_f64 v[2:3], -v[0:1], v[4:5]
+; GCN-NEXT: v_mov_b32_e32 v0, v6
+; GCN-NEXT: v_mov_b32_e32 v1, v7
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg double %a
+ %add = fadd nsz double %fneg.a, %b
+ %fneg = fneg double %add
+ %use1 = fmul double %fneg.a, %c
+
+ %insert.0 = insertvalue { double, double } poison, double %fneg, 0
+ %insert.1 = insertvalue { double, double } %insert.0, double %use1, 1
+ ret { double, double } %insert.1
+}
+
; This one asserted with -enable-no-signed-zeros-fp-math
define amdgpu_ps double @fneg_fadd_0_f64(double inreg %tmp2, double inreg %tmp6, <4 x i32> %arg) #0 {
-; SI-SAFE-LABEL: fneg_fadd_0_f64:
-; SI-SAFE: ; %bb.0: ; %.entry
-; SI-SAFE-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; SI-SAFE-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-SAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SAFE-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; SI-SAFE-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; SI-SAFE-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; SI-SAFE-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; SI-SAFE-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; SI-SAFE-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; SI-SAFE-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; SI-SAFE-NEXT: v_mov_b32_e32 v2, s1
-; SI-SAFE-NEXT: v_mov_b32_e32 v3, s0
-; SI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; SI-SAFE-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; SI-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; SI-SAFE-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
-; SI-SAFE-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; SI-SAFE-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; SI-SAFE-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-SAFE-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; SI-SAFE-NEXT: s_mov_b32 s0, 0
-; SI-SAFE-NEXT: ; return to shader part epilog
-;
-; SI-NSZ-LABEL: fneg_fadd_0_f64:
-; SI-NSZ: ; %bb.0: ; %.entry
-; SI-NSZ-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; SI-NSZ-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-NSZ-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-NSZ-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; SI-NSZ-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; SI-NSZ-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; SI-NSZ-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; SI-NSZ-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; SI-NSZ-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; SI-NSZ-NEXT: v_mov_b32_e32 v2, s1
-; SI-NSZ-NEXT: v_mov_b32_e32 v3, s0
-; SI-NSZ-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; SI-NSZ-NEXT: s_mov_b32 s2, 0
-; SI-NSZ-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; SI-NSZ-NEXT: s_brev_b32 s3, 1
-; SI-NSZ-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
-; SI-NSZ-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; SI-NSZ-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; SI-NSZ-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NSZ-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; SI-NSZ-NEXT: s_mov_b32 s0, 0
-; SI-NSZ-NEXT: ; return to shader part epilog
-;
-; VI-SAFE-LABEL: fneg_fadd_0_f64:
-; VI-SAFE: ; %bb.0: ; %.entry
-; VI-SAFE-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; VI-SAFE-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-SAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SAFE-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; VI-SAFE-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; VI-SAFE-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; VI-SAFE-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; VI-SAFE-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; VI-SAFE-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; VI-SAFE-NEXT: v_mov_b32_e32 v4, s0
-; VI-SAFE-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, s1
-; VI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; VI-SAFE-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; VI-SAFE-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; VI-SAFE-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
-; VI-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; VI-SAFE-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-SAFE-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SAFE-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-SAFE-NEXT: s_mov_b32 s0, 0
-; VI-SAFE-NEXT: ; return to shader part epilog
+; SI-LABEL: fneg_fadd_0_f64:
+; SI: ; %bb.0: ; %.entry
+; SI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; SI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; SI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; SI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; SI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
+; SI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; SI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; SI-NEXT: v_mov_b32_e32 v2, s1
+; SI-NEXT: v_mov_b32_e32 v3, s0
+; SI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
+; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
+; SI-NEXT: v_add_f64 v[0:1], v[0:1], 0
+; SI-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
+; SI-NEXT: v_xor_b32_e32 v4, 0x80000000, v1
+; SI-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; SI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
+; SI-NEXT: s_mov_b32 s0, 0
+; SI-NEXT: ; return to shader part epilog
;
-; VI-NSZ-LABEL: fneg_fadd_0_f64:
-; VI-NSZ: ; %bb.0: ; %.entry
-; VI-NSZ-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; VI-NSZ-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-NSZ-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-NSZ-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; VI-NSZ-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; VI-NSZ-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; VI-NSZ-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; VI-NSZ-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
-; VI-NSZ-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; VI-NSZ-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, s1
-; VI-NSZ-NEXT: v_mov_b32_e32 v3, s0
-; VI-NSZ-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; VI-NSZ-NEXT: s_mov_b32 s2, 0
-; VI-NSZ-NEXT: s_brev_b32 s3, 1
-; VI-NSZ-NEXT: v_mul_f64 v[0:1], v[0:1], 0
-; VI-NSZ-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
-; VI-NSZ-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; VI-NSZ-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NSZ-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NSZ-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NSZ-NEXT: s_mov_b32 s0, 0
-; VI-NSZ-NEXT: ; return to shader part epilog
+; VI-LABEL: fneg_fadd_0_f64:
+; VI: ; %bb.0: ; %.entry
+; VI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; VI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; VI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; VI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; VI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
+; VI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; VI-NEXT: v_mov_b32_e32 v2, s1
+; VI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
+; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
+; VI-NEXT: v_add_f64 v[0:1], v[0:1], 0
+; VI-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
+; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: ; return to shader part epilog
.entry:
%tmp7 = fdiv double 1.000000e+00, %tmp6
%tmp8 = fmul double 0.000000e+00, %tmp7
@@ -599,6 +644,75 @@ define amdgpu_ps double @fneg_fadd_0_f64(double inreg %tmp2, double inreg %tmp6,
ret double %.i198
}
+define amdgpu_ps double @fneg_fadd_0_f64_nsz(double inreg %tmp2, double inreg %tmp6, <4 x i32> %arg) #0 {
+; SI-LABEL: fneg_fadd_0_f64_nsz:
+; SI: ; %bb.0: ; %.entry
+; SI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; SI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; SI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; SI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; SI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
+; SI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; SI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; SI-NEXT: v_mov_b32_e32 v2, s1
+; SI-NEXT: v_mov_b32_e32 v3, s0
+; SI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
+; SI-NEXT: s_brev_b32 s3, 1
+; SI-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
+; SI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; SI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
+; SI-NEXT: s_mov_b32 s0, 0
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: fneg_fadd_0_f64_nsz:
+; VI: ; %bb.0: ; %.entry
+; VI-NEXT: v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
+; VI-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; VI-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; VI-NEXT: v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; VI-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; VI-NEXT: v_mul_f64 v[6:7], v[4:5], v[2:3]
+; VI-NEXT: v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; VI-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; VI-NEXT: v_mov_b32_e32 v2, s1
+; VI-NEXT: v_mov_b32_e32 v3, s0
+; VI-NEXT: v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
+; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: s_brev_b32 s3, 1
+; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0
+; VI-NEXT: v_fma_f64 v[0:1], v[0:1], s[2:3], s[2:3]
+; VI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
+; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: ; return to shader part epilog
+.entry:
+ %tmp7 = fdiv double 1.000000e+00, %tmp6
+ %tmp8 = fmul double 0.000000e+00, %tmp7
+ %tmp9 = fmul reassoc nnan arcp contract double 0.000000e+00, %tmp8
+ %.i188 = fadd contract double %tmp9, 0.000000e+00
+ %tmp10 = fcmp uge double %.i188, %tmp2
+ %tmp11 = fneg nsz double %.i188
+ %.i092 = select i1 %tmp10, double %tmp2, double %tmp11
+ %tmp12 = fcmp ule double %.i092, 0.000000e+00
+ %.i198 = select i1 %tmp12, double 0.000000e+00, double 0x7FF8000000000000
+ ret double %.i198
+}
+
; This is a workaround because -enable-no-signed-zeros-fp-math does not set up
; function attribute unsafe-fp-math automatically. Combine with the previous test
; when that is done.
@@ -2447,23 +2561,28 @@ define <2 x float> @v_fneg_maximumnum_multi_use_maximumnum_f32_no_ieee(float %a,
; --------------------------------------------------------------------------------
define float @v_fneg_fma_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, -v1, -v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.fma.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
ret float %fneg
}
+define float @v_fneg_fma_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, -v1, -v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define { float, float } @v_fneg_fma_store_use_fma_f32(float %a, float %b, float %c) #0 {
; GCN-LABEL: v_fneg_fma_store_use_fma_f32:
; GCN: ; %bb.0:
@@ -2479,20 +2598,13 @@ define { float, float } @v_fneg_fma_store_use_fma_f32(float %a, float %b, float
}
define { float, float } @v_fneg_fma_multi_use_fma_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_multi_use_fma_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v1, v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
-; GCN-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_multi_use_fma_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, -v1, -v2
-; GCN-NSZ-NEXT: v_mul_f32_e32 v1, -4.0, v0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_multi_use_fma_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v1, v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 4.0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.fma.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
%use1 = fmul float %fma, 4.0
@@ -2501,57 +2613,78 @@ define { float, float } @v_fneg_fma_multi_use_fma_f32(float %a, float %b, float
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_fma_multi_use_fma_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_multi_use_fma_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, -v1, -v2
+; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fma, 4.0
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1
+ ret { float, float } %insert.1
+}
+
define float @v_fneg_fma_fneg_x_y_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_fneg_x_y_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_fneg_x_y_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, v1, -v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_fneg_x_y_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, -v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
ret float %fneg
}
+define float @v_fneg_fma_fneg_x_y_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_fneg_x_y_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, -v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define float @v_fneg_fma_x_fneg_y_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_x_fneg_y_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, v0, -v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_x_fneg_y_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, v1, -v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_x_fneg_y_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, -v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.b = fneg float %b
%fma = call float @llvm.fma.f32(float %a, float %fneg.b, float %c)
%fneg = fneg float %fma
ret float %fneg
}
+define float @v_fneg_fma_x_fneg_y_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_x_fneg_y_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, -v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.b = fneg float %b
+ %fma = call nsz float @llvm.fma.f32(float %a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define float @v_fneg_fma_fneg_fneg_y_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_fneg_fneg_y_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, -v1, -v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_fneg_fneg_y_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fneg.b = fneg float %b
%fma = call float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)
@@ -2559,19 +2692,26 @@ define float @v_fneg_fma_fneg_fneg_y_f32(float %a, float %b, float %c) #0 {
ret float %fneg
}
+define float @v_fneg_fma_fneg_fneg_y_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_fneg_fneg_y_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, -v1, -v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fneg.b = fneg float %b
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %fneg.b, float %c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define float @v_fneg_fma_fneg_x_fneg_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, -v0, v1, -v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_fneg_x_fneg_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, v1, v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_fneg_x_fneg_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, -v0, v1, -v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fneg.c = fneg float %c
%fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)
@@ -2579,42 +2719,53 @@ define float @v_fneg_fma_fneg_x_fneg_f32(float %a, float %b, float %c) #0 {
ret float %fneg
}
+define float @v_fneg_fma_fneg_x_fneg_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_fneg_x_fneg_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fneg.c = fneg float %c
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %fneg.c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define float @v_fneg_fma_x_y_fneg_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_x_y_fneg_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v0, v0, v1, -v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_x_y_fneg_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, -v1, v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_x_y_fneg_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, v1, -v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.c = fneg float %c
%fma = call float @llvm.fma.f32(float %a, float %b, float %fneg.c)
%fneg = fneg float %fma
ret float %fneg
}
+define float @v_fneg_fma_x_y_fneg_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_x_y_fneg_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v0, v0, -v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.c = fneg float %c
+ %fma = call nsz float @llvm.fma.f32(float %a, float %b, float %fneg.c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define { float, float } @v_fneg_fma_store_use_fneg_x_y_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
-; GCN-SAFE-NEXT: v_fma_f32 v0, -v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: v_mov_b32_e32 v1, v3
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
-; GCN-NSZ-NEXT: v_fma_f32 v0, v0, v1, -v2
-; GCN-NSZ-NEXT: v_mov_b32_e32 v1, v3
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_store_use_fneg_x_y_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; GCN-NEXT: v_fma_f32 v0, -v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: v_mov_b32_e32 v1, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
@@ -2623,23 +2774,31 @@ define { float, float } @v_fneg_fma_store_use_fneg_x_y_f32(float %a, float %b, f
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_fma_store_use_fneg_x_y_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fma_store_use_fneg_x_y_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; GCN-NEXT: v_fma_f32 v0, v0, v1, -v2
+; GCN-NEXT: v_mov_b32_e32 v1, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fneg = fneg float %fma
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %fneg.a, 1
+ ret { float, float } %insert.1
+}
+
define { float, float } @v_fneg_fma_multi_use_fneg_x_y_f32(float %a, float %b, float %c, float %d) #0 {
-; GCN-SAFE-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v1, -v0, v1, v2
-; GCN-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
-; GCN-SAFE-NEXT: v_mul_f32_e64 v1, -v0, v3
-; GCN-SAFE-NEXT: v_mov_b32_e32 v0, v2
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v2, v0, v1, -v2
-; GCN-NSZ-NEXT: v_mul_f32_e64 v1, -v0, v3
-; GCN-NSZ-NEXT: v_mov_b32_e32 v0, v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v1, -v0, v1, v2
+; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v1
+; GCN-NEXT: v_mul_f32_e64 v1, -v0, v3
+; GCN-NEXT: v_mov_b32_e32 v0, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fneg.a = fneg float %a
%fma = call float @llvm.fma.f32(float %fneg.a, float %b, float %c)
%fneg = fneg float %fma
@@ -2649,70 +2808,90 @@ define { float, float } @v_fneg_fma_multi_use_fneg_x_y_f32(float %a, float %b, f
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_fma_multi_use_fneg_x_y_f32_nsz(float %a, float %b, float %c, float %d) #0 {
+; GCN-LABEL: v_fneg_fma_multi_use_fneg_x_y_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v2, v0, v1, -v2
+; GCN-NEXT: v_mul_f32_e64 v1, -v0, v3
+; GCN-NEXT: v_mov_b32_e32 v0, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fneg.a = fneg float %a
+ %fma = call nsz float @llvm.fma.f32(float %fneg.a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fneg.a, %d
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1
+ ret { float, float } %insert.1
+}
+
; --------------------------------------------------------------------------------
; fmad tests
; --------------------------------------------------------------------------------
define float @v_fneg_fmad_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fmad_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_mac_f32_e32 v2, v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v2
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fmad_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_mad_f32 v0, v0, -v1, -v2
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fmad_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mac_f32_e32 v2, v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
ret float %fneg
}
+define float @v_fneg_fmad_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fmad_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mad_f32 v0, v0, -v1, -v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz float @llvm.fmuladd.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ ret float %fneg
+}
+
define <4 x float> @v_fneg_fmad_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fmad_v4f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_mac_f32_e32 v11, v3, v7
-; GCN-SAFE-NEXT: v_mac_f32_e32 v10, v2, v6
-; GCN-SAFE-NEXT: v_mac_f32_e32 v9, v1, v5
-; GCN-SAFE-NEXT: v_mac_f32_e32 v8, v0, v4
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v8
-; GCN-SAFE-NEXT: v_xor_b32_e32 v1, 0x80000000, v9
-; GCN-SAFE-NEXT: v_xor_b32_e32 v2, 0x80000000, v10
-; GCN-SAFE-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fmad_v4f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_mad_f32 v0, v0, -v4, -v8
-; GCN-NSZ-NEXT: v_mad_f32 v1, v1, -v5, -v9
-; GCN-NSZ-NEXT: v_mad_f32 v2, v2, -v6, -v10
-; GCN-NSZ-NEXT: v_mad_f32 v3, v3, -v7, -v11
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fmad_v4f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mac_f32_e32 v11, v3, v7
+; GCN-NEXT: v_mac_f32_e32 v10, v2, v6
+; GCN-NEXT: v_mac_f32_e32 v9, v1, v5
+; GCN-NEXT: v_mac_f32_e32 v8, v0, v4
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v8
+; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v9
+; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v10
+; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v11
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
%fneg = fneg <4 x float> %fma
ret <4 x float> %fneg
}
+define <4 x float> @v_fneg_fmad_v4f32_nsz(<4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {
+; GCN-LABEL: v_fneg_fmad_v4f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mad_f32 v0, v0, -v4, -v8
+; GCN-NEXT: v_mad_f32 v1, v1, -v5, -v9
+; GCN-NEXT: v_mad_f32 v2, v2, -v6, -v10
+; GCN-NEXT: v_mad_f32 v3, v3, -v7, -v11
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz <4 x float> @llvm.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
+ %fneg = fneg <4 x float> %fma
+ ret <4 x float> %fneg
+}
+
define { float, float } @v_fneg_fmad_multi_use_fmad_f32(float %a, float %b, float %c) #0 {
-; GCN-SAFE-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_mac_f32_e32 v2, v0, v1
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v2
-; GCN-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v2
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_fmad_multi_use_fmad_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_mad_f32 v0, v0, -v1, -v2
-; GCN-NSZ-NEXT: v_mul_f32_e32 v1, -4.0, v0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_fmad_multi_use_fmad_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mac_f32_e32 v2, v0, v1
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v2
+; GCN-NEXT: v_mul_f32_e32 v1, 4.0, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
%fneg = fneg float %fma
%use1 = fmul float %fma, 4.0
@@ -2721,6 +2900,21 @@ define { float, float } @v_fneg_fmad_multi_use_fmad_f32(float %a, float %b, floa
ret { float, float } %insert.1
}
+define { float, float } @v_fneg_fmad_multi_use_fmad_f32_nsz(float %a, float %b, float %c) #0 {
+; GCN-LABEL: v_fneg_fmad_multi_use_fmad_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mad_f32 v0, v0, -v1, -v2
+; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma = call nsz float @llvm.fmuladd.f32(float %a, float %b, float %c)
+ %fneg = fneg float %fma
+ %use1 = fmul float %fma, 4.0
+ %insert.0 = insertvalue { float, float } poison, float %fneg, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %use1, 1
+ ret { float, float } %insert.1
+}
+
; --------------------------------------------------------------------------------
; fp_extend tests
; --------------------------------------------------------------------------------
@@ -3232,35 +3426,40 @@ define float @v_fneg_trunc_f32(float %a) #0 {
; --------------------------------------------------------------------------------
define float @v_fneg_round_f32(float %a) #0 {
-; GCN-SAFE-LABEL: v_fneg_round_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_trunc_f32_e32 v1, v0
-; GCN-SAFE-NEXT: v_sub_f32_e32 v2, v0, v1
-; GCN-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
-; GCN-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
-; GCN-SAFE-NEXT: s_brev_b32 s4, -2
-; GCN-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
-; GCN-SAFE-NEXT: v_add_f32_e32 v0, v1, v0
-; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: v_fneg_round_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_trunc_f32_e32 v1, v0
-; GCN-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
-; GCN-NSZ-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
-; GCN-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
-; GCN-NSZ-NEXT: s_brev_b32 s4, -2
-; GCN-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
-; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v1, v0
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_fneg_round_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_trunc_f32_e32 v1, v0
+; GCN-NEXT: v_sub_f32_e32 v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GCN-NEXT: s_brev_b32 s4, -2
+; GCN-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GCN-NEXT: v_add_f32_e32 v0, v1, v0
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%round = call float @llvm.round.f32(float %a)
%fneg = fneg float %round
ret float %fneg
}
+define float @v_fneg_round_f32_nsz(float %a) #0 {
+; GCN-LABEL: v_fneg_round_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_trunc_f32_e32 v1, v0
+; GCN-NEXT: v_sub_f32_e32 v2, v0, v1
+; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GCN-NEXT: s_brev_b32 s4, -2
+; GCN-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GCN-NEXT: v_sub_f32_e64 v0, -v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %round = call nsz float @llvm.round.f32(float %a)
+ %fneg = fneg float %round
+ ret float %fneg
+}
+
; --------------------------------------------------------------------------------
; rint tests
; --------------------------------------------------------------------------------
@@ -3413,12 +3612,12 @@ define void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, float %a, float %b, flo
; SI-NEXT: v_mul_f32_e32 v2, v2, v3
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; SI-NEXT: s_cbranch_execz .LBB192_2
+; SI-NEXT: s_cbranch_execz .LBB220_2
; SI-NEXT: ; %bb.1: ; %if
; SI-NEXT: v_mul_f32_e64 v3, -v2, v4
; SI-NEXT: flat_store_dword v[0:1], v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: .LBB192_2: ; %endif
+; SI-NEXT: .LBB220_2: ; %endif
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -3434,12 +3633,12 @@ define void @v_fneg_copytoreg_f32(ptr addrspace(1) %out, float %a, float %b, flo
; VI-NEXT: v_mul_f32_e32 v2, v2, v3
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT: s_cbranch_execz .LBB192_2
+; VI-NEXT: s_cbranch_execz .LBB220_2
; VI-NEXT: ; %bb.1: ; %if
; VI-NEXT: v_mul_f32_e64 v3, -v2, v4
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: .LBB192_2: ; %endif
+; VI-NEXT: .LBB220_2: ; %endif
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3564,21 +3763,13 @@ define { float, float } @multiuse_fneg_vop2_vop3_users_f32(float %a, float %b, f
; The use of the fneg requires a code size increase, but folding into
; the source does not
define { float, float } @free_fold_src_code_size_cost_use_f32(ptr addrspace(1) %out, float %a, float %b, float %c, float %d) #0 {
-; GCN-SAFE-LABEL: free_fold_src_code_size_cost_use_f32:
-; GCN-SAFE: ; %bb.0:
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_fma_f32 v1, v2, v3, 2.0
-; GCN-SAFE-NEXT: v_mul_f32_e64 v0, -v1, v4
-; GCN-SAFE-NEXT: v_mul_f32_e64 v1, -v1, v5
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NSZ-LABEL: free_fold_src_code_size_cost_use_f32:
-; GCN-NSZ: ; %bb.0:
-; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NSZ-NEXT: v_fma_f32 v1, v2, -v3, -2.0
-; GCN-NSZ-NEXT: v_mul_f32_e32 v0, v1, v4
-; GCN-NSZ-NEXT: v_mul_f32_e32 v1, v1, v5
-; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: free_fold_src_code_size_cost_use_f32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v1, v2, v3, 2.0
+; GCN-NEXT: v_mul_f32_e64 v0, -v1, v4
+; GCN-NEXT: v_mul_f32_e64 v1, -v1, v5
+; GCN-NEXT: s_setpc_b64 s[30:31]
%fma0 = call float @llvm.fma.f32(float %a, float %b, float 2.0)
%fneg.fma0 = fneg float %fma0
%mul1 = fmul float %fneg.fma0, %c
@@ -3589,6 +3780,24 @@ define { float, float } @free_fold_src_code_size_cost_use_f32(ptr addrspace(1) %
ret { float, float } %insert.1
}
+define { float, float } @free_fold_src_code_size_cost_use_f32_nsz(ptr addrspace(1) %out, float %a, float %b, float %c, float %d) #0 {
+; GCN-LABEL: free_fold_src_code_size_cost_use_f32_nsz:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_fma_f32 v1, v2, -v3, -2.0
+; GCN-NEXT: v_mul_f32_e32 v0, v1, v4
+; GCN-NEXT: v_mul_f32_e32 v1, v1, v5
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %fma0 = call nsz float @llvm.fma.f32(float %a, float %b, float 2.0)
+ %fneg.fma0 = fneg float %fma0
+ %mul1 = fmul float %fneg.fma0, %c
+ %mul2 = fmul float %fneg.fma0, %d
+
+ %insert.0 = insertvalue { float, float } poison, float %mul1, 0
+ %insert.1 = insertvalue { float, float } %insert.0, float %mul2, 1
+ ret { float, float } %insert.1
+}
+
define { double, double } @free_fold_src_code_size_cost_use_f64(double %a, double %b, double %c, double %d) #0 {
; GCN-LABEL: free_fold_src_code_size_cost_use_f64:
; GCN: ; %bb.0:
@@ -4383,20 +4592,12 @@ define float @v_fneg_fabs_select_infloop_regression(float %arg, i1 %arg1) {
}
define float @v_fmul_0_fsub_0_safe_infloop_regression(float %arg) {
-; GCN-SAFE-LABEL: v_fmul_0_fsub_0_safe_infloop_regression:
-; GCN-SAFE: ; %bb.0: ; %bb
-; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-SAFE-NEXT: v_mul_f32_e32 v0, 0, v0
-; GCN-SAFE-NEXT: v_sub_f32_e32 v0, 0, v0
-; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-NSZ-LABEL: v_fmul_0_fsub_0_safe_infloop_regression:
-; SI-NSZ: ; %bb.0: ; %bb
-; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NSZ-NEXT: s_brev_b32 s4, 1
-; SI-NSZ-NEXT: v_fma_f32 v0, v0, s4, 0
-; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
+; GCN-LABEL: v_fmul_0_fsub_0_safe_infloop_regression:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v0, 0, v0
+; GCN-NEXT: v_sub_f32_e32 v0, 0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
; FIXME: utils/update_llc_test_checks.py will generate redundant VI
; labels, remove them, they will cause test failure.
bb:
@@ -4461,5 +4662,4 @@ declare half @llvm.amdgcn.rcp.f16(half) #1
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
-attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" }
attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
diff --git a/llvm/test/CodeGen/AMDGPU/omod.ll b/llvm/test/CodeGen/AMDGPU/omod.ll
index 7ed68dd6a00fe..c248de294eb81 100644
--- a/llvm/test/CodeGen/AMDGPU/omod.ll
+++ b/llvm/test/CodeGen/AMDGPU/omod.ll
@@ -393,7 +393,7 @@ define amdgpu_ps void @v_omod_div2_f32(float %a) #0 {
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2 = fmul float %add, 0.5
+ %div2 = fmul nsz float %add, 0.5
store float %div2, ptr addrspace(1) poison
ret void
}
@@ -451,7 +451,7 @@ define amdgpu_ps void @v_omod_mul2_f32(float %a) #0 {
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2 = fmul float %add, 2.0
+ %div2 = fmul nsz float %add, 2.0
store float %div2, ptr addrspace(1) poison
ret void
}
@@ -483,7 +483,7 @@ define amdgpu_ps void @v_omod_mul2_med3(float %x, float %y, float %z) #0 {
; GFX12-NEXT: global_store_b32 v[0:1], v0, off
; GFX12-NEXT: s_endpgm
%fmed3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)
- %div2 = fmul float %fmed3, 2.0
+ %div2 = fmul nsz float %fmed3, 2.0
store float %div2, ptr addrspace(1) poison
ret void
}
@@ -541,7 +541,7 @@ define amdgpu_ps void @v_omod_mul4_f32(float %a) #0 {
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2 = fmul float %add, 4.0
+ %div2 = fmul nsz float %add, 4.0
store float %div2, ptr addrspace(1) poison
ret void
}
@@ -649,7 +649,7 @@ define amdgpu_ps void @v_omod_mul4_dbg_use_f32(float %a) #0 {
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10
- %div2 = fmul float %add, 4.0
+ %div2 = fmul nsz float %add, 4.0
store float %div2, ptr addrspace(1) poison
ret void
}
@@ -676,7 +676,7 @@ define amdgpu_ps void @v_clamp_omod_div2_f32(float %a) #0 {
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2 = fmul float %add, 0.5
+ %div2 = fmul nsz float %add, 0.5
%max = call float @llvm.maxnum.f32(float %div2, float 0.0)
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
@@ -933,7 +933,7 @@ define amdgpu_ps void @v_omod_div2_omod_div2_f32(float %a) #0 {
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2.0 = fmul float %add, 0.5
+ %div2.0 = fmul nsz float %add, 0.5
%div2.1 = fmul float %div2.0, 0.5
store float %div2.1, ptr addrspace(1) poison
ret void
@@ -1132,7 +1132,7 @@ define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
; GFX12-FAKE16-NEXT: s_endpgm
%add = fadd half %a, 1.0
- %div2 = fmul half %add, 0.5
+ %div2 = fmul nsz half %add, 0.5
store half %div2, ptr addrspace(1) poison
ret void
}
@@ -1190,7 +1190,7 @@ define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
; GFX12-FAKE16-NEXT: s_endpgm
%add = fadd half %a, 1.0
- %mul2 = fadd half %add, %add
+ %mul2 = fadd nsz half %add, %add
store half %mul2, ptr addrspace(1) poison
ret void
}
@@ -1238,7 +1238,7 @@ define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
; GFX12-FAKE16-NEXT: s_endpgm
%add = fadd half %a, 1.0
- %div2 = fmul half %add, 0.5
+ %div2 = fmul nsz half %add, 0.5
store half %div2, ptr addrspace(1) poison
ret void
}
@@ -1270,7 +1270,7 @@ define amdgpu_ps void @v_omod_mac_to_mad(float %b, float %a) #0 {
; GFX11PLUS-NEXT: s_endpgm
%mul = fmul float %a, %a
%add = fadd float %mul, %b
- %mad = fmul float %add, 2.0
+ %mad = fmul nsz float %add, 2.0
%res = fmul float %mad, %b
store float %res, ptr addrspace(1) poison
ret void
@@ -1297,7 +1297,7 @@ define amdgpu_ps void @v_clamp_omod_div2_f32_minimumnum_maximumnum(float %a) #0
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
; GFX11PLUS-NEXT: s_endpgm
%add = fadd float %a, 1.0
- %div2 = fmul float %add, 0.5
+ %div2 = fmul nsz float %add, 0.5
%max = call float @llvm.maximumnum.f32(float %div2, float 0.0)
%clamp = call float @llvm.minimumnum.f32(float %max, float 1.0)
@@ -1319,13 +1319,13 @@ declare half @llvm.minnum.f16(half, half) #1
declare half @llvm.maxnum.f16(half, half) #1
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
-attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-signed-zeros-fp-math"="true" }
+attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #1 = { nounwind readnone }
-attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "no-signed-zeros-fp-math"="true" }
-attributes #3 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" "no-signed-zeros-fp-math"="true" }
+attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
+attributes #3 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }
attributes #4 = { nounwind "no-signed-zeros-fp-math"="false" }
attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }
-attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" "no-signed-zeros-fp-math"="true" }
+attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3}
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
index b2317cd653842..4362c570137d0 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
@@ -1,13 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,CI-SAFE %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,VI-SAFE %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SAFE,GFX11-SAFE-FAKE16 %s
-
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=CI,CI-NSZ %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=VI,VI-NSZ %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -enable-no-signed-zeros-fp-math < %s | FileCheck -check-prefixes=GFX11,GFX11-NSZ,GFX11-NSZ-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-SAFE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-SAFE-FAKE16 %s
define half @add_select_fabs_fabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fabs_fabs_f16:
@@ -46,24 +41,6 @@ define half @add_select_fabs_fabs_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -116,26 +93,6 @@ define { half, half } @add_select_multi_use_lhs_fabs_fabs_f16(i32 %c, half %x, h
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v4
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_lhs_fabs_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v1.l, |v1.l|, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v4.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_lhs_fabs_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v1, |v1|, v3
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v4
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -189,26 +146,6 @@ define { half, half } @add_select_multi_store_use_lhs_fabs_fabs_f16(i32 %c, half
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -263,26 +200,6 @@ define { half, half } @add_select_multi_use_rhs_fabs_fabs_f16(i32 %c, half %x, h
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_rhs_fabs_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v1.l, |v2.l|, v4.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_rhs_fabs_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v1, |v2|, v4
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -335,26 +252,6 @@ define half @add_select_fabs_var_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_var_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_var_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half %fabs.x, half %y
@@ -405,26 +302,6 @@ define half @add_select_fabs_negk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half %fabs, half -1.0
@@ -476,26 +353,6 @@ define half @add_select_fabs_negk_negk_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negk_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xbc00
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, 0xc000, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negk_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc000
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, half -2.0, half -1.0
%fabs = call half @llvm.fabs.f16(half %select)
@@ -546,26 +403,6 @@ define half @add_select_posk_posk_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_posk_posk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3c00
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, 0x4000, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_posk_posk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v2, 0x4000
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, half 2.0, half 1.0
%add = fadd half %select, %x
@@ -615,26 +452,6 @@ define half @add_select_negk_fabs_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negk_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negk_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half -1.0, half %fabs
@@ -685,26 +502,6 @@ define half @add_select_negliteralk_fabs_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xe400, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negliteralk_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xe400, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negliteralk_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xe400, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half -1024.0, half %fabs
@@ -751,24 +548,6 @@ define half @add_select_fabs_posk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_posk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_posk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half %fabs, half 1.0
@@ -815,24 +594,6 @@ define half @add_select_posk_fabs_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_posk_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e64 v0.l, |v0.l|, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_posk_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e64 v0, |v0|, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs = call half @llvm.fabs.f16(half %x)
%select = select i1 %cmp, half 1.0, half %fabs
@@ -877,24 +638,6 @@ define half @add_select_fneg_fneg_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%fneg.y = fneg half %y
@@ -947,26 +690,6 @@ define { half, half } @add_select_multi_use_lhs_fneg_fneg_f16(i32 %c, half %x, h
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_lhs_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v1.l, v4.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_lhs_fneg_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v1, v4, v1
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%fneg.y = fneg half %y
@@ -1020,26 +743,6 @@ define { half, half } @add_select_multi_store_use_lhs_fneg_fneg_f16(i32 %c, half
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%fneg.y = fneg half %y
@@ -1094,26 +797,6 @@ define { half, half } @add_select_multi_use_rhs_fneg_fneg_f16(i32 %c, half %x, h
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_multi_use_rhs_fneg_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v1.l, v4.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_multi_use_rhs_fneg_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v1, v4, v2
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%fneg.y = fneg half %y
@@ -1166,26 +849,6 @@ define half @add_select_fneg_var_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_var_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_var_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half %fneg.x, half %y
@@ -1232,24 +895,6 @@ define half @add_select_fneg_negk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half %fneg.x, half -1.0
@@ -1296,24 +941,6 @@ define half @add_select_fneg_inv2pi_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_inv2pi_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xb118, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_inv2pi_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xb118, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half %fneg.x, half 0xH3118
@@ -1360,24 +987,6 @@ define half @add_select_fneg_neginv2pi_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_neginv2pi_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3118, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_neginv2pi_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3118, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half %fneg.x, half 0xHB118
@@ -1428,26 +1037,6 @@ define half @add_select_negk_negk_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negk_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xbc00
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, 0xc000, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negk_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc000
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, half -2.0, half -1.0
%add = fadd half %select, %x
@@ -1497,26 +1086,6 @@ define half @add_select_negliteralk_negliteralk_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xec00, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negliteralk_negliteralk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xec00
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, 0xe800, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negliteralk_negliteralk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v2, 0xe800
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xec00, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, half -2048.0, half -4096.0
%add = fadd half %select, %x
@@ -1566,26 +1135,6 @@ define half @add_select_fneg_negk_negk_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_negk_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xbc00
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, 0xc000, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v1.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_negk_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc000
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v1, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, half -2.0, half -1.0
%fneg.x = fneg half %select
@@ -1632,24 +1181,6 @@ define half @add_select_negk_fneg_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negk_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negk_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x3c00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half -1.0, half %fneg.x
@@ -1696,24 +1227,6 @@ define half @add_select_fneg_posk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fneg_posk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fneg_posk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half %fneg.x, half 1.0
@@ -1760,24 +1273,6 @@ define half @add_select_posk_fneg_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_posk_fneg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_posk_fneg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xbc00, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v2, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fneg half %x
%select = select i1 %cmp, half 1.0, half %fneg.x
@@ -1830,28 +1325,6 @@ define half @add_select_negfabs_fabs_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negfabs_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.h, 0x7fff, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negfabs_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -1906,28 +1379,6 @@ define half @add_select_fabs_negfabs_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_negfabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_negfabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v2, 0x8000, v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -1982,28 +1433,6 @@ define half @add_select_neg_fabs_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_neg_fabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.h, 0x7fff, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_neg_fabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fsub half -0.000000e+00, %x
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -2057,28 +1486,6 @@ define half @add_select_fabs_neg_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_fabs_neg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_fabs_neg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.y = fsub half -0.000000e+00, %y
@@ -2128,26 +1535,6 @@ define half @add_select_neg_negfabs_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_neg_negfabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_neg_negfabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fneg.x = fsub half -0.000000e+00, %x
%fabs.y = call half @llvm.fabs.f16(half %y)
@@ -2198,26 +1585,6 @@ define half @add_select_negfabs_neg_f16(i32 %c, half %x, half %y, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: add_select_negfabs_neg_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, v3.l, v0.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: add_select_negfabs_neg_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v0, v3, v0
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -2270,26 +1637,6 @@ define half @mul_select_negfabs_posk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: mul_select_negfabs_posk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: mul_select_negfabs_posk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -2341,26 +1688,6 @@ define half @mul_select_posk_negfabs_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: mul_select_posk_negfabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: mul_select_posk_negfabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -2412,26 +1739,6 @@ define half @mul_select_negfabs_negk_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: mul_select_negfabs_negk_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: mul_select_negfabs_negk_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -2483,26 +1790,6 @@ define half @mul_select_negk_negfabs_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: mul_select_negk_negfabs_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: mul_select_negk_negfabs_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xc400, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fabs.x = call half @llvm.fabs.f16(half %x)
%fneg.fabs.x = fsub half -0.000000e+00, %fabs.x
@@ -2516,27 +1803,25 @@ define half @mul_select_negk_negfabs_f16(i32 %c, half %x, half %y) {
; --------------------------------------------------------------------------------
define half @select_fneg_posk_src_add_f16(i32 %c, half %x, half %y) {
-; CI-SAFE-LABEL: select_fneg_posk_src_add_f16:
-; CI-SAFE: ; %bb.0:
-; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-SAFE-NEXT: v_add_f32_e32 v1, 4.0, v1
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: select_fneg_posk_src_add_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f16_e32 v1, 4.0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; CI-LABEL: select_fneg_posk_src_add_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_add_f32_e32 v1, 4.0, v1
+; CI-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_add_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v1, 4.0, v1
+; VI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_add_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
@@ -2557,44 +1842,6 @@ define half @select_fneg_posk_src_add_f16(i32 %c, half %x, half %y) {
; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; CI-NSZ-LABEL: select_fneg_posk_src_add_f16:
-; CI-NSZ: ; %bb.0:
-; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NSZ-NEXT: v_sub_f32_e32 v1, -4.0, v1
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: select_fneg_posk_src_add_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e32 v1, -4.0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_add_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, -4.0, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_add_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v1, -4.0, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%add = fadd half %x, 4.0
%fneg = fneg half %add
@@ -2602,30 +1849,72 @@ define half @select_fneg_posk_src_add_f16(i32 %c, half %x, half %y) {
ret half %select
}
-define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
-; CI-SAFE-LABEL: select_fneg_posk_src_sub_f16:
-; CI-SAFE: ; %bb.0:
-; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-SAFE-NEXT: v_add_f32_e32 v1, -4.0, v1
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: select_fneg_posk_src_sub_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_add_f16_e32 v1, -4.0, v1
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+define half @select_fneg_posk_src_add_f16_nsz(i32 %c, half %x, half %y) {
+; CI-LABEL: select_fneg_posk_src_add_f16_nsz:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_sub_f32_e32 v1, -4.0, v1
+; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_sub_f16:
+; VI-LABEL: select_fneg_posk_src_add_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v1, -4.0, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_add_f16_nsz:
+; GFX11-SAFE-TRUE16: ; %bb.0:
+; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, -4.0, v1.l
+; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
+; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_add_f16_nsz:
+; GFX11-SAFE-FAKE16: ; %bb.0:
+; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v1, -4.0, v1
+; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
+; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %c, 0
+ %add = fadd nsz half %x, 4.0
+ %fneg = fneg half %add
+ %select = select i1 %cmp, half %fneg, half 2.0
+ ret half %select
+}
+
+define half @select_fneg_posk_src_sub_f16_nsz(i32 %c, half %x) {
+; CI-LABEL: select_fneg_posk_src_sub_f16_nsz:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_add_f32_e32 v1, -4.0, v1
+; CI-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_sub_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_f16_e32 v1, -4.0, v1
+; VI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_sub_f16_nsz:
; GFX11-SAFE-TRUE16: ; %bb.0:
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SAFE-TRUE16-NEXT: v_add_f16_e32 v1.l, -4.0, v1.l
@@ -2635,7 +1924,7 @@ define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_sub_f16:
+; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_sub_f16_nsz:
; GFX11-SAFE-FAKE16: ; %bb.0:
; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SAFE-FAKE16-NEXT: v_add_f16_e32 v1, -4.0, v1
@@ -2644,44 +1933,6 @@ define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; CI-NSZ-LABEL: select_fneg_posk_src_sub_f16:
-; CI-NSZ: ; %bb.0:
-; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NSZ-NEXT: v_sub_f32_e32 v1, 4.0, v1
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: select_fneg_posk_src_sub_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_sub_f16_e32 v1, 4.0, v1
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_sub_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_sub_f16_e32 v0.l, 4.0, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_sub_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_sub_f16_e32 v1, 4.0, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%add = fsub half %x, 4.0
%fneg = fneg half %add
@@ -2689,6 +1940,50 @@ define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
ret half %select
}
+define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
+; CI-LABEL: select_fneg_posk_src_sub_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_sub_f32_e32 v1, 4.0, v1
+; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_sub_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_sub_f16_e32 v1, 4.0, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_sub_f16:
+; GFX11-SAFE-TRUE16: ; %bb.0:
+; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-TRUE16-NEXT: v_sub_f16_e32 v0.l, 4.0, v1.l
+; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
+; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_sub_f16:
+; GFX11-SAFE-FAKE16: ; %bb.0:
+; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-FAKE16-NEXT: v_sub_f16_e32 v1, 4.0, v1
+; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
+; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %c, 0
+ %add = fsub nsz half %x, 4.0
+ %fneg = fneg half %add
+ %select = select i1 %cmp, half %fneg, half 2.0
+ ret half %select
+}
+
define half @select_fneg_posk_src_mul_f16(i32 %c, half %x) {
; CI-LABEL: select_fneg_posk_src_mul_f16:
; CI: ; %bb.0:
@@ -2727,24 +2022,6 @@ define half @select_fneg_posk_src_mul_f16(i32 %c, half %x) {
; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_mul_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e32 v0.l, -4.0, v1.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_mul_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_mul_f16_e32 v1, -4.0, v1
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%mul = fmul half %x, 4.0
%fneg = fneg half %mul
@@ -2753,72 +2030,26 @@ define half @select_fneg_posk_src_mul_f16(i32 %c, half %x) {
}
define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
-; CI-SAFE-LABEL: select_fneg_posk_src_fma_f16:
-; CI-SAFE: ; %bb.0:
-; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
-; CI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
-; CI-SAFE-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
-; CI-SAFE-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
-; CI-SAFE-NEXT: v_fma_f64 v[1:2], v[3:4], 4.0, v[1:2]
-; CI-SAFE-NEXT: v_and_b32_e32 v3, 0x1ff, v2
-; CI-SAFE-NEXT: v_or_b32_e32 v1, v3, v1
-; CI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CI-SAFE-NEXT: v_and_b32_e32 v3, 0xffe, v4
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CI-SAFE-NEXT: v_bfe_u32 v4, v2, 20, 11
-; CI-SAFE-NEXT: v_or_b32_e32 v1, v3, v1
-; CI-SAFE-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
-; CI-SAFE-NEXT: v_or_b32_e32 v3, 0x1000, v1
-; CI-SAFE-NEXT: v_med3_i32 v5, v5, 0, 13
-; CI-SAFE-NEXT: v_lshrrev_b32_e32 v6, v5, v3
-; CI-SAFE-NEXT: v_lshlrev_b32_e32 v5, v5, v6
-; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
-; CI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; CI-SAFE-NEXT: v_lshlrev_b32_e32 v5, 12, v4
-; CI-SAFE-NEXT: v_or_b32_e32 v3, v6, v3
-; CI-SAFE-NEXT: v_or_b32_e32 v5, v1, v5
-; CI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-SAFE-NEXT: v_and_b32_e32 v5, 7, v3
-; CI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CI-SAFE-NEXT: v_or_b32_e32 v5, v5, v6
-; CI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; CI-SAFE-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; CI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7c00
-; CI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-SAFE-NEXT: v_mov_b32_e32 v6, 0x7e00
-; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CI-SAFE-NEXT: s_movk_i32 s4, 0x40f
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
-; CI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-SAFE-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; CI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1
-; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
-; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: select_fneg_posk_src_fma_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, v1, 4.0, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; CI-LABEL: select_fneg_posk_src_fma_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_fma_f32 v1, v1, 4.0, v2
+; CI-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_fma_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v1, 4.0, v2
+; VI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fma_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
@@ -2839,89 +2070,6 @@ define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v2
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; CI-NSZ-LABEL: select_fneg_posk_src_fma_f16:
-; CI-NSZ: ; %bb.0:
-; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
-; CI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
-; CI-NSZ-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
-; CI-NSZ-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
-; CI-NSZ-NEXT: v_fma_f64 v[1:2], v[3:4], -4.0, v[1:2]
-; CI-NSZ-NEXT: v_and_b32_e32 v3, 0x1ff, v2
-; CI-NSZ-NEXT: v_or_b32_e32 v1, v3, v1
-; CI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CI-NSZ-NEXT: v_and_b32_e32 v3, 0xffe, v4
-; CI-NSZ-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CI-NSZ-NEXT: v_bfe_u32 v4, v2, 20, 11
-; CI-NSZ-NEXT: v_or_b32_e32 v1, v3, v1
-; CI-NSZ-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
-; CI-NSZ-NEXT: v_or_b32_e32 v3, 0x1000, v1
-; CI-NSZ-NEXT: v_med3_i32 v5, v5, 0, 13
-; CI-NSZ-NEXT: v_lshrrev_b32_e32 v6, v5, v3
-; CI-NSZ-NEXT: v_lshlrev_b32_e32 v5, v5, v6
-; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
-; CI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
-; CI-NSZ-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; CI-NSZ-NEXT: v_lshlrev_b32_e32 v5, 12, v4
-; CI-NSZ-NEXT: v_or_b32_e32 v3, v6, v3
-; CI-NSZ-NEXT: v_or_b32_e32 v5, v1, v5
-; CI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-NSZ-NEXT: v_and_b32_e32 v5, 7, v3
-; CI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
-; CI-NSZ-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
-; CI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CI-NSZ-NEXT: v_or_b32_e32 v5, v5, v6
-; CI-NSZ-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; CI-NSZ-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; CI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7c00
-; CI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-NSZ-NEXT: v_mov_b32_e32 v6, 0x7e00
-; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CI-NSZ-NEXT: s_movk_i32 s4, 0x40f
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
-; CI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NSZ-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; CI-NSZ-NEXT: v_or_b32_e32 v1, v2, v1
-; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: select_fneg_posk_src_fma_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v1, v1, -4.0, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_fma_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, -4.0, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_fma_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_fma_f16 v1, v1, -4.0, -v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fma = call half @llvm.fma.f16(half %x, half 4.0, half %z)
%fneg = fneg half %fma
@@ -2929,32 +2077,73 @@ define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
ret half %select
}
+define half @select_fneg_posk_src_fma_f16_nsz(i32 %c, half %x, half %z) {
+; CI-LABEL: select_fneg_posk_src_fma_f16_nsz:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_fma_f32 v1, v1, -4.0, -v2
+; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_fma_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v1, -4.0, -v2
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fma_f16_nsz:
+; GFX11-SAFE-TRUE16: ; %bb.0:
+; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, -4.0, -v2.l
+; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
+; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_fma_f16_nsz:
+; GFX11-SAFE-FAKE16: ; %bb.0:
+; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-FAKE16-NEXT: v_fma_f16 v1, v1, -4.0, -v2
+; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
+; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %c, 0
+ %fma = call nsz half @llvm.fma.f16(half %x, half 4.0, half %z)
+ %fneg = fneg half %fma
+ %select = select nsz i1 %cmp, half %fneg, half 2.0
+ ret half %select
+}
+
define half @select_fneg_posk_src_fmad_f16(i32 %c, half %x, half %z) {
-; CI-SAFE-LABEL: select_fneg_posk_src_fmad_f16:
-; CI-SAFE: ; %bb.0:
-; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-SAFE-NEXT: v_add_f32_e32 v1, v1, v2
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
-; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: select_fneg_posk_src_fmad_f16:
-; VI-SAFE: ; %bb.0:
-; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT: v_fma_f16 v1, v1, 4.0, v2
-; VI-SAFE-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; VI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
+; CI-LABEL: select_fneg_posk_src_fmad_f16:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_mul_f32_e32 v1, 4.0, v1
+; CI-NEXT: v_add_f32_e32 v1, v1, v2
+; CI-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_fmad_f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v1, 4.0, v2
+; VI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fmad_f16:
; GFX11-SAFE-TRUE16: ; %bb.0:
@@ -2975,48 +2164,6 @@ define half @select_fneg_posk_src_fmad_f16(i32 %c, half %x, half %z) {
; GFX11-SAFE-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v2
; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; CI-NSZ-LABEL: select_fneg_posk_src_fmad_f16:
-; CI-NSZ: ; %bb.0:
-; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NSZ-NEXT: v_mul_f32_e32 v1, -4.0, v1
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NSZ-NEXT: v_sub_f32_e32 v1, v1, v2
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-NSZ-LABEL: select_fneg_posk_src_fmad_f16:
-; VI-NSZ: ; %bb.0:
-; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NSZ-NEXT: v_fma_f16 v1, v1, -4.0, -v2
-; VI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
-; VI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-TRUE16-LABEL: select_fneg_posk_src_fmad_f16:
-; GFX11-NSZ-TRUE16: ; %bb.0:
-; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, -4.0, -v2.l
-; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NSZ-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-NSZ-FAKE16-LABEL: select_fneg_posk_src_fmad_f16:
-; GFX11-NSZ-FAKE16: ; %bb.0:
-; GFX11-NSZ-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NSZ-FAKE16-NEXT: v_fma_f16 v1, v1, -4.0, -v2
-; GFX11-NSZ-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NSZ-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NSZ-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
-; GFX11-NSZ-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %c, 0
%fmad = call half @llvm.fmuladd.f16(half %x, half 4.0, half %z)
%fneg = fneg half %fmad
@@ -3024,12 +2171,54 @@ define half @select_fneg_posk_src_fmad_f16(i32 %c, half %x, half %z) {
ret half %select
}
+define half @select_fneg_posk_src_fmad_f16_nsz(i32 %c, half %x, half %z) {
+; CI-LABEL: select_fneg_posk_src_fmad_f16_nsz:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-NEXT: v_mul_f32_e32 v1, -4.0, v1
+; CI-NEXT: v_sub_f32_e32 v1, v1, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: select_fneg_posk_src_fmad_f16_nsz:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_fma_f16 v1, v1, -4.0, -v2
+; VI-NEXT: v_mov_b32_e32 v2, 0x4000
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-TRUE16-LABEL: select_fneg_posk_src_fmad_f16_nsz:
+; GFX11-SAFE-TRUE16: ; %bb.0:
+; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, -4.0, -v2.l
+; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
+; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SAFE-FAKE16-LABEL: select_fneg_posk_src_fmad_f16_nsz:
+; GFX11-SAFE-FAKE16: ; %bb.0:
+; GFX11-SAFE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SAFE-FAKE16-NEXT: v_fma_f16 v1, v1, -4.0, -v2
+; GFX11-SAFE-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SAFE-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v1, vcc_lo
+; GFX11-SAFE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %c, 0
+ %fmad = call nsz half @llvm.fmuladd.f16(half %x, half 4.0, half %z)
+ %fneg = fneg half %fmad
+ %select = select i1 %cmp, half %fneg, half 2.0
+ ret half %select
+}
+
declare half @llvm.fabs.f16(half) #0
declare half @llvm.fma.f16(half, half, half) #0
declare half @llvm.fmuladd.f16(half, half, half) #0
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11: {{.*}}
-; GFX11-NSZ: {{.*}}
-; GFX11-SAFE: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
index c402b692f797f..23d0a6e7ee411 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
@@ -1,14 +1,52 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -enable-no-signed-zeros-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -enable-no-signed-zeros-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=VI %s
+
+
+
+
+
+
-; GCN-LABEL: {{^}}add_select_fabs_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
define amdgpu_kernel void @add_select_fabs_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -21,16 +59,65 @@ define amdgpu_kernel void @add_select_fabs_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_use_lhs_fabs_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: buffer_load_dword [[W:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
-; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, [[W]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_use_lhs_fabs_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_use_lhs_fabs_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_add_f32_e64 v1, |v1|, v2
+; SI-NEXT: v_add_f32_e64 v0, |v0|, v3
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_use_lhs_fabs_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; VI-NEXT: v_add_f32_e64 v1, |v1|, v2
+; VI-NEXT: v_add_f32_e64 v0, |v0|, v3
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -46,18 +133,63 @@ define amdgpu_kernel void @add_select_multi_use_lhs_fabs_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_store_use_lhs_fabs_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN-DAG: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_add_f32_e64 [[ADD:v[0-9]+]], |[[SELECT]]|, [[Z]]
-; GCN-DAG: v_and_b32_e32 [[X_ABS:v[0-9]+]], 0x7fffffff, [[X]]
-; GCN: buffer_store_dword [[ADD]]
-; GCN: buffer_store_dword [[X_ABS]]
+
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_store_use_lhs_fabs_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -71,16 +203,65 @@ define amdgpu_kernel void @add_select_multi_store_use_lhs_fabs_fabs_f32(i32 %c)
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_use_rhs_fabs_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: buffer_load_dword [[W:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
-; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[Y]]|, [[W]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_use_rhs_fabs_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_use_rhs_fabs_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; SI-NEXT: v_add_f32_e64 v1, |v1|, v3
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_use_rhs_fabs_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; VI-NEXT: v_add_f32_e64 v1, |v1|, v3
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -96,14 +277,53 @@ define amdgpu_kernel void @add_select_multi_use_rhs_fabs_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_var_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[Y]], |[[X]]|,
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fabs_var_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_var_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v1, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_var_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -115,13 +335,48 @@ define amdgpu_kernel void @add_select_fabs_var_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, |[[X]]|,
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
define amdgpu_kernel void @add_select_fabs_negk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -1.0, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -132,12 +387,43 @@ define amdgpu_kernel void @add_select_fabs_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_negk_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, -2.0, s
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[X]], [[SELECT]]
+
+
+
+
define amdgpu_kernel void @add_select_fabs_negk_negk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_negk_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, s[0:1]
+; SI-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_negk_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, s[0:1]
+; VI-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2.0, float -1.0
@@ -147,12 +433,43 @@ define amdgpu_kernel void @add_select_fabs_negk_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_posk_posk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 1.0, 2.0, s
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
+
+
+
+
define amdgpu_kernel void @add_select_posk_posk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_posk_posk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_posk_posk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float 2.0, float 1.0
@@ -161,15 +478,50 @@ define amdgpu_kernel void @add_select_posk_posk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negk_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, |[[X]]|, [[VCC]]
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negk_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negk_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -1.0, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negk_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -180,16 +532,53 @@ define amdgpu_kernel void @add_select_negk_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negliteralk_fabs_f32:
-; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
-; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xc4800000
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], |[[X]]|, [[VCC]]
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negliteralk_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negliteralk_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0xc4800000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negliteralk_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_mov_b32_e32 v2, 0xc4800000
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v2, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -200,13 +589,48 @@ define amdgpu_kernel void @add_select_negliteralk_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_posk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 1.0, |[[X]]|, s{{\[[0-9]+:[0-9]+\]}}
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
define amdgpu_kernel void @add_select_fabs_posk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_posk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_posk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
@@ -218,15 +642,50 @@ define amdgpu_kernel void @add_select_fabs_posk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_posk_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 1.0, |[[X]]|, s{{\[[0-9]+:[0-9]+\]}}
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_posk_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_posk_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_posk_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -237,14 +696,53 @@ define amdgpu_kernel void @add_select_posk_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Z]], [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fneg_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -257,16 +755,65 @@ define amdgpu_kernel void @add_select_fneg_fneg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_use_lhs_fneg_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: buffer_load_dword [[W:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_sub_f32_e32 v{{[0-9]+}}, [[Z]], [[SELECT]]
-; GCN-DAG: v_sub_f32_e32 v{{[0-9]+}}, [[W]], [[X]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_use_lhs_fneg_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_use_lhs_fneg_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v1, v2, v1
+; SI-NEXT: v_sub_f32_e32 v0, v3, v0
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_use_lhs_fneg_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v1, v2, v1
+; VI-NEXT: v_sub_f32_e32 v0, v3, v0
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -282,18 +829,63 @@ define amdgpu_kernel void @add_select_multi_use_lhs_fneg_fneg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_store_use_lhs_fneg_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN-DAG: v_xor_b32_e32 [[NEG_X:v[0-9]+]], 0x80000000, [[X]]
-; GCN-DAG: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_sub_f32_e32 [[ADD:v[0-9]+]], [[Z]], [[SELECT]]
-; GCN: buffer_store_dword [[ADD]]
-; GCN: buffer_store_dword [[NEG_X]]
+
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_store_use_lhs_fneg_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -307,16 +899,65 @@ define amdgpu_kernel void @add_select_multi_store_use_lhs_fneg_fneg_f32(i32 %c)
ret void
}
-; GCN-LABEL: {{^}}add_select_multi_use_rhs_fneg_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: buffer_load_dword [[W:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[Y]], [[X]], vcc
-; GCN-DAG: v_sub_f32_e32 v{{[0-9]+}}, [[Z]], [[SELECT]]
-; GCN-DAG: v_sub_f32_e32 v{{[0-9]+}}, [[W]], [[Y]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_multi_use_rhs_fneg_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_multi_use_rhs_fneg_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-NEXT: v_sub_f32_e32 v1, v3, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_multi_use_rhs_fneg_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-NEXT: v_sub_f32_e32 v1, v3, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -332,14 +973,53 @@ define amdgpu_kernel void @add_select_multi_use_rhs_fneg_fneg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_var_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[Y]], -[[X]],
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fneg_var_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_var_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_var_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -351,13 +1031,48 @@ define amdgpu_kernel void @add_select_fneg_var_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @add_select_fneg_negk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -368,14 +1083,51 @@ define amdgpu_kernel void @add_select_fneg_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_inv2pi_f32:
-; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
-; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xbe22f983
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[K]], [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fneg_inv2pi_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_inv2pi_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_inv2pi_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -386,16 +1138,52 @@ define amdgpu_kernel void @add_select_fneg_inv2pi_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_neginv2pi_f32:
-; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
-; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]]
+
+
+
; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e22f983
; SI: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[K]], [[X]], vcc
; VI: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 0.15915494, [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
define amdgpu_kernel void @add_select_fneg_neginv2pi_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_neginv2pi_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0x3e22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_neginv2pi_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, 0.15915494, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -406,13 +1194,44 @@ define amdgpu_kernel void @add_select_fneg_neginv2pi_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negk_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: s_cmp_eq_u32
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, -2.0, s
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
+
+
+
+
+
define amdgpu_kernel void @add_select_negk_negk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negk_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negk_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2.0, float -1.0
@@ -421,15 +1240,50 @@ define amdgpu_kernel void @add_select_negk_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negliteralk_negliteralk_f32:
-; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 0xc5000000
-; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0xc5800000
-; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
-; GCN: s_cmp_eq_u32
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[K1]], [[K0]], vcc
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negliteralk_negliteralk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negliteralk_negliteralk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v1, 0xc5800000
+; SI-NEXT: v_mov_b32_e32 v2, 0xc5000000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negliteralk_negliteralk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_mov_b32_e32 v1, 0xc5800000
+; VI-NEXT: v_mov_b32_e32 v2, 0xc5000000
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2048.0, float -4096.0
@@ -438,12 +1292,43 @@ define amdgpu_kernel void @add_select_negliteralk_negliteralk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_negk_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 1.0, 2.0, s
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
+
+
+
+
define amdgpu_kernel void @add_select_fneg_negk_negk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_negk_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_negk_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2.0, float -1.0
@@ -453,15 +1338,50 @@ define amdgpu_kernel void @add_select_fneg_negk_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negk_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 vcc, -1, 0
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negk_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negk_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negk_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -472,13 +1392,48 @@ define amdgpu_kernel void @add_select_negk_fneg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fneg_posk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -1.0, [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @add_select_fneg_posk_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fneg_posk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fneg_posk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -489,15 +1444,50 @@ define amdgpu_kernel void @add_select_fneg_posk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_posk_fneg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 vcc, -1, 0
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -1.0, [[X]], vcc
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
+
+
+
+
+
+
+
define amdgpu_kernel void @add_select_posk_fneg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_posk_fneg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
+; SI-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_posk_fneg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -508,14 +1498,53 @@ define amdgpu_kernel void @add_select_posk_fneg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negfabs_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], |[[Y]]|, -|[[X]]|,
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negfabs_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negfabs_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, |v1|, -|v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negfabs_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, |v1|, -|v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -529,14 +1558,53 @@ define amdgpu_kernel void @add_select_negfabs_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -|[[Y]]|, |[[X]]|,
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fabs_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -|v1|, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -|v1|, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -550,14 +1618,53 @@ define amdgpu_kernel void @add_select_fabs_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_neg_fabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], |[[Y]]|, -[[X]],
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_neg_fabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_neg_fabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, |v1|, -v0, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_neg_fabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, |v1|, -v0, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -570,14 +1677,53 @@ define amdgpu_kernel void @add_select_neg_fabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_fabs_neg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -[[Y]], |[[X]]|,
-; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_fabs_neg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_fabs_neg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -v1, |v0|, s[0:1]
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_fabs_neg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -v1, |v0|, s[0:1]
+; VI-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -590,14 +1736,53 @@ define amdgpu_kernel void @add_select_fabs_neg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_neg_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], |[[Y]]|, [[X]],
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Z]], [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_neg_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: add_select_neg_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, |v1|, v0, s[0:1]
+; SI-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_neg_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, |v1|, v0, s[0:1]
+; VI-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -611,14 +1796,53 @@ define amdgpu_kernel void @add_select_neg_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}add_select_negfabs_neg_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], |[[X]]|, [[Y]],
-; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Z]], [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @add_select_negfabs_neg_f32(i32 %c) #0 {
+; SI-LABEL: add_select_negfabs_neg_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, s[0:1]
+; SI-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: add_select_negfabs_neg_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, s[0:1]
+; VI-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
@@ -632,15 +1856,50 @@ define amdgpu_kernel void @add_select_negfabs_neg_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_posk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 4.0, -|[[X]]|, [[VCC]]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negfabs_posk_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_posk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 4.0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_posk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 4.0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -652,15 +1911,50 @@ define amdgpu_kernel void @mul_select_negfabs_posk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_posk_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 4.0, -|[[X]]|, [[VCC]]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_posk_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_posk_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 4.0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_posk_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 4.0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -672,13 +1966,48 @@ define amdgpu_kernel void @mul_select_posk_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_negk_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, -|[[X]]|, s{{\[[0-9]+:[0-9]+\]}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
define amdgpu_kernel void @mul_select_negfabs_negk_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_negk_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -4.0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_negk_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -4.0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -690,15 +2019,50 @@ define amdgpu_kernel void @mul_select_negfabs_negk_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negk_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: s_cmp_lg_u32
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, -|[[X]]|, [[VCC]]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negk_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negk_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, -4.0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negk_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, -4.0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -714,47 +2078,144 @@ define amdgpu_kernel void @mul_select_negk_negfabs_f32(i32 %c) #0 {
; Don't fold if fneg can fold into the source
; --------------------------------------------------------------------------------
-; GCN-LABEL: {{^}}select_fneg_posk_src_add_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_sub_f32_e32 [[ADD:v[0-9]+]], -4.0, [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[ADD]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_add_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_add_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_sub_f32_e32 v0, -4.0, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_add_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_sub_f32_e32 v0, -4.0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
- %add = fadd float %x, 4.0
+ %add = fadd nsz float %x, 4.0
%fneg = fsub float -0.0, %add
%select = select i1 %cmp, float %fneg, float 2.0
store volatile float %select, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}select_fneg_posk_src_sub_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_sub_f32_e32 [[ADD:v[0-9]+]], 4.0, [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[ADD]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_sub_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_sub_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_sub_f32_e32 v0, 4.0, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_sub_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_sub_f32_e32 v0, 4.0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
- %add = fsub float %x, 4.0
+ %add = fsub nsz float %x, 4.0
%fneg = fsub float -0.0, %add
%select = select i1 %cmp, float %fneg, float 2.0
store volatile float %select, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}select_fneg_posk_src_mul_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[MUL]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_mul_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_mul_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_mul_f32_e32 v0, -4.0, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_mul_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_mul_f32_e32 v0, -4.0, v0
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
%mul = fmul float %x, 4.0
@@ -764,35 +2225,106 @@ define amdgpu_kernel void @select_fneg_posk_src_mul_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}select_fneg_posk_src_fma_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[X]], -4.0, -[[Z]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[FMA]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_fma_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_fma_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_fma_f32 v0, v0, -4.0, -v1
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_fma_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_fma_f32 v0, v0, -4.0, -v1
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
- %fma = call float @llvm.fma.f32(float %x, float 4.0, float %z)
+ %fma = call nsz float @llvm.fma.f32(float %x, float 4.0, float %z)
%fneg = fsub float -0.0, %fma
%select = select i1 %cmp, float %fneg, float 2.0
store volatile float %select, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}select_fneg_posk_src_fmad_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Z:v[0-9]+]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[X]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_fmad_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_fmad_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_fma_f32 v0, v0, -4.0, -v1
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_fmad_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_mul_f32_e32 v0, -4.0, v0
+; VI-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%z = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
- %fmad = call float @llvm.fmuladd.f32(float %x, float 4.0, float %z)
+ %fmad = call nsz float @llvm.fmuladd.f32(float %x, float 4.0, float %z)
%fneg = fsub float -0.0, %fmad
%select = select i1 %cmp, float %fneg, float 2.0
store volatile float %select, ptr addrspace(1) poison
@@ -800,13 +2332,48 @@ define amdgpu_kernel void @select_fneg_posk_src_fmad_f32(i32 %c) #0 {
}
; FIXME: This one should fold to rcp
-; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[RCP]], vcc
-; GCN-NEXT: buffer_store_dword [[SELECT]]
+
+
+
+
+
define amdgpu_kernel void @select_fneg_posk_src_rcp_f32(i32 %c) #0 {
+; SI-LABEL: select_fneg_posk_src_rcp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_rcp_f32_e64 v0, -v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: select_fneg_posk_src_rcp_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_rcp_f32_e64 v0, -v0
+; VI-NEXT: v_cndmask_b32_e32 v0, 2.0, v0, vcc
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -817,12 +2384,12 @@ define amdgpu_kernel void @select_fneg_posk_src_rcp_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_posk_inv2pi_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
-; GCN-DAG: s_cselect_b64 [[VCC:.*]], -1, 0
+
+
+
+
+
; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e22f983
; SI: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], -|[[X]]|, [[VCC]]
@@ -831,6 +2398,42 @@ define amdgpu_kernel void @select_fneg_posk_src_rcp_f32(i32 %c) #0 {
; VI: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 0.15915494, -|[[X]]|, [[VCC]]
; VI: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
define amdgpu_kernel void @mul_select_negfabs_posk_inv2pi_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_posk_inv2pi_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0x3e22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_posk_inv2pi_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 0.15915494, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -842,13 +2445,13 @@ define amdgpu_kernel void @mul_select_negfabs_posk_inv2pi_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_posk_inv2pi_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN-DAG: s_cselect_b64 [[VCC:.*]], -1, 0
+
+
+
+
+
; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e22f983
; SI: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], -|[[X]]|, [[VCC]]
@@ -858,6 +2461,42 @@ define amdgpu_kernel void @mul_select_negfabs_posk_inv2pi_f32(i32 %c) #0 {
; VI: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 0.15915494, -|[[X]]|, [[VCC]]
; VI: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
define amdgpu_kernel void @mul_select_posk_inv2pi_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_posk_inv2pi_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0x3e22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_posk_inv2pi_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 0.15915494, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -869,13 +2508,50 @@ define amdgpu_kernel void @mul_select_posk_inv2pi_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_negk_inv2pi_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xbe22f983
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], -|[[X]]|, s
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negfabs_negk_inv2pi_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_negk_inv2pi_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_negk_inv2pi_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -887,16 +2563,53 @@ define amdgpu_kernel void @mul_select_negfabs_negk_inv2pi_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negk_inv2pi_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xbe22f983
-; GCN: s_cmp_lg_u32
-; GCN: s_cselect_b64 s[0:1], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], -|[[X]]|, s[0:1]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negk_inv2pi_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negk_inv2pi_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negk_inv2pi_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_mov_b32_e32 v2, 0xbe22f983
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -908,14 +2621,49 @@ define amdgpu_kernel void @mul_select_negk_inv2pi_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_posk_0_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 0, -|[[X]]|, [[VCC]]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negfabs_posk_0_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_posk_0_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_posk_0_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -928,15 +2676,50 @@ define amdgpu_kernel void @mul_select_negfabs_posk_0_f32(i32 %c) #0 {
}
-; GCN-LABEL: {{^}}mul_select_posk_0_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
-; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], 0, -|[[X]]|, [[VCC]]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_posk_0_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_posk_0_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_posk_0_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, 0, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -948,14 +2731,51 @@ define amdgpu_kernel void @mul_select_posk_0_negfabs_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negfabs_negk_0_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[NEG0]], -|[[X]]|, s{{\[[0-9]+:[0-9]+\]}}
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negfabs_negk_0_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negfabs_negk_0_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_bfrev_b32_e32 v2, 1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_eq_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negfabs_negk_0_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_bfrev_b32_e32 v2, 1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_eq_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
@@ -967,16 +2787,53 @@ define amdgpu_kernel void @mul_select_negfabs_negk_0_f32(i32 %c) #0 {
ret void
}
-; GCN-LABEL: {{^}}mul_select_negk_0_negfabs_f32:
-; GCN: buffer_load_dword [[X:v[0-9]+]]
-; GCN: buffer_load_dword [[Y:v[0-9]+]]
-; GCN: v_bfrev_b32_e32 [[NEG0:v[0-9]+]], 1
-; GCN: s_cmp_lg_u32
-; GCN: s_cselect_b64 s[0:1], -1, 0
-; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[NEG0]], -|[[X]]|, s[0:1]
-; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
+
+
+
+
+
+
+
+
define amdgpu_kernel void @mul_select_negk_0_negfabs_f32(i32 %c) #0 {
+; SI-LABEL: mul_select_negk_0_negfabs_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_load_dword s0, s[4:5], 0x9
+; SI-NEXT: v_bfrev_b32_e32 v2, 1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: mul_select_negk_0_negfabs_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_load_dword s0, s[4:5], 0x24
+; VI-NEXT: v_bfrev_b32_e32 v2, 1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: v_cndmask_b32_e64 v0, v2, -|v0|, s[0:1]
+; VI-NEXT: v_mul_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_endpgm
%x = load volatile float, ptr addrspace(1) poison
%y = load volatile float, ptr addrspace(1) poison
%cmp = icmp eq i32 %c, 0
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
index d1fae8ae92a2a..ed6718ffe6945 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
@@ -12,7 +12,6 @@
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
@@ -285,7 +284,6 @@
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index 3e4eaf0a3cd98..9641375883bfc 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -11,7 +11,6 @@
; AFTER-PEI-NEXT: dynLDSAlign: 1
; AFTER-PEI-NEXT: isEntryFunction: true
; AFTER-PEI-NEXT: isChainFunction: false
-; AFTER-PEI-NEXT: noSignedZerosFPMath: false
; AFTER-PEI-NEXT: memoryBound: false
; AFTER-PEI-NEXT: waveLimiter: false
; AFTER-PEI-NEXT: hasSpilledSGPRs: true
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
index 2d820102e8706..72387307bb68f 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
@@ -12,7 +12,6 @@
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
index c949a3d94c6a3..43ae1ab5a674e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
@@ -12,7 +12,6 @@
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index 87c3eb626ef0d..16a750b7e530f 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -12,7 +12,6 @@
# FULL-NEXT: dynLDSAlign: 1
# FULL-NEXT: isEntryFunction: true
# FULL-NEXT: isChainFunction: false
-# FULL-NEXT: noSignedZerosFPMath: false
# FULL-NEXT: memoryBound: true
# FULL-NEXT: waveLimiter: true
# FULL-NEXT: hasSpilledSGPRs: false
@@ -96,7 +95,6 @@ machineFunctionInfo:
ldsSize: 2048
gdsSize: 256
isEntryFunction: true
- noSignedZerosFPMath: false
memoryBound: true
waveLimiter: true
scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'
@@ -125,7 +123,6 @@ body: |
# FULL-NEXT: dynLDSAlign: 1
# FULL-NEXT: isEntryFunction: false
# FULL-NEXT: isChainFunction: false
-# FULL-NEXT: noSignedZerosFPMath: false
# FULL-NEXT: memoryBound: false
# FULL-NEXT: waveLimiter: false
# FULL-NEXT: hasSpilledSGPRs: false
@@ -207,7 +204,6 @@ body: |
# FULL-NEXT: dynLDSAlign: 1
# FULL-NEXT: isEntryFunction: false
# FULL-NEXT: isChainFunction: false
-# FULL-NEXT: noSignedZerosFPMath: false
# FULL-NEXT: memoryBound: false
# FULL-NEXT: waveLimiter: false
# FULL-NEXT: hasSpilledSGPRs: false
@@ -290,7 +286,6 @@ body: |
# FULL-NEXT: dynLDSAlign: 1
# FULL-NEXT: isEntryFunction: true
# FULL-NEXT: isChainFunction: false
-# FULL-NEXT: noSignedZerosFPMath: false
# FULL-NEXT: memoryBound: false
# FULL-NEXT: waveLimiter: false
# FULL-NEXT: hasSpilledSGPRs: false
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
index ab3c0335f8ea9..1a17c988c831c 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -15,7 +15,6 @@
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
@@ -78,7 +77,6 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: true
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
@@ -145,7 +143,6 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: false
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: false
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
@@ -204,7 +201,6 @@ define void @function() {
; CHECK-NEXT: dynLDSAlign: 1
; CHECK-NEXT: isEntryFunction: false
; CHECK-NEXT: isChainFunction: false
-; CHECK-NEXT: noSignedZerosFPMath: true
; CHECK-NEXT: memoryBound: false
; CHECK-NEXT: waveLimiter: false
; CHECK-NEXT: hasSpilledSGPRs: false
diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir b/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
index 73e75fc0f7ef5..e97a00e084b08 100644
--- a/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
+++ b/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
@@ -20,7 +20,6 @@
# RESULT-NEXT: gdsSize: 128
# RESULT-NEXT: dynLDSAlign: 16
# RESULT-NEXT: isEntryFunction: true
-# RESULT-NEXT: noSignedZerosFPMath: true
# RESULT-NEXT: memoryBound: true
# RESULT-NEXT: waveLimiter: true
# RESULT-NEXT: hasSpilledSGPRs: true
@@ -74,7 +73,6 @@ machineFunctionInfo:
gdsSize: 128
dynLDSAlign: 16
isEntryFunction: true
- noSignedZerosFPMath: true
memoryBound: true
waveLimiter: true
hasSpilledSGPRs: true
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