[llvm] Marking the undefined sub-registers of a tuple as IMPLICIT_DEF in two address instruction pass (PR #178387)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 28 01:46:06 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Abhinav Garg (abhigargrepo)
<details>
<summary>Changes</summary>
Currently, live interval analysis is unable to track the undefined sub parts of a register tuple which are later used.
This patch will insert IMPLICIT_DEF for undefined sub-registers in two address instruction pass so that live interval analysis can track the liveness of those sub-registers correctly.
Live interval analysis is unable to emit lane masks for undefined sub-registers of a tuple.
Also, with this patch, we found that the assumption made by the register coalescer pass that IMPLICIT_DEF doesn't cause real interference, and can be merged into the value it overlaps doesn't hold true any more. Hence, we have to teach the register coalescer pass not to delete the IMPLICIT_DEF, if it is used to define the sub parts of register tuple.
Fixes [SWDEV-526290]
---
Patch is 8.92 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/178387.diff
337 Files Affected:
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+4-1)
- (modified) llvm/lib/CodeGen/TwoAddressInstructionPass.cpp (+15-1)
- (modified) llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll (+1)
- (modified) llvm/test/CodeGen/AArch64/arm64-dup.ll (+1)
- (modified) llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll (+33-27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll (+110-88)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+26-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll (+5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+72-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll (+30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll (+114-54)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll (+22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll (+31-25)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+33-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+14-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+572-568)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll (+72-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll (+26-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+526-520)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+14-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll (+11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll (+247-238)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll (+11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+6423-5428)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll (+294-58)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll (+402-56)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll (+166-28)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll (+496-70)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll (+1720-64)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll (+350-28)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll (+960-64)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll (+472)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+659-482)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll (+4118-342)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll (+5052-1372)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll (+5077-1905)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll (+5018-2314)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll (+4596-2412)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll (+3948-2248)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll (+3584-2364)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+316-42)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll (+9-1)
- (modified) llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll (+56-16)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll (+74)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+93-29)
- (modified) llvm/test/CodeGen/AMDGPU/bitop3.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/bswap.ll (+16-7)
- (modified) llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll (+142-28)
- (modified) llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll (+15)
- (modified) llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll (+11)
- (modified) llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll (+8)
- (modified) llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (+13-5)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/dead-lane.mir (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll (+21-15)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+3-1)
- (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+135-123)
- (modified) llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll (+144)
- (modified) llvm/test/CodeGen/AMDGPU/extract-subvector.ll (+144)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (+10-6)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll (+113-29)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+81-19)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+98-42)
- (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+8)
- (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fmaximum.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/fmaximum3.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fminimum.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/fminimum3.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+50)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg.bf16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/fpext-free.ll (+21-7)
- (modified) llvm/test/CodeGen/AMDGPU/fptoi.i128.ll (+28-22)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll (+7)
- (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+92)
- (modified) llvm/test/CodeGen/AMDGPU/frem.ll (+90-8)
- (modified) llvm/test/CodeGen/AMDGPU/fshr.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll (+54-26)
- (modified) llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/global-saddr-load.ll (+216-72)
- (modified) llvm/test/CodeGen/AMDGPU/gws_agpr.ll (+10)
- (modified) llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll (+152-149)
- (modified) llvm/test/CodeGen/AMDGPU/idiv-licm.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/idot4s.ll (+13-7)
- (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll (+40)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+129-88)
- (modified) llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/itofp.i128.ll (+127-107)
- (modified) llvm/test/CodeGen/AMDGPU/kernel-args.ll (+5-2)
- (modified) llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll (+7-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll (+67-27)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll (+168-76)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll (+8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll (+29-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll (+24)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll (+314-112)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll (+114-44)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll (+114-44)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll (+46-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll (+82-36)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll (+8-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.frexp.ll (+36)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.round.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+1731-1206)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i16.ll (+745-583)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i8.ll (+893-693)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+143-77)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i8.ll (+810-666)
- (modified) llvm/test/CodeGen/AMDGPU/load-local-i16.ll (+221-64)
- (modified) llvm/test/CodeGen/AMDGPU/lrint.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/lround.ll (+9-4)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll (+59-10)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll (+82-20)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix.ll (+401-113)
- (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+11-4)
- (modified) llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll (+32-11)
- (modified) llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/maximumnum.ll (+137-51)
- (modified) llvm/test/CodeGen/AMDGPU/min.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/minimummaximum.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.ll (+135-51)
- (modified) llvm/test/CodeGen/AMDGPU/minmax.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll (+7-6)
- (modified) llvm/test/CodeGen/AMDGPU/mul_int24.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+56-30)
- (modified) llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/r600-export-fix.ll (+29-29)
- (modified) llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll (+8-3)
- (modified) llvm/test/CodeGen/AMDGPU/repeated-divisor.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll (+11)
- (modified) llvm/test/CodeGen/AMDGPU/roundeven.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/scratch-simple.ll (+564-466)
- (modified) llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll (+48-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll (+95-30)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll (+90-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll (+236-56)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll (+48-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll (+95-30)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll (+90-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll (+236-56)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll (+66-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll (+138-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll (+138-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll (+270-150)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll (+66-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll (+138-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll (+138-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll (+48-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll (+95-30)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll (+90-18)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll (+236-56)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll (+27)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll (+36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll (+51)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll (+27)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll (+36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll (+51)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll (+151-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll (+178-52)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll (+257-60)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll (+27)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll (+36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll (+51)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll (+151-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll (+178-52)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll (+257-60)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll (+158-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll (+225-51)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll (+350-76)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll (+158-36)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll (+225-51)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll (+350-76)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll (+151-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll (+178-52)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll (+257-60)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll (+120-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll (+78-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll (+108-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll (+120-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll (+78-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll (+108-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll (+228-75)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll (+402-132)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll (+484-115)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll (+120-66)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll (+78-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll (+108-6)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll (+228-75)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll (+402-132)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/sign_extend.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll (+9)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll (+6)
- (modified) llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll (+8-5)
- (modified) llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/uaddo.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll (+3)
- (modified) llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll (+25-14)
- (modified) llvm/test/CodeGen/AMDGPU/uniform-select.ll (+4)
- (modified) llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/usubo.ll (+1)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll (+12)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll (+10)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll (+10)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll (+10)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll (+5)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll (+10)
``````````diff
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 527ecca6eab47..6ff8bd6872d8b 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -2876,7 +2876,10 @@ JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
//
// Clearing the valid lanes is deferred until it is sure this can be
// erased.
- V.ErasableImplicitDef = true;
+ // IMPLICIT_DEF can also be used to intialize the undef sub-parts of a tuple
+ // We want to retain those IMPLICIT_DEF.
+ if (DefMI->getOperand(0).getSubReg() == 0)
+ V.ErasableImplicitDef = true;
}
}
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index ff339d4a23915..cc088b20be9ab 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2020,9 +2020,23 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
MachineOperand &UseMO = MI.getOperand(i);
Register SrcReg = UseMO.getReg();
unsigned SubIdx = MI.getOperand(i+1).getImm();
- // Nothing needs to be inserted for undef operands.
+ // Insert IMPLICIT_DEF for undef operands with the corresponding
+ // sub-register.
if (UseMO.isUndef()) {
UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
+ // Insert IMPLICIT_DEF on dst register with the sub-register index.
+ MachineInstr *DefMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
+ TII->get(TargetOpcode::IMPLICIT_DEF))
+ .addReg(DstReg, RegState::Define, SubIdx);
+ // The first def needs an undef flag because there is no live register
+ // before it.
+ if (!DefEmitted) {
+ DefMI->getOperand(0).setIsUndef(true);
+ // Return an iterator pointing to the first inserted instr.
+ MBBI = DefMI;
+ DefEmitted = true;
+ }
+ LLVM_DEBUG(dbgs() << "Inserted: " << *DefMI);
continue;
}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index 99a857027e87d..0435fbd9f8333 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -207,6 +207,7 @@ define void @matrix_mul_double_shuffle(i32 %N, ptr nocapture %C, ptr nocapture r
; CHECK-GI-NEXT: fmov s2, w9
; CHECK-GI-NEXT: mov w9, w0
; CHECK-GI-NEXT: add w0, w0, #8
+; CHECK-GI-NEXT: // implicit-def: $q3
; CHECK-GI-NEXT: lsl x9, x9, #2
; CHECK-GI-NEXT: tbl v2.16b, { v2.16b, v3.16b }, v1.16b
; CHECK-GI-NEXT: mul v2.4s, v0.4s, v2.4s
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 49fb6c98e223f..d93aa7a59e646 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -513,6 +513,7 @@ define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: adrp x8, .LCPI38_1
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI38_1]
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: adrp x8, .LCPI38_0
; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI38_0]
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
index ccd1917ae3d85..b9b33d916a71f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
@@ -406,6 +406,7 @@ define <4 x i32> @test_sabd_knownbits_vec4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]
; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: ret
@@ -437,6 +438,7 @@ define <4 x i32> @knownbits_sabd_and_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI32_0]
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -464,6 +466,7 @@ define <4 x i32> @knownbits_sabd_and_or_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: uabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -501,6 +504,7 @@ define <4 x i32> @knownbits_sabd_and_xor_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -529,6 +533,7 @@ define <4 x i32> @knownbits_sabd_and_shl_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #17
; CHECK-GI-NEXT: shl v1.4s, v1.4s, #17
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
@@ -565,6 +570,7 @@ define <4 x i32> @knownbits_sabd_and_mul_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: mul v1.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI36_0]
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index 5c60eb696f6b2..3208b3b769b85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -86,6 +86,7 @@ define i16 @v_add_i16(i16 %a, i16 %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_add_i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
index 18578c55697cf..885b3444fd38f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
@@ -339,6 +339,8 @@ define amdgpu_ps <3 x i32> @s_and_i96(i96 inreg %num, i96 inreg %den) {
; GCN-NEXT: s_mov_b32 s7, s4
; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]
; GCN-NEXT: s_and_b32 s2, s2, s5
+; GCN-NEXT: ; implicit-def: $sgpr3
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_and_i96:
@@ -347,6 +349,8 @@ define amdgpu_ps <3 x i32> @s_and_i96(i96 inreg %num, i96 inreg %den) {
; GFX10PLUS-NEXT: s_mov_b32 s7, s4
; GFX10PLUS-NEXT: s_and_b32 s2, s2, s5
; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: s_and_i96:
@@ -355,6 +359,8 @@ define amdgpu_ps <3 x i32> @s_and_i96(i96 inreg %num, i96 inreg %den) {
; GFX12-NEXT: s_mov_b32 s7, s4
; GFX12-NEXT: s_and_b32 s2, s2, s5
; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]
+; GFX12-NEXT: ; implicit-def: $sgpr3
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: ; return to shader part epilog
%result = and i96 %num, %den
%cast = bitcast i96 %result to <3 x i32>
@@ -368,6 +374,8 @@ define i96 @v_and_i96(i96 %num, i96 %den) {
; GCN-NEXT: v_and_b32_e32 v0, v0, v3
; GCN-NEXT: v_and_b32_e32 v1, v1, v4
; GCN-NEXT: v_and_b32_e32 v2, v2, v5
+; GCN-NEXT: ; implicit-def: $vgpr6
+; GCN-NEXT: ; implicit-def: $vgpr6
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_and_i96:
@@ -376,6 +384,8 @@ define i96 @v_and_i96(i96 %num, i96 %den) {
; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v3
; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v4
; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v5
+; GFX10PLUS-NEXT: ; implicit-def: $vgpr3
+; GFX10PLUS-NEXT: ; implicit-def: $vgpr3
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_and_i96:
@@ -388,6 +398,8 @@ define i96 @v_and_i96(i96 %num, i96 %den) {
; GFX12-NEXT: v_and_b32_e32 v0, v0, v3
; GFX12-NEXT: v_and_b32_e32 v1, v1, v4
; GFX12-NEXT: v_and_b32_e32 v2, v2, v5
+; GFX12-NEXT: ; implicit-def: $vgpr3
+; GFX12-NEXT: ; implicit-def: $vgpr3
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = and i96 %num, %den
ret i96 %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 6fe6b526a7afe..ecc0de6542656 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -1839,21 +1839,23 @@ define i65 @v_ashr_i65_33(i65 %value) {
define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_ashr_i65:
; GCN: ; %bb.0:
-; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
-; GCN-NEXT: s_sub_i32 s10, s3, 64
-; GCN-NEXT: s_sub_i32 s8, 64, s3
-; GCN-NEXT: s_cmp_lt_u32 s3, 64
+; GCN-NEXT: s_mov_b32 s4, s3
+; GCN-NEXT: ; implicit-def: $sgpr3
+; GCN-NEXT: s_sub_i32 s10, s4, 64
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: s_sub_i32 s8, 64, s4
+; GCN-NEXT: s_cmp_lt_u32 s4, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
-; GCN-NEXT: s_cmp_eq_u32 s3, 0
+; GCN-NEXT: s_cmp_eq_u32 s4, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0
-; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s3
-; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3
-; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
-; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GCN-NEXT: s_ashr_i32 s7, s5, 31
-; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s10
+; GCN-NEXT: s_ashr_i64 s[6:7], s[2:3], s4
+; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
+; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
+; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GCN-NEXT: s_ashr_i32 s7, s3, 31
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], s10
; GCN-NEXT: s_cmp_lg_u32 s11, 0
-; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
@@ -1862,25 +1864,27 @@ define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
;
; GFX10PLUS-LABEL: s_ashr_i65:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
-; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64
-; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3
-; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
+; GFX10PLUS-NEXT: s_mov_b32 s4, s3
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
+; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX10PLUS-NEXT: s_sub_i32 s10, s4, 64
+; GFX10PLUS-NEXT: s_sub_i32 s5, 64, s4
+; GFX10PLUS-NEXT: s_cmp_lt_u32 s4, 64
; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s4, 0
; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
-; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2
-; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[4:5], s3
+; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s4
+; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[2:3], s5
+; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[2:3], s4
; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX10PLUS-NEXT: s_ashr_i32 s3, s5, 31
-; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s10
+; GFX10PLUS-NEXT: s_ashr_i32 s5, s3, 31
+; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], s10
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, s3
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s4, s5
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = ashr i65 %value, %amount
ret i65 %result
@@ -1889,8 +1893,9 @@ define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_ashr_i65_33:
; GCN: ; %bb.0:
-; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_lshr_b32 s4, s1, 1
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GCN-NEXT: s_or_b32 s0, s0, s4
; GCN-NEXT: s_ashr_i32 s2, s3, 1
@@ -1898,8 +1903,9 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
;
; GFX10PLUS-LABEL: s_ashr_i65_33:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
+; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index 57755c6856858..0f02e93014543 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -2,8 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
; GFX7-LABEL: s_bswap_i32:
@@ -31,11 +31,11 @@ define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call i32 @llvm.bswap.i32(i32 %src)
ret i32 %bswap
}
@@ -64,11 +64,11 @@ define i32 @v_bswap_i32(i32 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x10203
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i32 @llvm.bswap.i32(i32 %src)
ret i32 %bswap
}
@@ -109,13 +109,13 @@ define amdgpu_ps <2 x i32> @s_bswap_v2i32(<2 x i32> inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s1, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, s1, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
ret <2 x i32> %bswap
}
@@ -149,12 +149,12 @@ define <2 x i32> @v_bswap_v2i32(<2 x i32> %src) {
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v1, 0x10203
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
ret <2 x i32> %bswap
}
@@ -195,13 +195,13 @@ define amdgpu_ps i64 @s_bswap_i64(i64 inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s0, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call i64 @llvm.bswap.i64(i64 %src)
ret i64 %bswap
}
@@ -238,13 +238,13 @@ define i64 @v_bswap_i64(i64 %src) {
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v2, 0, v1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203
-; GFX10-NEXT: v_mov_b32_e32 v0, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v2, 0, v1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i64 @llvm.bswap.i64(i64 %src)
ret i64 %bswap
}
@@ -305,17 +305,17 @@ define amdgpu_ps <2 x i64> @s_bswap_v2i64(<2 x i64> inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s0, 0x10203
-; GFX10-NEXT: v_perm_b32 v2, 0, s3, 0x10203
-; GFX10-NEXT: v_perm_b32 v3, 0, s2, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/178387
More information about the llvm-commits
mailing list