[lld] [ELF] Simplify RelocScan after #163138 (PR #178375)

Fangrui Song via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 28 00:14:11 PST 2026


https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/178375

None

>From 9cde51beeda6c92ce12b84f5c9cfbd0582f9e38e Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Wed, 28 Jan 2026 00:02:06 -0800
Subject: [PATCH] [ELF] Simplify RelocScan after #163138

---
 lld/ELF/Arch/Mips.cpp  |  5 ++---
 lld/ELF/Arch/PPC64.cpp | 16 +++-------------
 lld/ELF/Arch/RISCV.cpp | 14 ++++----------
 lld/ELF/RelocScan.h    | 13 +++++++++++++
 4 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/lld/ELF/Arch/Mips.cpp b/lld/ELF/Arch/Mips.cpp
index 091903b103ade..ffedf820822e0 100644
--- a/lld/ELF/Arch/Mips.cpp
+++ b/lld/ELF/Arch/Mips.cpp
@@ -632,8 +632,7 @@ void MIPS<ELFT>::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
 
     uint32_t symIdx = rel.getSymbol(ctx.arg.isMips64EL);
     Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
-    RelExpr expr =
-        ctx.target->getRelExpr(type, sym, sec.content().data() + rel.r_offset);
+    RelExpr expr = getRelExpr(type, sym, sec.content().data() + rel.r_offset);
     if (expr == R_NONE)
       continue;
     if (sym.isUndefined() && symIdx != 0 &&
@@ -657,7 +656,7 @@ void MIPS<ELFT>::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
         for (auto *ri = &rel; ri != rels.end(); ++ri) {
           if (ri->getType(ctx.arg.isMips64EL) == pairTy &&
               ri->getSymbol(ctx.arg.isMips64EL) == symIdx) {
-            addend += ctx.target->getImplicitAddend(buf + ri->r_offset, pairTy);
+            addend += getImplicitAddend(buf + ri->r_offset, pairTy);
             found = true;
             break;
           }
diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp
index 6cdccd86bec37..f68048c8f9277 100644
--- a/lld/ELF/Arch/PPC64.cpp
+++ b/lld/ELF/Arch/PPC64.cpp
@@ -181,7 +181,6 @@ class PPC64 final : public TargetInfo {
                  uint64_t pltEntryAddr) const override;
   template <class ELFT, class RelTy>
   void scanSectionImpl(InputSectionBase &, Relocs<RelTy>);
-  template <class ELFT> void scanSection1(InputSectionBase &);
   void scanSection(InputSectionBase &) override;
   void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
@@ -1312,8 +1311,7 @@ void PPC64::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
     uint32_t symIdx = rel.getSymbol(false);
     Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
     RelType type = rel.getType(false);
-    RelExpr expr =
-        ctx.target->getRelExpr(type, sym, sec.content().data() + offset);
+    RelExpr expr = getRelExpr(type, sym, sec.content().data() + offset);
     if (expr == R_NONE)
       continue;
     if (sym.isUndefined() && symIdx != 0 &&
@@ -1373,19 +1371,11 @@ void PPC64::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
   }
 }
 
-template <class ELFT> void PPC64::scanSection1(InputSectionBase &sec) {
-  auto relocs = sec.template relsOrRelas<ELFT>();
-  if (relocs.areRelocsCrel())
-    scanSectionImpl<ELFT>(sec, relocs.crels);
-  else
-    scanSectionImpl<ELFT>(sec, relocs.relas);
-}
-
 void PPC64::scanSection(InputSectionBase &sec) {
   if (ctx.arg.isLE)
-    scanSection1<ELF64LE>(sec);
+    elf::scanSection1<PPC64, ELF64LE>(*this, sec);
   else
-    scanSection1<ELF64BE>(sec);
+    elf::scanSection1<PPC64, ELF64BE>(*this, sec);
 }
 
 void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 7ec75b0d61fce..6e069c7c9d456 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -42,7 +42,6 @@ class RISCV final : public TargetInfo {
                 uint64_t pltEntryAddr) const override;
   template <class ELFT, class RelTy>
   void scanSectionImpl(InputSectionBase &, Relocs<RelTy>);
-  template <class ELFT> void scanSection1(InputSectionBase &);
   void scanSection(InputSectionBase &) override;
   RelType getDynRel(RelType type) const override;
   RelExpr getRelExpr(RelType type, const Symbol &s,
@@ -1537,16 +1536,11 @@ void RISCV::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
                     });
 }
 
-template <class ELFT> void RISCV::scanSection1(InputSectionBase &sec) {
-  const RelsOrRelas<ELFT> rels = sec.template relsOrRelas<ELFT>();
-  if (rels.areRelocsCrel())
-    scanSectionImpl<ELFT>(sec, rels.crels);
-  else
-    scanSectionImpl<ELFT>(sec, rels.relas);
-}
-
 void RISCV::scanSection(InputSectionBase &sec) {
-  invokeELFT(scanSection1, sec);
+  if (ctx.arg.is64)
+    elf::scanSection1<RISCV, ELF64LE>(*this, sec);
+  else
+    elf::scanSection1<RISCV, ELF32LE>(*this, sec);
 }
 
 namespace lld::elf {
diff --git a/lld/ELF/RelocScan.h b/lld/ELF/RelocScan.h
index 43f337d07c42a..01750431b7468 100644
--- a/lld/ELF/RelocScan.h
+++ b/lld/ELF/RelocScan.h
@@ -121,6 +121,19 @@ void RelocScan::scan(typename Relocs<RelTy>::const_iterator &it, RelType type,
 
   process(expr, type, offset, sym, addend);
 }
+
+// Dispatch to target-specific scanSectionImpl based on relocation format.
+template <class Target, class ELFT>
+void scanSection1(Target &target, InputSectionBase &sec) {
+  const RelsOrRelas<ELFT> rels = sec.template relsOrRelas<ELFT>();
+  if (rels.areRelocsCrel())
+    target.template scanSectionImpl<ELFT>(sec, rels.crels);
+  else if (rels.areRelocsRel())
+    target.template scanSectionImpl<ELFT>(sec, rels.rels);
+  else
+    target.template scanSectionImpl<ELFT>(sec, rels.relas);
+}
+
 } // namespace lld::elf
 
 #endif



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