[llvm] [RISCV] Make sure Zvk* and Zvb* predicates are always paired with a GetVTypePredicates<vti>.Predicates. NFC (PR #178269)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 27 19:26:03 PST 2026
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/178269
>From 862ee36c598f4deb1bf8722e7f2c1103fe3726fa Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 27 Jan 2026 08:45:23 -0800
Subject: [PATCH 1/2] [RISCV] Replace VPatBinaryV_VX_VROTATE with
VPatBinaryV_VX. NFC
VPatBinaryV_VX_VROTATE appeared to be almost exact copy and paste
of VPatBinaryV_VX except it used 'XLenVT' instead of 'vti.Scalar'.
'vti.Scalar' is 'XLenVT' for integer vectors so this wasn't a real
difference.
This change allows VV_VX or VV_VX_VI combination classes to be used,
further reducing the code.
No tablegen outputs change with this patch.
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 01ba3a7c27e67..af59dd481ab64 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -1057,16 +1057,9 @@ multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
string instruction2, list<VTypeInfo> vtilist>
- : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
- VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
+ : VPatBinaryV_VV_VX<intrinsic, instruction, vtilist>,
VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;
-multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
- list<VTypeInfo> vtilist>
- : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
- VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
- VPatBinaryV_VI<intrinsic, instruction, vtilist, uimm6>;
-
multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist>
: VPatBinaryW_VV<intrinsic, instruction, vtilist> {
@@ -1106,7 +1099,7 @@ let Predicates = [HasStdExtZvkb] in {
defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;
defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;
- defm : VPatBinaryV_VV_VX_VI_VROR<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
+ defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors, uimm6>;
} // Predicates = [HasStdExtZvkb]
let Predicates = [HasStdExtZvkg] in {
>From ee6ba2ef8b54668d1bb36031d05d4393fc9772f9 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 27 Jan 2026 09:03:58 -0800
Subject: [PATCH 2/2] [RISCV] Make sure Zvk*Zvb* predicates are always paired
with a GetVTypePredicates<vti>.Predicates. NFC
We were inconsistent about this. Being consistent reduces the
number of unique predicate checks in the generated file.
NFC because illegal types don't make it to isel.
Stacked on #178254
---
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 42 +++--
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 150 +++++++++---------
2 files changed, 101 insertions(+), 91 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 8d13aed7ba096..8aff5b3c62f6d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4567,9 +4567,10 @@ multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
}
multiclass VPatUnaryV_V<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, bit isSEWAware = 0> {
+ list<VTypeInfo> vtilist, bit isSEWAware = 0,
+ list<Predicate> ExtraPreds = []> {
foreach vti = vtilist in {
- let Predicates = GetVTypePredicates<vti>.Predicates in {
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in {
def : VPatUnaryNoMask<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
@@ -4813,9 +4814,10 @@ multiclass VPatConversionRTZ<string intrinsic,
}
multiclass VPatBinaryV_VV<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, bit isSEWAware = 0> {
+ list<VTypeInfo> vtilist, bit isSEWAware = 0,
+ list<Predicate> ExtraPreds = []> {
foreach vti = vtilist in
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
defm : VPatBinary<intrinsic,
!if(isSEWAware,
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
@@ -4874,10 +4876,11 @@ multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VX<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, bit isSEWAware = 0> {
+ list<VTypeInfo> vtilist, bit isSEWAware = 0,
+ list<Predicate> ExtraPreds = []> {
foreach vti = vtilist in {
defvar kind = "V"#vti.ScalarSuffix;
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
defm : VPatBinary<intrinsic,
!if(isSEWAware,
instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
@@ -4916,9 +4919,10 @@ multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VI<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, Operand imm_type> {
+ list<VTypeInfo> vtilist, Operand imm_type,
+ list<Predicate> ExtraPreds = []> {
foreach vti = vtilist in
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,
vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.RegClass,
@@ -4958,11 +4962,13 @@ multiclass VPatBinaryM_MM<string intrinsic, string instruction> {
}
multiclass VPatBinaryW_VV<string intrinsic, string instruction,
- list<VTypeInfoToWide> vtilist> {
+ list<VTypeInfoToWide> vtilist,
+ list<Predicate> ExtraPreds = []> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
+ let Predicates = !listconcat(ExtraPreds,
+ GetVTypePredicates<Vti>.Predicates,
GetVTypePredicates<Wti>.Predicates) in
defm : VPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX,
Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,
@@ -5342,10 +5348,11 @@ multiclass VPatBinaryM_VI<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, Operand ImmType = simm5>
- : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
- VPatBinaryV_VX<intrinsic, instruction, vtilist>,
- VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
+ list<VTypeInfo> vtilist, Operand ImmType = simm5,
+ list<Predicate> ExtraPreds = []>
+ : VPatBinaryV_VV<intrinsic, instruction, vtilist, ExtraPreds=ExtraPreds>,
+ VPatBinaryV_VX<intrinsic, instruction, vtilist, ExtraPreds=ExtraPreds>,
+ VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType, ExtraPreds=ExtraPreds>;
multiclass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType>
@@ -5354,9 +5361,10 @@ multiclass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,
VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;
multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, bit isSEWAware = 0>
- : VPatBinaryV_VV<intrinsic, instruction, vtilist, isSEWAware>,
- VPatBinaryV_VX<intrinsic, instruction, vtilist, isSEWAware>;
+ list<VTypeInfo> vtilist, bit isSEWAware = 0,
+ list<Predicate> ExtraPreds = []>
+ : VPatBinaryV_VV<intrinsic, instruction, vtilist, isSEWAware, ExtraPreds>,
+ VPatBinaryV_VX<intrinsic, instruction, vtilist, isSEWAware, ExtraPreds>;
multiclass VPatBinaryV_VV_VX_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist, bit isSEWAware = 0>
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index af59dd481ab64..93c4615b8d361 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -945,32 +945,42 @@ class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,
GPR:$vl, sew, (XLenVT timm:$policy))>;
multiclass VPatUnaryV_V_NoMask_Zvk<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds> {
foreach vti = vtilist in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : VPatUnaryNoMask_Zvk<intrinsic # "_vv", instruction, "VV",
- vti.Vector, vti.Vector, vti.Log2SEW,
- vti.LMul, vti.RegClass, vti.RegClass>;
+ vti.Vector, vti.Vector, vti.Log2SEW,
+ vti.LMul, vti.RegClass, vti.RegClass>;
}
multiclass VPatUnaryV_S_NoMaskVectorCrypto<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds> {
foreach vti = vtilist in
foreach vti_vs2 = ZvkI32IntegerVectors<vti.LMul.MX>.vs2_types in
+ let Predicates = !listconcat(ExtraPreds,
+ GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<vti_vs2>.Predicates) in
def : VPatUnaryNoMask_VS_Zvk<intrinsic # "_vs", instruction, "VS",
vti.Vector, vti_vs2.Vector, vti.Log2SEW,
vti.LMul, vti_vs2.LMul, vti.RegClass, vti_vs2.RegClass>;
}
multiclass VPatUnaryV_V_S_NoMask_Zvk<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
- defm : VPatUnaryV_V_NoMask_Zvk<intrinsic, instruction, vtilist>;
- defm : VPatUnaryV_S_NoMaskVectorCrypto<intrinsic, instruction, vtilist>;
+ list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds> {
+ defm : VPatUnaryV_V_NoMask_Zvk<intrinsic, instruction, vtilist, ExtraPreds>;
+ defm : VPatUnaryV_S_NoMaskVectorCrypto<intrinsic, instruction, vtilist,
+ ExtraPreds>;
}
multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,
list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds,
bit isSEWAware = false> {
foreach vti = vtilist in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass,
@@ -980,8 +990,10 @@ multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,
multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,
list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds,
Operand imm_type = tuimm5> {
foreach vti = vtilist in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT,
vti.Log2SEW, vti.LMul, vti.RegClass,
@@ -990,16 +1002,20 @@ multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,
multiclass VPatBinaryV_VI_NoMaskTU<string intrinsic, string instruction,
list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds,
Operand imm_type = tuimm5> {
foreach vti = vtilist in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VI_" # vti.LMul.MX,
vti.Vector, vti.Vector, XLenVT, vti.Log2SEW,
vti.RegClass, vti.RegClass, imm_type>;
}
multiclass VPatBinaryV_VV_NoMaskTU<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds> {
foreach vti = vtilist in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VV_" # vti.LMul.MX,
vti.Vector, vti.Vector, vti.Vector, vti.Log2SEW,
vti.RegClass, vti.RegClass, vti.RegClass>;
@@ -1021,13 +1037,14 @@ multiclass VPatBinaryV_VX_VROTATE<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, bit isSEWAware = 0> {
+ list<VTypeInfo> vtilist, bit isSEWAware = 0,
+ list<Predicate> ExtraPreds = []> {
foreach vti = vtilist in {
defvar Intr = !cast<Intrinsic>(intrinsic);
defvar Pseudo = !cast<Instruction>(
!if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW,
instruction#"_VI_"#vti.LMul.MX));
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : Pat<(vti.Vector (Intr (vti.Vector vti.RegClass:$passthru),
(vti.Vector vti.RegClass:$rs2),
(XLenVT uimm6:$rs1),
@@ -1041,7 +1058,7 @@ multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
defvar PseudoMask = !cast<Instruction>(
!if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK",
instruction#"_VI_"#vti.LMul.MX#"_MASK"));
- let Predicates = GetVTypePredicates<vti>.Predicates in
+ let Predicates = !listconcat(ExtraPreds, GetVTypePredicates<vti>.Predicates) in
def : Pat<(vti.Vector (IntrMask (vti.Vector vti.RegClass:$passthru),
(vti.Vector vti.RegClass:$rs2),
(XLenVT uimm6:$rs1),
@@ -1056,18 +1073,21 @@ multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
- string instruction2, list<VTypeInfo> vtilist>
- : VPatBinaryV_VV_VX<intrinsic, instruction, vtilist>,
- VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;
+ string instruction2, list<VTypeInfo> vtilist,
+ list<Predicate> ExtraPreds>
+ : VPatBinaryV_VV_VX<intrinsic, instruction, vtilist, ExtraPreds=ExtraPreds>,
+ VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist, ExtraPreds=ExtraPreds>;
multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
- list<VTypeInfoToWide> vtilist>
- : VPatBinaryW_VV<intrinsic, instruction, vtilist> {
+ list<VTypeInfoToWide> vtilist,
+ list<Predicate> ExtraPreds>
+ : VPatBinaryW_VV<intrinsic, instruction, vtilist, ExtraPreds=ExtraPreds> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti;
defvar kind = "V"#Vti.ScalarSuffix;
- let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
+ let Predicates = !listconcat(ExtraPreds,
+ GetVTypePredicates<Vti>.Predicates,
GetVTypePredicates<Wti>.Predicates) in {
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
@@ -1081,60 +1101,42 @@ multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
}
}
-let Predicates = [HasStdExtZvbb] in {
- defm : VPatUnaryV_V<"int_riscv_vbrev", "PseudoVBREV", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vclz", "PseudoVCLZ", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vctz", "PseudoVCTZ", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vcpopv", "PseudoVCPOP", AllIntegerVectors>;
- defm : VPatBinaryW_VV_VX_VI_VWSLL<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors>;
-} // Predicates = [HasStdExtZvbb]
-
-let Predicates = [HasStdExtZvbc] in {
- defm : VPatBinaryV_VV_VX<"int_riscv_vclmul", "PseudoVCLMUL", I64IntegerVectors>;
- defm : VPatBinaryV_VV_VX<"int_riscv_vclmulh", "PseudoVCLMULH", I64IntegerVectors>;
-} // Predicates = [HasStdExtZvbc]
-
-let Predicates = [HasStdExtZvkb] in {
- defm : VPatBinaryV_VV_VX<"int_riscv_vandn", "PseudoVANDN", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;
- defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;
- defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;
- defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors, uimm6>;
-} // Predicates = [HasStdExtZvkb]
-
-let Predicates = [HasStdExtZvkg] in {
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vghsh", "PseudoVGHSH", I32IntegerVectors>;
- defm : VPatUnaryV_V_NoMask_Zvk<"int_riscv_vgmul", "PseudoVGMUL", I32IntegerVectors>;
-} // Predicates = [HasStdExtZvkg]
-
-let Predicates = [HasStdExtZvkned] in {
- defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdf", "PseudoVAESDF", I32IntegerVectors>;
- defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdm", "PseudoVAESDM", I32IntegerVectors>;
- defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesef", "PseudoVAESEF", I32IntegerVectors>;
- defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesem", "PseudoVAESEM", I32IntegerVectors>;
- defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vaeskf1", "PseudoVAESKF1", I32IntegerVectors>;
- defm : VPatBinaryV_VI_NoMask<"int_riscv_vaeskf2", "PseudoVAESKF2", I32IntegerVectors>;
- defm : VPatUnaryV_S_NoMaskVectorCrypto<"int_riscv_vaesz", "PseudoVAESZ", I32IntegerVectors>;
-} // Predicates = [HasStdExtZvkned]
-
-let Predicates = [HasStdExtZvknhaOrZvknhb] in {
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors>;
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors>;
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, isSEWAware=true>;
-} // Predicates = [HasStdExtZvknha]
-
-let Predicates = [HasStdExtZvknhb] in {
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I64IntegerVectors>;
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I64IntegerVectors>;
- defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I64IntegerVectors, isSEWAware=true>;
-} // Predicates = [HasStdExtZvknhb]
-
-let Predicates = [HasStdExtZvksed] in {
- defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vsm4k", "PseudoVSM4K", I32IntegerVectors>;
- defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vsm4r", "PseudoVSM4R", I32IntegerVectors>;
-} // Predicates = [HasStdExtZvksed]
-
-let Predicates = [HasStdExtZvksh] in {
- defm : VPatBinaryV_VI_NoMask<"int_riscv_vsm3c", "PseudoVSM3C", I32IntegerVectors>;
- defm : VPatBinaryV_VV_NoMaskTU<"int_riscv_vsm3me", "PseudoVSM3ME", I32IntegerVectors>;
-} // Predicates = [HasStdExtZvksh]
+defm : VPatUnaryV_V<"int_riscv_vbrev", "PseudoVBREV", AllIntegerVectors, ExtraPreds=[HasStdExtZvbb]>;
+defm : VPatUnaryV_V<"int_riscv_vclz", "PseudoVCLZ", AllIntegerVectors, ExtraPreds=[HasStdExtZvbb]>;
+defm : VPatUnaryV_V<"int_riscv_vctz", "PseudoVCTZ", AllIntegerVectors, ExtraPreds=[HasStdExtZvbb]>;
+defm : VPatUnaryV_V<"int_riscv_vcpopv", "PseudoVCPOP", AllIntegerVectors, ExtraPreds=[HasStdExtZvbb]>;
+defm : VPatBinaryW_VV_VX_VI_VWSLL<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors, [HasStdExtZvbb]>;
+
+defm : VPatBinaryV_VV_VX<"int_riscv_vclmul", "PseudoVCLMUL", I64IntegerVectors, ExtraPreds=[HasStdExtZvbc]>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vclmulh", "PseudoVCLMULH", I64IntegerVectors, ExtraPreds=[HasStdExtZvbc]>;
+
+defm : VPatBinaryV_VV_VX<"int_riscv_vandn", "PseudoVANDN", AllIntegerVectors, ExtraPreds=[HasStdExtZvkb]>;
+defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors, ExtraPreds=[HasStdExtZvkb]>;
+defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors, ExtraPreds=[HasStdExtZvkb]>;
+defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors, [HasStdExtZvkb]>;
+defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors, uimm6, ExtraPreds=[HasStdExtZvkb]>;
+
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vghsh", "PseudoVGHSH", I32IntegerVectors, [HasStdExtZvkg]>;
+defm : VPatUnaryV_V_NoMask_Zvk<"int_riscv_vgmul", "PseudoVGMUL", I32IntegerVectors, [HasStdExtZvkg]>;
+
+defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdf", "PseudoVAESDF", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdm", "PseudoVAESDM", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesef", "PseudoVAESEF", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesem", "PseudoVAESEM", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vaeskf1", "PseudoVAESKF1", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatBinaryV_VI_NoMask<"int_riscv_vaeskf2", "PseudoVAESKF2", I32IntegerVectors, [HasStdExtZvkned]>;
+defm : VPatUnaryV_S_NoMaskVectorCrypto<"int_riscv_vaesz", "PseudoVAESZ", I32IntegerVectors, [HasStdExtZvkned] >;
+
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb]>;
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb]>;
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb], isSEWAware=true>;
+
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I64IntegerVectors, [HasStdExtZvknhb]>;
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I64IntegerVectors, [HasStdExtZvknhb]>;
+defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I64IntegerVectors, [HasStdExtZvknhb], isSEWAware=true>;
+
+defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vsm4k", "PseudoVSM4K", I32IntegerVectors, ExtraPreds=[HasStdExtZvksed]>;
+defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vsm4r", "PseudoVSM4R", I32IntegerVectors, [HasStdExtZvksed]>;
+
+defm : VPatBinaryV_VI_NoMask<"int_riscv_vsm3c", "PseudoVSM3C", I32IntegerVectors, [HasStdExtZvksh]>;
+defm : VPatBinaryV_VV_NoMaskTU<"int_riscv_vsm3me", "PseudoVSM3ME", I32IntegerVectors, [HasStdExtZvksh]>;
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