[llvm] 115d170 - [RISCV] Make RVInstIVI_VROR inherit from RVInstVBase. NFC (#178293)

[via llvm-commits]

Author: Craig Topper
Date: 2026-01-27T19:02:53-08:00
New Revision: 115d170e3e6022c35c1cc70a9f13d40a00c91161

URL: https://github.com/llvm/llvm-project/commit/115d170e3e6022c35c1cc70a9f13d40a00c91161
DIFF: https://github.com/llvm/llvm-project/commit/115d170e3e6022c35c1cc70a9f13d40a00c91161.diff

LOG: [RISCV] Make RVInstIVI_VROR inherit from RVInstVBase. NFC (#178293)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index af59dd481ab64..a0c0666f51c34 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -31,23 +31,15 @@ multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
 
 class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
                      string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInstVBase<funct6, OPIVI, outs, ins, opcodestr, argstr> {
   bits<5> vs2;
   bits<6> imm;
-  bits<5> vd;
-  bit vm;
 
-  let Inst{31-27} = funct6{5-1};
+  // This overwrites the lsb of funct6 in the RVInstVBase base class with imm{5}
+  assert !eq(funct6{0}, 0), "funct6 LSB should be zero";
   let Inst{26} = imm{5};
-  let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm{4-0};
-  let Inst{14-12} = OPIVI.Value;
-  let Inst{11-7} = vd;
-  let Inst{6-0} = OPC_OP_V.Value;
-
-  let Uses = [VL, VTYPE];
-  let RVVConstraint = VMConstraint;
 }
 
 multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>