[llvm] 9ec6a12 - [RISCV] Replace VPatBinaryV_VX_VROTATE with VPatBinaryV_VX. NFC (#178254)

[via llvm-commits]

Author: Craig Topper
Date: 2026-01-27T11:06:01-08:00
New Revision: 9ec6a12dda5061db1b4a190881c152fb3bd0d1d6

URL: https://github.com/llvm/llvm-project/commit/9ec6a12dda5061db1b4a190881c152fb3bd0d1d6
DIFF: https://github.com/llvm/llvm-project/commit/9ec6a12dda5061db1b4a190881c152fb3bd0d1d6.diff

LOG: [RISCV] Replace VPatBinaryV_VX_VROTATE with VPatBinaryV_VX. NFC (#178254)

VPatBinaryV_VX_VROTATE appeared to be almost exact copy and paste of
VPatBinaryV_VX except it used 'XLenVT' instead of 'vti.Scalar'.
'vti.Scalar' is 'XLenVT' for integer vectors so this wasn't a real
difference.

This change allows VV_VX or VV_VX_VI combination classes to be used,
further reducing the code.

No tablegen outputs change with this patch.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 01ba3a7c27e67..af59dd481ab64 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -1057,16 +1057,9 @@ multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
 
 multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
                                   string instruction2, list<VTypeInfo> vtilist>
-    : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
-      VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
+    : VPatBinaryV_VV_VX<intrinsic, instruction, vtilist>,
       VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;
 
-multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
-                                     list<VTypeInfo> vtilist>
-    : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
-      VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
-      VPatBinaryV_VI<intrinsic, instruction, vtilist, uimm6>;
-
 multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
                                       list<VTypeInfoToWide> vtilist>
     : VPatBinaryW_VV<intrinsic, instruction, vtilist> {
@@ -1106,7 +1099,7 @@ let Predicates = [HasStdExtZvkb] in {
   defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;
   defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;
   defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;
-  defm : VPatBinaryV_VV_VX_VI_VROR<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
+  defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors, uimm6>;
 } // Predicates = [HasStdExtZvkb]
 
 let Predicates = [HasStdExtZvkg] in {