[llvm] [AMDGPU] Add DPP16 Row Share optimization for llvm.amdgcn.wave.shuffle (PR #177470)

[via llvm-commits]

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@@ -1759,6 +1856,12 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
     NewII->copyMetadata(II);
     return IC.eraseInstFromFunction(II);
   }
+  case Intrinsic::amdgcn_wave_shuffle: {
+    if (!ST->hasDPP())
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saxlungs wrote:

The goal was to just check for dpp usability before going into the helper function. In the helper function, I've wrapped all of the row_share checks inside a check for GFX10 or later

https://github.com/llvm/llvm-project/pull/177470