[llvm] [AMDGPU] Add DPP16 Row Share optimization for llvm.amdgcn.wave.shuffle (PR #177470)

[via llvm-commits]

================
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -passes=instcombine -S < %s | FileCheck -check-prefixes=CHECK-W32 %s
+; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck -check-prefixes=CHECK-W64 %s
+
+define i32 @test_wave_shuffle_self_select(i32 %val) {
+; CHECK-W32-LABEL: define i32 @test_wave_shuffle_self_select(
+; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-W32-NEXT:    [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
+; CHECK-W32-NEXT:    [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[TID]])
+; CHECK-W32-NEXT:    ret i32 [[RES]]
+;
+; CHECK-W64-LABEL: define i32 @test_wave_shuffle_self_select(
+; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-W64-NEXT:    [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
+; CHECK-W64-NEXT:    [[TID1:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[TID]])
+; CHECK-W64-NEXT:    [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[TID1]])
+; CHECK-W64-NEXT:    ret i32 [[RES]]
+;
+  %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
+  %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
+  %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %tid)
+  ret i32 %res
+}
+
+define i32 @test_wave_shuffle_dpp_row_share_0(i32 %val) {
+; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0(
+; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] {
+; CHECK-W32-NEXT:    [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 [[VAL]], i32 272, i32 15, i32 15, i1 false)
+; CHECK-W32-NEXT:    ret i32 [[RES]]
+;
+; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0(
+; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] {
+; CHECK-W64-NEXT:    [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 [[VAL]], i32 272, i32 15, i32 15, i1 false)
+; CHECK-W64-NEXT:    ret i32 [[RES]]
+;
+  %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
+  %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
+  %masked = and i32 %tid, 65520   ; 0xFFF0
+  %share_0 = or i32 %masked, 0
----------------
saxlungs wrote:

Yes. I believe the `or` only gets optimized out in the DPP_ROW_SHR_0 case, which we don't match against an `or` in that case

https://github.com/llvm/llvm-project/pull/177470