[llvm] [VPlan] Fix register usage of VPExpressionRecipe (PR #176971)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

> For the function dotp_unrolled in reg-usage.ll the code we generate (using -force-vector-width=16 -force-vector-interleave=1 so we select VF 16 with no interleaving) is

What is the VPlan for the test case? The result should only have a scale factor, if we formed a partial reduction, and in that case, all recipes in the expression should be folded into the partial reduction IIRC.

But from the assembly, it looks like we don't create a partial reduction. is it possible that we incorrectly formed a VPExpression recipe for a dot product that we then cannot lower to a dot product?

https://github.com/llvm/llvm-project/pull/176971