[llvm] [RISCV] Add SpacemiT X100 base scheduling model (PR #178189)

[Olaf Bernstein via llvm-commits]

camel-cdr wrote:

[When I tried to measure scalar instruction thoughput](https://camel-cdr.github.io/rvv-bench-results/spacemit_x100/index.html), I got 3 IALU per cycle (add/sub/xor, but also the bitmanip instructions), which is different to the 2 per cycle in the scheduling model.

Is it possible that the X100 fuses things like `add t0, t1, t2; add t0, t1, t2` and has a 3 wide decode?



https://github.com/llvm/llvm-project/pull/178189