[llvm] [AMDGPU] Fix iterator type in fixVALUMaskWriteHazard for bundled instr (PR #178195)

[Dmitry Sidorov via llvm-commits]

https://github.com/MrSidims created https://github.com/llvm/llvm-project/pull/178195

Use reverse_instr_iterator instead of reverse_iterator when iterating backwards from MI to find wait instructions. Otherwise if we start from somewhere in the middle of the block we fail with assertion.

Fixes: https://github.com/llvm/llvm-project/issues/172331

>From b3b9dff6f1436728f41af1da69676bdd65fd0702 Mon Sep 17 00:00:00 2001
From: Dmitry Sidorov <dmitrii.s.sidorov at gmail.com>
Date: Sat, 24 Jan 2026 02:42:00 +0100
Subject: [PATCH] [AMDGPU] Fix iterator type in fixVALUMaskWriteHazard for
 bundled instructions

Use reverse_instr_iterator instead of reverse_iterator when iterating
backwards from MI to find wait instructions. Otherwise if we start from
somewhere in the middle of the block we fail with assertion.

Fixes: https://github.com/llvm/llvm-project/issues/172331
---
 .../lib/Target/AMDGPU/GCNHazardRecognizer.cpp |  5 +++--
 .../valu-mask-write-hazard-getpc-bundle.ll    | 22 +++++++++++++++++++
 2 files changed, 25 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-getpc-bundle.ll

diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index d504d8618b90d..47ff6018b05ef 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -3498,8 +3498,9 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
     // This is expected to be a very short walk within the same block.
     SmallVector<MachineInstr *> ToErase;
     unsigned Found = 0;
-    for (MachineBasicBlock::reverse_iterator It = MI->getReverseIterator(),
-                                             End = MI->getParent()->rend();
+    for (MachineBasicBlock::reverse_instr_iterator
+             It = MI->getReverseIterator(),
+             End = MI->getParent()->instr_rend();
          Found < WaitInstrs.size() && It != End; ++It) {
       MachineInstr *WaitMI = &*It;
       // Find next wait instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-getpc-bundle.ll b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-getpc-bundle.ll
new file mode 100644
index 0000000000000..2dcd6695c65a1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-getpc-bundle.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck %s
+;
+; This test validates that the VALU mask write hazard pass correctly handles
+; bundled instructions.
+
+; CHECK-LABEL: main:
+; CHECK: s_getpc_b64
+; CHECK: s_waitcnt_depctr
+
+define amdgpu_cs i32 @main(i32 %arg, i32 %arg1) {
+bb:
+  %i = udiv i32 %arg, %arg1
+  %i2 = uitofp i32 %i to float
+  %i3 = udiv i32 1, %arg
+  %i4 = uitofp i32 %i3 to float
+  %i5 = call float @llvm.fma.f32(float %i2, float 0.000000e+00, float %i4)
+  %i6 = fptosi float %i5 to i32
+  %i7 = call i32 @func(i32 0, i32 %i6)
+  ret i32 %i7
+}
+
+declare i32 @func(i32, i32)