[llvm] [AMDGPU] Add folding ISD::SELECT from vXiY into vZi32 with X * Y = Z * 32 (PR #173328)

[Simon Pilgrim via llvm-commits]

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@@ -6976,6 +6976,35 @@ static SDValue combineSelectAsExtAnd(SDValue Cond, SDValue T, SDValue F,
   return DAG.getNode(ISD::AND, DL, OpVT, CondMask, T.getOperand(0));
 }
 
+// Try to convert vXiY into vZi32 with X * Y = Z * 32
+// This prevent promotion of integer vectors like v32i4 to v32i16
+// which can create extra operations on type casting.
+static SDValue castTypeSelect(SDNode *N, SelectionDAG &DAG,
+                              const TargetLowering &TLI, SDValue Cond,
+                              SDValue TrueVal, SDValue FalseVal) {
+  EVT ResultVT = N->getValueType(0);
+  if (ResultVT.isSimple() || !ResultVT.isVector() ||
+      !ResultVT.isPow2VectorType() ||
+      TLI.getTypeAction(*DAG.getContext(), ResultVT) !=
+          TargetLowering::TypePromoteInteger)
+    return SDValue();
+
+  EVT EltVT = ResultVT.getVectorElementType();
+  if (!EltVT.isInteger() || ResultVT.getVectorElementCount().isScalar())
+    return SDValue();
+
+  EVT NewVT = ResultVT.getIntegerVectorWithElementWidth(*DAG.getContext(), 32);
+  if (NewVT == EVT())
+    return SDValue();
+
+  SDValue NewTrue = DAG.getNode(ISD::BITCAST, SDLoc(TrueVal), NewVT, TrueVal);
+  SDValue NewFalse =
+      DAG.getNode(ISD::BITCAST, SDLoc(FalseVal), NewVT, FalseVal);
+  SDValue NewSelect =
+      DAG.getNode(ISD::SELECT, SDLoc(N), NewVT, Cond, NewTrue, NewFalse);
+  return DAG.getNode(ISD::BITCAST, SDLoc(N), ResultVT, NewSelect);
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RKSimon wrote:

DAG.getBitcast

https://github.com/llvm/llvm-project/pull/173328