[llvm] [AMDGPU] Add DPP16 Row Share optimization for llvm.amdgcn.wave.shuffle (PR #177470)

[Brox Chen via llvm-commits]

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@@ -553,6 +553,103 @@ static CallInst *rewriteCall(IRBuilderBase &B, CallInst &Old,
   return NewCall;
 }
 
+// Return true for sequences of instructions that effectively assign
+// each lane to its thread ID
+bool isThreadID(const GCNSubtarget *ST, Value *V) {
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broxigarchen wrote:

should be static if only used in this file

https://github.com/llvm/llvm-project/pull/177470