[llvm] [SDAG] Remove non-canonical fabs libcall handling (PR #177967)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 26 06:43:39 PST 2026
https://github.com/nikic created https://github.com/llvm/llvm-project/pull/177967
This is a followup to https://github.com/llvm/llvm-project/pull/171288, which removed lowering of libcalls to SDAG nodes for most libcalls that get unconditionally canonicalized to intrinsics. This handles the remaining fabs case, which I originally skipped due to larger test impact.
>From cdbadd2365c303e6a482fbd85d2c66cb463f97aa Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Mon, 26 Jan 2026 15:27:15 +0100
Subject: [PATCH] [SDAG] Remove non-canonical fabs libcall handling
---
.../SelectionDAG/SelectionDAGBuilder.cpp | 7 ---
llvm/test/CodeGen/AArch64/floatdp_1source.ll | 8 +--
llvm/test/CodeGen/AMDGPU/complex-folding.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fabs-r600.ll | 35 -----------
llvm/test/CodeGen/AMDGPU/fabs.f64.ll | 41 -------------
llvm/test/CodeGen/AMDGPU/fabs.ll | 61 -------------------
llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll | 21 -------
llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll | 34 -----------
llvm/test/CodeGen/AMDGPU/fneg-fabs.ll | 32 ----------
...nite-loop-bug-while-reorganizing-vector.ll | 4 +-
llvm/test/CodeGen/AMDGPU/schedule-if-2.ll | 4 +-
llvm/test/CodeGen/ARM/fabs-to-bfc.ll | 4 +-
llvm/test/CodeGen/ARM/fabss.ll | 4 +-
llvm/test/CodeGen/ARM/fparith.ll | 8 +--
llvm/test/CodeGen/ARM/vfp.ll | 8 +--
llvm/test/CodeGen/Hexagon/bit-extract-off.ll | 4 +-
llvm/test/CodeGen/Hexagon/opt-fabs.ll | 6 +-
llvm/test/CodeGen/Mips/f16abs.ll | 8 +--
llvm/test/CodeGen/Mips/fabs.ll | 8 +--
llvm/test/CodeGen/Mips/mips64-f128.ll | 4 +-
llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll | 4 +-
llvm/test/CodeGen/PowerPC/fabs.ll | 2 +-
llvm/test/CodeGen/PowerPC/fnabs.ll | 4 +-
llvm/test/CodeGen/X86/fabs.ll | 8 +--
llvm/test/CodeGen/X86/fnabs.ll | 6 +-
llvm/test/CodeGen/X86/fp128-i128.ll | 6 +-
llvm/test/CodeGen/X86/pr2656.ll | 4 +-
llvm/test/CodeGen/X86/stack-align.ll | 6 +-
28 files changed, 57 insertions(+), 288 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index ff3ed6e6dcb14..63c9d193421ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9608,13 +9608,6 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
return;
}
break;
- case LibFunc_fabs:
- case LibFunc_fabsf:
- case LibFunc_fabsl:
- // TODO: Remove this, already canonicalized by the middle-end.
- if (visitUnaryFloatCall(I, ISD::FABS))
- return;
- break;
case LibFunc_sin:
case LibFunc_sinf:
case LibFunc_sinl:
diff --git a/llvm/test/CodeGen/AArch64/floatdp_1source.ll b/llvm/test/CodeGen/AArch64/floatdp_1source.ll
index 32d73d9e830f8..c3e8362ea2690 100644
--- a/llvm/test/CodeGen/AArch64/floatdp_1source.ll
+++ b/llvm/test/CodeGen/AArch64/floatdp_1source.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-declare float @fabsf(float) readonly
-declare double @fabs(double) readonly
+declare float @llvm.fabs.f32(float) readonly
+declare double @llvm.fabs.f64(double) readonly
declare float @llvm.sqrt.f32(float %Val)
declare double @llvm.sqrt.f64(double %Val)
@@ -12,7 +12,7 @@ define float @fabs_f(float %v) {
; CHECK: ; %bb.0:
; CHECK-NEXT: fabs s0, s0
; CHECK-NEXT: ret
- %r = call float @fabsf(float %v)
+ %r = call float @llvm.fabs.f32(float %v)
ret float %r
}
@@ -84,7 +84,7 @@ define double @fabs_d(double %v) {
; CHECK: ; %bb.0:
; CHECK-NEXT: fabs d0, d0
; CHECK-NEXT: ret
- %r = call double @fabs(double %v)
+ %r = call double @llvm.fabs.f64(double %v)
ret double %r
}
diff --git a/llvm/test/CodeGen/AMDGPU/complex-folding.ll b/llvm/test/CodeGen/AMDGPU/complex-folding.ll
index 3d124e8cb7f4a..2de9ce3e8fcbf 100644
--- a/llvm/test/CodeGen/AMDGPU/complex-folding.ll
+++ b/llvm/test/CodeGen/AMDGPU/complex-folding.ll
@@ -5,7 +5,7 @@
define amdgpu_ps void @main(<4 x float> inreg %reg0) {
entry:
%0 = extractelement <4 x float> %reg0, i32 0
- %1 = call float @fabsf(float %0)
+ %1 = call float @llvm.fabs.f32(float %0)
%2 = fptoui float %1 to i32
%3 = bitcast i32 %2 to float
%4 = insertelement <4 x float> poison, float %3, i32 0
@@ -13,5 +13,5 @@ entry:
ret void
}
-declare float @fabsf(float ) readnone
+declare float @llvm.fabs.f32(float ) readnone
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/fabs-r600.ll b/llvm/test/CodeGen/AMDGPU/fabs-r600.ll
index 7e1aa99c3ec40..5e22d5f792c18 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs-r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs-r600.ll
@@ -5,24 +5,6 @@
; DAGCombiner will transform:
; (fabsf (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
; unless isFabsFree returns true
-define amdgpu_kernel void @s_fabsf_fn_free(ptr addrspace(1) %out, i32 %in) {
-; R600-LABEL: s_fabsf_fn_free:
-; R600: ; %bb.0:
-; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: MOV * T0.W, KC0[2].Z,
-; R600-NEXT: MOV T0.X, |PV.W|,
-; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
- %bc= bitcast i32 %in to float
- %fabs = call float @fabsf(float %bc)
- store float %fabs, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @s_fabsf_free(ptr addrspace(1) %out, i32 %in) {
; R600-LABEL: s_fabsf_free:
; R600: ; %bb.0:
@@ -100,23 +82,6 @@ define amdgpu_kernel void @fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
ret void
}
-define amdgpu_kernel void @fabsf_fn_fold(ptr addrspace(1) %out, float %in0, float %in1) {
-; R600-LABEL: fabsf_fn_fold:
-; R600: ; %bb.0:
-; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
-; R600-NEXT: MUL_IEEE * T1.X, |KC0[2].Z|, KC0[2].W,
-; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
- %fabs = call float @fabsf(float %in0)
- %fmul = fmul float %fabs, %in1
- store float %fmul, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fabs_fold(ptr addrspace(1) %out, float %in0, float %in1) {
; R600-LABEL: fabs_fold:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f64.ll b/llvm/test/CodeGen/AMDGPU/fabs.f64.ll
index 5d45f6723a8d1..e845cfdc37295 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.f64.ll
@@ -3,7 +3,6 @@
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
-declare double @fabs(double) readnone
declare double @llvm.fabs.f64(double) readnone
declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
@@ -124,26 +123,6 @@ define amdgpu_kernel void @fabs_fold_f64(ptr addrspace(1) %out, [8 x i32], doubl
ret void
}
-define amdgpu_kernel void @fabs_fn_fold_f64(ptr addrspace(1) %out, [8 x i32], double %in0, [8 x i32], double %in1) {
-; SI-LABEL: fabs_fn_fold_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x1d
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x13
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: v_mul_f64 v[0:1], |s[8:9]|, v[0:1]
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
- %fabs = call double @fabs(double %in0)
- %fmul = fmul double %fabs, %in1
- store double %fmul, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fabs_free_f64(ptr addrspace(1) %out, i64 %in) {
; SI-LABEL: fabs_free_f64:
; SI: ; %bb.0:
@@ -163,23 +142,3 @@ define amdgpu_kernel void @fabs_free_f64(ptr addrspace(1) %out, i64 %in) {
store double %fabs, ptr addrspace(1) %out
ret void
}
-
-define amdgpu_kernel void @fabs_fn_free_f64(ptr addrspace(1) %out, i64 %in) {
-; SI-LABEL: fabs_fn_free_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset0_b32 s3, 31
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_mov_b32_e32 v0, s2
-; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-NEXT: s_endpgm
- %bc= bitcast i64 %in to double
- %fabs = call double @fabs(double %bc)
- store double %fabs, ptr addrspace(1) %out
- ret void
-}
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.ll b/llvm/test/CodeGen/AMDGPU/fabs.ll
index 97e23fcdb2263..fd0b6b4b0c59f 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.ll
@@ -6,36 +6,6 @@
; DAGCombiner will transform:
; (fabsf (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
; unless isFabsFree returns true
-define amdgpu_kernel void @s_fabsf_fn_free(ptr addrspace(1) %out, i32 %in) {
-; SI-LABEL: s_fabsf_fn_free:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_load_dword s4, s[4:5], 0xb
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset0_b32 s4, 31
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_fabsf_fn_free:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
- %bc= bitcast i32 %in to float
- %fabs = call float @fabsf(float %bc)
- store float %fabs, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @s_fabsf_free(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_fabsf_free:
; SI: ; %bb.0:
@@ -168,36 +138,6 @@ define amdgpu_kernel void @fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
ret void
}
-define amdgpu_kernel void @fabsf_fn_fold(ptr addrspace(1) %out, float %in0, float %in1) {
-; SI-LABEL: fabsf_fn_fold:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_mov_b32_e32 v0, s3
-; SI-NEXT: v_mul_f32_e64 v0, |s2|, v0
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: fabsf_fn_fold:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_mul_f32_e64 v2, |s2|, v0
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
- %fabs = call float @fabsf(float %in0)
- %fmul = fmul float %fabs, %in1
- store float %fmul, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fabs_fold(ptr addrspace(1) %out, float %in0, float %in1) {
; SI-LABEL: fabs_fold:
; SI: ; %bb.0:
@@ -258,7 +198,6 @@ define amdgpu_kernel void @bitpreserve_fabsf_f32(ptr addrspace(1) %out, float %i
ret void
}
-declare float @fabsf(float) readnone
declare float @llvm.fabs.f32(float) readnone
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
index caf7a845759fc..dccabf078c3d7 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
@@ -57,26 +57,6 @@ define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
ret void
}
-define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) {
-; R600-LABEL: fneg_fabsf_fn_free_f32:
-; R600: ; %bb.0:
-; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: MOV * T0.W, KC0[2].Z,
-; R600-NEXT: MOV * T0.W, |PV.W|,
-; R600-NEXT: MOV T0.X, -PV.W,
-; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
- %bc = bitcast i32 %in to float
- %fabs = call float @fabsf(float %bc)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {
; R600-LABEL: fneg_fabsf_f32:
; R600: ; %bb.0:
@@ -171,7 +151,6 @@ define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %
ret void
}
-declare float @fabsf(float) readnone
declare float @llvm.fabs.f32(float) readnone
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
index 52b6d2cbaa6eb..65c3917294baf 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
@@ -138,39 +138,6 @@ define amdgpu_kernel void @fneg_fabs_free_f64(ptr addrspace(1) %out, i64 %in) {
ret void
}
-define amdgpu_kernel void @fneg_fabs_fn_free_f64(ptr addrspace(1) %out, i64 %in) {
-; SI-LABEL: fneg_fabs_fn_free_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset1_b32 s3, 31
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_mov_b32_e32 v0, s2
-; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: fneg_fabs_fn_free_f64:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_or_b32 s0, s3, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT: s_endpgm
- %bc = bitcast i64 %in to double
- %fabs = call double @fabs(double %bc)
- %fsub = fsub double -0.000000e+00, %fabs
- store double %fsub, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fneg_fabs_f64(ptr addrspace(1) %out, [8 x i32], double %in) {
; SI-LABEL: fneg_fabs_f64:
; SI: ; %bb.0:
@@ -297,7 +264,6 @@ define amdgpu_kernel void @fneg_fabs_v4f64(ptr addrspace(1) %out, <4 x double> %
ret void
}
-declare double @fabs(double) readnone
declare double @llvm.fabs.f64(double) readnone
declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
index 214ccedd75170..1264ac9096839 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
@@ -95,37 +95,6 @@ define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
ret void
}
-define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) {
-; SI-LABEL: fneg_fabsf_fn_free_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s2, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s2, 0x80000000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: fneg_fabsf_fn_free_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
- %bc = bitcast i32 %in to float
- %fabs = call float @fabsf(float %bc)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: fneg_fabsf_f32:
; SI: ; %bb.0:
@@ -270,7 +239,6 @@ define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %
ret void
}
-declare float @fabsf(float) readnone
declare float @llvm.fabs.f32(float) readnone
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
diff --git a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
index d815c18a289e1..b2a925d8f7c05 100644
--- a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
@@ -15,7 +15,7 @@ main_body:
%tmp11 = extractelement <4 x float> %tmp9, i32 1
%tmp12 = extractelement <4 x float> %tmp9, i32 2
%tmp13 = extractelement <4 x float> %tmp9, i32 3
- %tmp14 = call float @fabsf(float %tmp12)
+ %tmp14 = call float @llvm.fabs.f32(float %tmp12)
%tmp15 = fdiv float 1.000000e+00, %tmp14
%tmp16 = fmul float %tmp10, %tmp15
%tmp17 = fadd float %tmp16, 1.500000e+00
@@ -48,7 +48,7 @@ main_body:
declare <4 x float> @llvm.r600.cube(<4 x float>) #0
; Function Attrs: readnone
-declare float @fabsf(float) #0
+declare float @llvm.fabs.f32(float) #0
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll b/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
index 2baa955ed8d06..089fe2fe1fed7 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
@@ -17,7 +17,7 @@ main_body:
br i1 %10, label %IF, label %ELSE
IF: ; preds = %main_body
- %11 = call float @fabsf(float %2)
+ %11 = call float @llvm.fabs.f32(float %2)
%12 = fcmp ueq float %11, 0x7FF0000000000000
%13 = select i1 %12, float 1.000000e+00, float 0.000000e+00
%14 = fsub float -0.000000e+00, %13
@@ -87,7 +87,7 @@ IF23: ; preds = %ELSE
br label %ENDIF
}
-declare float @fabsf(float) #0
+declare float @llvm.fabs.f32(float) #0
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/fabs-to-bfc.ll b/llvm/test/CodeGen/ARM/fabs-to-bfc.ll
index 1a2e04584a913..8374dd79460e9 100644
--- a/llvm/test/CodeGen/ARM/fabs-to-bfc.ll
+++ b/llvm/test/CodeGen/ARM/fabs-to-bfc.ll
@@ -4,11 +4,11 @@
define double @test(double %tx) {
;CHECK-LABEL: test:
- %call = tail call double @fabs(double %tx)
+ %call = tail call double @llvm.fabs.f64(double %tx)
ret double %call
;CHECK-VABS: vabs.f64
;CHECK-BFC: bfc
}
-declare double @fabs(double) readnone
+declare double @llvm.fabs.f64(double) readnone
diff --git a/llvm/test/CodeGen/ARM/fabss.ll b/llvm/test/CodeGen/ARM/fabss.ll
index 77c21c5be91a7..28415efa138f4 100644
--- a/llvm/test/CodeGen/ARM/fabss.ll
+++ b/llvm/test/CodeGen/ARM/fabss.ll
@@ -6,12 +6,12 @@
define float @test(float %a, float %b) {
entry:
%dum = fadd float %a, %b
- %0 = tail call float @fabsf(float %dum) readnone
+ %0 = tail call float @llvm.fabs.f32(float %dum) readnone
%dum1 = fadd float %0, %b
ret float %dum1
}
-declare float @fabsf(float)
+declare float @llvm.fabs.f32(float)
; VFP2-LABEL: test:
; VFP2: vabs.f32 s
diff --git a/llvm/test/CodeGen/ARM/fparith.ll b/llvm/test/CodeGen/ARM/fparith.ll
index 824824429db17..9382a8871fc22 100644
--- a/llvm/test/CodeGen/ARM/fparith.ll
+++ b/llvm/test/CodeGen/ARM/fparith.ll
@@ -84,18 +84,18 @@ define float @f11(float %a) {
;CHECK-LABEL: f11:
;CHECK: bic
entry:
- %tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
+ %tmp1 = call float @llvm.fabs.f32( float %a ) readnone ; <float> [#uses=1]
ret float %tmp1
}
-declare float @fabsf(float)
+declare float @llvm.fabs.f32(float)
define arm_aapcs_vfpcc double @f12(double %a) {
;CHECK-LABEL: f12:
;CHECK: vabs.f64
entry:
- %tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1]
+ %tmp1 = call double @llvm.fabs.f64( double %a ) readnone ; <double> [#uses=1]
ret double %tmp1
}
-declare double @fabs(double)
+declare double @llvm.fabs.f64(double)
diff --git a/llvm/test/CodeGen/ARM/vfp.ll b/llvm/test/CodeGen/ARM/vfp.ll
index 6f5bfc9aac018..2ba7875a070dc 100644
--- a/llvm/test/CodeGen/ARM/vfp.ll
+++ b/llvm/test/CodeGen/ARM/vfp.ll
@@ -9,19 +9,19 @@ define void @test(ptr %P, ptr %D) {
ret void
}
-declare float @fabsf(float)
+declare float @llvm.fabs.f32(float)
-declare double @fabs(double)
+declare double @llvm.fabs.f64(double)
define void @test_abs(ptr %P, ptr %D) {
;CHECK-LABEL: test_abs:
%a = load float, ptr %P ; <float> [#uses=1]
;CHECK: vabs.f32
- %b = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
+ %b = call float @llvm.fabs.f32( float %a ) readnone ; <float> [#uses=1]
store float %b, ptr %P
%A = load double, ptr %D ; <double> [#uses=1]
;CHECK: vabs.f64
- %B = call double @fabs( double %A ) readnone ; <double> [#uses=1]
+ %B = call double @llvm.fabs.f64( double %A ) readnone ; <double> [#uses=1]
store double %B, ptr %D
ret void
}
diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
index 3396779737a42..2c00f52744b09 100644
--- a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
@@ -14,12 +14,12 @@ b4:
br label %b5
b5: ; preds = %b5, %b4
- %v6 = call double @fabs(double undef) #1
+ %v6 = call double @llvm.fabs.f64(double undef) #1
store double %v6, ptr @g0, align 8
br label %b5
}
-declare double @fabs(double) #1
+declare double @llvm.fabs.f64(double) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/CodeGen/Hexagon/opt-fabs.ll b/llvm/test/CodeGen/Hexagon/opt-fabs.ll
index 86974bf84de28..2a70ef7e492fc 100644
--- a/llvm/test/CodeGen/Hexagon/opt-fabs.ll
+++ b/llvm/test/CodeGen/Hexagon/opt-fabs.ll
@@ -3,13 +3,13 @@
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
-define float @my_fabsf(float %x) nounwind {
+define float @my_llvm.fabs.f32(float %x) nounwind {
entry:
%x.addr = alloca float, align 4
store float %x, ptr %x.addr, align 4
%0 = load float, ptr %x.addr, align 4
- %call = call float @fabsf(float %0) readnone
+ %call = call float @llvm.fabs.f32(float %0) readnone
ret float %call
}
-declare float @fabsf(float)
+declare float @llvm.fabs.f32(float)
diff --git a/llvm/test/CodeGen/Mips/f16abs.ll b/llvm/test/CodeGen/Mips/f16abs.ll
index 242d8ff4b2acc..3de0d1d1be268 100644
--- a/llvm/test/CodeGen/Mips/f16abs.ll
+++ b/llvm/test/CodeGen/Mips/f16abs.ll
@@ -12,12 +12,12 @@
define i32 @main() #0 {
entry:
%0 = load double, ptr @y, align 8
- %call = tail call double @fabs(double %0) #2
+ %call = tail call double @llvm.fabs.f64(double %0) #2
store double %call, ptr @x, align 8
; static-NOT: .ent __call_stub_fp_fabs
; static-NOT: jal fabs
%1 = load float, ptr @y1, align 4
- %call2 = tail call float @fabsf(float %1) #2
+ %call2 = tail call float @llvm.fabs.f32(float %1) #2
store float %call2, ptr @x1, align 4
; static-NOT: .ent __call_stub_fp_fabsf
; static-NOT: jal fabsf
@@ -25,9 +25,9 @@ entry:
}
; Function Attrs: nounwind optsize readnone
-declare double @fabs(double) #1
+declare double @llvm.fabs.f64(double) #1
-declare float @fabsf(float) #1
+declare float @llvm.fabs.f32(float) #1
attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" }
attributes #1 = { nounwind optsize readnone "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" }
diff --git a/llvm/test/CodeGen/Mips/fabs.ll b/llvm/test/CodeGen/Mips/fabs.ll
index 75aa7d8295f94..8cb06826b6879 100644
--- a/llvm/test/CodeGen/Mips/fabs.ll
+++ b/llvm/test/CodeGen/Mips/fabs.ll
@@ -80,11 +80,11 @@ entry:
; CHECK-ABSLEGACY: {{(ori|ins)}}
; CHECK-ABSLEGACY-NOT: abs.s
- %call = tail call float @fabsf(float %a) nounwind readnone
+ %call = tail call float @llvm.fabs.f32(float %a) nounwind readnone
ret float %call
}
-declare float @fabsf(float) nounwind readnone
+declare float @llvm.fabs.f32(float) nounwind readnone
define double @foo1(double %a) nounwind readnone {
entry:
@@ -94,8 +94,8 @@ entry:
; CHECK-ABSLEGACY: {{(ori|ins|dsll)}}
; CHECK-ABSLEGACY-NOT: abs.d
- %call = tail call double @fabs(double %a) nounwind readnone
+ %call = tail call double @llvm.fabs.f64(double %a) nounwind readnone
ret double %call
}
-declare double @fabs(double) nounwind readnone
+declare double @llvm.fabs.f64(double) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index f7331ef209a19..fb150094d5678 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -1232,11 +1232,11 @@ define fp128 @libcall1_fabsl() {
; CMP_CC_FMT-NEXT: jrc $ra
entry:
%0 = load fp128, ptr @gld0, align 16
- %call = tail call fp128 @fabsl(fp128 %0) nounwind readnone
+ %call = tail call fp128 @llvm.fabs.f128(fp128 %0) nounwind readnone
ret fp128 %call
}
-declare fp128 @fabsl(fp128) #1
+declare fp128 @llvm.fabs.f128(fp128) #1
define fp128 @libcall1_ceill() {
; C_CC_FMT-LABEL: libcall1_ceill:
diff --git a/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll b/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
index 0a0f14d43e361..f0f6bcf780ef3 100644
--- a/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
@@ -7,7 +7,7 @@ target triple = "powerpc64-unknown-linux-gnu"
; CHECK: blr
define hidden i256 @__divtc3(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
entry:
- call ppc_fp128 @fabsl( ppc_fp128 %d ) nounwind readnone ; <ppc_fp128>:0 [#uses=1]
+ call ppc_fp128 @llvm.fabs.ppcf128( ppc_fp128 %d ) nounwind readnone ; <ppc_fp128>:0 [#uses=1]
%1 = fcmp olt ppc_fp128 0xM00000000000000000000000000000000, %0 ; <i1>:1 [#uses=1]
%.pn106 = select i1 %1, ppc_fp128 %a, ppc_fp128 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
%.pn = fsub ppc_fp128 0xM00000000000000000000000000000000, %.pn106 ; <ppc_fp128> [#uses=1]
@@ -20,4 +20,4 @@ entry:
ret i256 0
}
-declare ppc_fp128 @fabsl(ppc_fp128) nounwind readnone
+declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128) nounwind readnone
diff --git a/llvm/test/CodeGen/PowerPC/fabs.ll b/llvm/test/CodeGen/PowerPC/fabs.ll
index 6821d827c6f2d..50e77844e4bc2 100644
--- a/llvm/test/CodeGen/PowerPC/fabs.ll
+++ b/llvm/test/CodeGen/PowerPC/fabs.ll
@@ -6,7 +6,7 @@ define double @fabs(double %f) {
; CHECK-NEXT: fabs f1, f1
; CHECK-NEXT: blr
;
- %t = tail call double @fabs( double %f ) readnone
+ %t = tail call double @llvm.fabs.f64( double %f ) readnone
ret double %t
}
diff --git a/llvm/test/CodeGen/PowerPC/fnabs.ll b/llvm/test/CodeGen/PowerPC/fnabs.ll
index d71f5457e9bb1..6c9fd4c449dc3 100644
--- a/llvm/test/CodeGen/PowerPC/fnabs.ll
+++ b/llvm/test/CodeGen/PowerPC/fnabs.ll
@@ -1,9 +1,9 @@
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fnabs
-declare double @fabs(double)
+declare double @llvm.fabs.f64(double)
define double @test(double %X) {
- %Y = call double @fabs( double %X ) readnone ; <double> [#uses=1]
+ %Y = call double @llvm.fabs.f64( double %X ) readnone ; <double> [#uses=1]
%Z = fsub double -0.000000e+00, %Y ; <double> [#uses=1]
ret double %Z
}
diff --git a/llvm/test/CodeGen/X86/fabs.ll b/llvm/test/CodeGen/X86/fabs.ll
index 4e6da83ec55f3..e1992be9e8829 100644
--- a/llvm/test/CodeGen/X86/fabs.ll
+++ b/llvm/test/CodeGen/X86/fabs.ll
@@ -3,8 +3,8 @@
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse,-sse2,-sse3 -enable-no-nans-fp-math | FileCheck %s --check-prefix=X87UNSAFE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
-declare float @fabsf(float)
-declare x86_fp80 @fabsl(x86_fp80)
+declare float @llvm.fabs.f32(float)
+declare x86_fp80 @llvm.fabs.f80(x86_fp80)
define float @test1(float %X) {
; X87-LABEL: test1:
@@ -23,7 +23,7 @@ define float @test1(float %X) {
; X64: # %bb.0:
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
- %Y = call float @fabsf(float %X) readnone
+ %Y = call float @llvm.fabs.f32(float %X) readnone
ret float %Y
}
@@ -45,7 +45,7 @@ define x86_fp80 @test2(x86_fp80 %X) {
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fabs
; X64-NEXT: retq
- %Y = call x86_fp80 @fabsl(x86_fp80 %X) readnone
+ %Y = call x86_fp80 @llvm.fabs.f80(x86_fp80 %X) readnone
ret x86_fp80 %Y
}
diff --git a/llvm/test/CodeGen/X86/fnabs.ll b/llvm/test/CodeGen/X86/fnabs.ll
index a3ddfb970dc44..b453f48f0b142 100644
--- a/llvm/test/CodeGen/X86/fnabs.ll
+++ b/llvm/test/CodeGen/X86/fnabs.ll
@@ -9,7 +9,7 @@ define float @scalar_no_abs(float %a) {
; CHECK-LABEL: scalar_no_abs:
; CHECK: vorps
; CHECK-NEXT: retq
- %fabs = tail call float @fabsf(float %a) #1
+ %fabs = tail call float @llvm.fabs.f32(float %a) #1
%fsub = fsub float -0.0, %fabs
ret float %fsub
}
@@ -20,7 +20,7 @@ define float @scalar_uses_abs(float %a) {
; CHECK-DAG: vorps
; CHECK: vmulss
; CHECK-NEXT: retq
- %fabs = tail call float @fabsf(float %a) #1
+ %fabs = tail call float @llvm.fabs.f32(float %a) #1
%fsub = fsub float -0.0, %fabs
%fmul = fmul float %fsub, %fabs
ret float %fmul
@@ -71,7 +71,7 @@ define <8 x float> @vector256_uses_abs(<8 x float> %a) {
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
-declare float @fabsf(float)
+declare float @llvm.fabs.f32(float)
attributes #1 = { readnone }
diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll
index ef616ca7d0d1b..338950ac4c350 100644
--- a/llvm/test/CodeGen/X86/fp128-i128.ll
+++ b/llvm/test/CodeGen/X86/fp128-i128.ll
@@ -419,11 +419,11 @@ define fp128 @TestFABS_LD(fp128 %x) #0 {
; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
entry:
- %call = tail call fp128 @fabsl(fp128 %x) #2
+ %call = tail call fp128 @llvm.fabs.f128(fp128 %x) #2
ret fp128 %call
}
-declare fp128 @fabsl(fp128) #1
+declare fp128 @llvm.fabs.f128(fp128) #1
declare fp128 @copysignl(fp128, fp128) #1
@@ -511,7 +511,7 @@ entry:
br i1 %cmp, label %if.then, label %cleanup
if.then: ; preds = %entry
- %call = tail call fp128 @fabsl(fp128 %sub) #2
+ %call = tail call fp128 @llvm.fabs.f128(fp128 %sub) #2
br label %cleanup
cleanup: ; preds = %entry, %if.then
diff --git a/llvm/test/CodeGen/X86/pr2656.ll b/llvm/test/CodeGen/X86/pr2656.ll
index 8306dafbb346f..d3f153be19293 100644
--- a/llvm/test/CodeGen/X86/pr2656.ll
+++ b/llvm/test/CodeGen/X86/pr2656.ll
@@ -61,9 +61,9 @@ define double @PR22371(double %x) {
; CHECK-NEXT: fldl (%esp)
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
- %call = tail call double @fabs(double %x) #0
+ %call = tail call double @llvm.fabs.f64(double %x) #0
ret double %call
}
-declare double @fabs(double) #0
+declare double @llvm.fabs.f64(double) #0
attributes #0 = { readnone }
diff --git a/llvm/test/CodeGen/X86/stack-align.ll b/llvm/test/CodeGen/X86/stack-align.ll
index 8be3b2240173f..85326357697c8 100644
--- a/llvm/test/CodeGen/X86/stack-align.ll
+++ b/llvm/test/CodeGen/X86/stack-align.ll
@@ -13,11 +13,11 @@ target triple = "i686-apple-darwin8"
define void @test(ptr byval({ double, double }) %z, ptr %P) nounwind {
entry:
%tmp3 = load double, ptr @G, align 16 ; <double> [#uses=1]
- %tmp4 = tail call double @fabs( double %tmp3 ) readnone ; <double> [#uses=1]
+ %tmp4 = tail call double @llvm.fabs.f64( double %tmp3 ) readnone ; <double> [#uses=1]
store volatile double %tmp4, ptr %P
%tmp = getelementptr { double, double }, ptr %z, i32 0, i32 0 ; <ptr> [#uses=1]
%tmp1 = load volatile double, ptr %tmp, align 8 ; <double> [#uses=1]
- %tmp2 = tail call double @fabs( double %tmp1 ) readnone ; <double> [#uses=1]
+ %tmp2 = tail call double @llvm.fabs.f64( double %tmp1 ) readnone ; <double> [#uses=1]
%tmp6 = fadd double %tmp4, %tmp2 ; <double> [#uses=1]
store volatile double %tmp6, ptr %P, align 8
ret void
@@ -48,7 +48,7 @@ entry:
ret <2 x double> %A
}
-declare double @fabs(double)
+declare double @llvm.fabs.f64(double)
; The pointer is already known aligned, so and x,-16 is eliminable.
define i32 @test4() nounwind {
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