[llvm] [AMDGPU][SILoadStoreOptimizer] Fix lds address operand offset (PR #176816)

[Mikael Holmen via llvm-commits]

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@@ -2226,20 +2258,35 @@ void SILoadStoreOptimizer::updateBaseAndOffset(MachineInstr &MI,
   TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);
 }
 
-std::optional<int32_t>
-SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
-  if (Op.isImm())
-    return Op.getImm();
+// Helper to extract a 64-bit constant offset from a V_ADD_U64_e64 instruction.
+// Returns true if successful, populating Addr with base register info and
+// offset.
+bool SILoadStoreOptimizer::processBaseWithConstOffset64(
+    MachineInstr *AddDef, const MachineOperand &Base, MemAddress &Addr) const {
+  if (!Base.isReg())
+    return false;
 
-  if (!Op.isReg())
-    return std::nullopt;
+  MachineOperand *Src0 = TII->getNamedOperand(*AddDef, AMDGPU::OpName::src0);
+  MachineOperand *Src1 = TII->getNamedOperand(*AddDef, AMDGPU::OpName::src1);
 
-  MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
-  if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 ||
-      !Def->getOperand(1).isImm())
-    return std::nullopt;
+  const MachineOperand *BaseOp = nullptr;
+
+  auto Offset = TII->getImmOrMaterializedImm(*Src1);
+
+  if (Offset) {
+    BaseOp = Src0;
+    Addr.Offset = *Offset;
+  } else {
+    // Both or neither are constants - can't handle this pattern
+    return false;
+  }
 
-  return Def->getOperand(1).getImm();
+  // Now extract the base register (which should be a 64-bit VGPR).
+  MachineInstr *BaseDef = MRI->getVRegDef(BaseOp->getReg());
----------------
mikaelholmen wrote:

BaseDef is unused when building without asserts.

https://github.com/llvm/llvm-project/pull/176816