[llvm] [AMDGPU] Optimize S_OR_B32 to S_ADDK_I32 where possible (PR #177949)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 26 05:03:27 PST 2026
https://github.com/Iasonaskrpr created https://github.com/llvm/llvm-project/pull/177949
This PR fixes #177753, converting disjoint S_OR_B32 to S_ADDK_I32 whenever possible, it avoids this transformation in case S_OR_B32 can be converted to bitset.
Note on Test Failures (Draft Status) This change causes significant register reshuffling across the test suite due to the new allocation hints and the swaps performed in case src0 is not a register and src1, along with the change from or to addk. To avoid a massive, noisy diff during the initial logic review:
This Draft PR only includes a representative sample of updated tests.
CodeGen/AMDGPU/combine-reg-or-const.ll -> Showcases change from S_OR to S_ADDK
CodeGen/AMDGPU/s-barrier.ll -> Showcases swap between Src0 and Src1 if src0 is not a register
The rest of the tests show the result of the register allocation hint we give, I have checked every test I updated and they seem ok to me.
Once the core logic is approved, I will run the update script across the remaining ~70 failing tests and mark the PR as "Ready for Review."
>From 496cc100ff512dda3b772de414fd043adb80281e Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Sun, 25 Jan 2026 14:42:41 +0200
Subject: [PATCH 1/5] AMDGPU added conversion from disjoint s_or_b32 to
s_addk_i32
---
.../Target/AMDGPU/SIShrinkInstructions.cpp | 34 ++++++++++++++-----
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 5b32bd0b72a59..337b4cc4f4168 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -911,7 +911,8 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
// Try to use S_ADDK_I32 and S_MULK_I32.
if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
- MI.getOpcode() == AMDGPU::S_MUL_I32) {
+ MI.getOpcode() == AMDGPU::S_MUL_I32 ||
+ MI.getOpcode() == AMDGPU::S_OR_B32) {
const MachineOperand *Dest = &MI.getOperand(0);
MachineOperand *Src0 = &MI.getOperand(1);
MachineOperand *Src1 = &MI.getOperand(2);
@@ -931,16 +932,31 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
continue;
}
-
+ unsigned Opc;
if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
if (Src1->isImm() && isKImmOperand(*Src1)) {
- unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?
- AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
-
- Src1->setImm(SignExtend64(Src1->getImm(), 32));
- MI.setDesc(TII->get(Opc));
- MI.tieOperands(0, 1);
- Changed = true;
+ unsigned NewOpc = 0;
+ int64_t ImmVal = Src1->getImm();
+
+ if (MI.getOpcode() == AMDGPU::S_OR_B32) {
+ uint32_t Imm = static_cast<uint32_t>(ImmVal);
+ if (MI.getFlag(MachineInstr::MIFlag::Disjoint)) {
+ bool IsBitSetCandidate = isPowerOf2_32(Imm) && MI.findRegisterDefOperand(AMDGPU::SCC, nullptr)->isDead() && (llvm::countr_zero(Imm) != 0);
+ if (!IsBitSetCandidate) {
+ NewOpc = AMDGPU::S_ADDK_I32;
+ }
+ }
+ }
+ else {
+ NewOpc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
+ }
+
+ if (NewOpc) {
+ Src1->setImm(SignExtend64(ImmVal, 32));
+ MI.setDesc(TII->get(NewOpc));
+ MI.tieOperands(0, 1);
+ Changed = true;
+ }
}
}
}
>From aff4bba0477b562bf1b673b213d2e1a71ace446b Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Sun, 25 Jan 2026 14:43:40 +0200
Subject: [PATCH 2/5] Formatted changes
---
.../Target/AMDGPU/SIShrinkInstructions.cpp | 30 +++++++++++--------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 337b4cc4f4168..0b82f167a3eb0 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -939,23 +939,27 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
int64_t ImmVal = Src1->getImm();
if (MI.getOpcode() == AMDGPU::S_OR_B32) {
- uint32_t Imm = static_cast<uint32_t>(ImmVal);
- if (MI.getFlag(MachineInstr::MIFlag::Disjoint)) {
- bool IsBitSetCandidate = isPowerOf2_32(Imm) && MI.findRegisterDefOperand(AMDGPU::SCC, nullptr)->isDead() && (llvm::countr_zero(Imm) != 0);
- if (!IsBitSetCandidate) {
- NewOpc = AMDGPU::S_ADDK_I32;
- }
+ uint32_t Imm = static_cast<uint32_t>(ImmVal);
+ if (MI.getFlag(MachineInstr::MIFlag::Disjoint)) {
+ bool IsBitSetCandidate =
+ isPowerOf2_32(Imm) &&
+ MI.findRegisterDefOperand(AMDGPU::SCC, nullptr)->isDead() &&
+ (llvm::countr_zero(Imm) != 0);
+ if (!IsBitSetCandidate) {
+ NewOpc = AMDGPU::S_ADDK_I32;
}
- }
- else {
- NewOpc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
+ }
+ } else {
+ NewOpc = (MI.getOpcode() == AMDGPU::S_ADD_I32)
+ ? AMDGPU::S_ADDK_I32
+ : AMDGPU::S_MULK_I32;
}
if (NewOpc) {
- Src1->setImm(SignExtend64(ImmVal, 32));
- MI.setDesc(TII->get(NewOpc));
- MI.tieOperands(0, 1);
- Changed = true;
+ Src1->setImm(SignExtend64(ImmVal, 32));
+ MI.setDesc(TII->get(NewOpc));
+ MI.tieOperands(0, 1);
+ Changed = true;
}
}
}
>From 30eb40c442e2cca12e89b3d9110ac18d1ffada33 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Mon, 26 Jan 2026 13:33:22 +0200
Subject: [PATCH 3/5] Removed unused variable
---
.../lib/Target/AMDGPU/SIShrinkInstructions.cpp | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 0b82f167a3eb0..b1b2de5cdd178 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -932,32 +932,30 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
continue;
}
- unsigned Opc;
if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
if (Src1->isImm() && isKImmOperand(*Src1)) {
- unsigned NewOpc = 0;
- int64_t ImmVal = Src1->getImm();
+ unsigned Opc = 0;
if (MI.getOpcode() == AMDGPU::S_OR_B32) {
- uint32_t Imm = static_cast<uint32_t>(ImmVal);
+ uint32_t Imm = static_cast<uint32_t>(Src1->getImm());
if (MI.getFlag(MachineInstr::MIFlag::Disjoint)) {
bool IsBitSetCandidate =
isPowerOf2_32(Imm) &&
- MI.findRegisterDefOperand(AMDGPU::SCC, nullptr)->isDead() &&
+ MI.registerDefIsDead(AMDGPU::SCC, /*TRI=*/nullptr) &&
(llvm::countr_zero(Imm) != 0);
if (!IsBitSetCandidate) {
- NewOpc = AMDGPU::S_ADDK_I32;
+ Opc = AMDGPU::S_ADDK_I32;
}
}
} else {
- NewOpc = (MI.getOpcode() == AMDGPU::S_ADD_I32)
+ Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32)
? AMDGPU::S_ADDK_I32
: AMDGPU::S_MULK_I32;
}
- if (NewOpc) {
- Src1->setImm(SignExtend64(ImmVal, 32));
- MI.setDesc(TII->get(NewOpc));
+ if (Opc != 0) {
+ Src1->setImm(SignExtend64(Src1->getImm(), 32));
+ MI.setDesc(TII->get(Opc));
MI.tieOperands(0, 1);
Changed = true;
}
>From 919b11d4324aa793ac90fe7f5c227762415c0b13 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Mon, 26 Jan 2026 14:45:25 +0200
Subject: [PATCH 4/5] Updated tests to work with transformation
---
llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll | 8 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll | 6 +-
.../GlobalISel/divergence-structurizer.ll | 60 +++---
.../test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll | 60 +++---
.../AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll | 6 +-
.../AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll | 10 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 178 +++++++++---------
.../CodeGen/AMDGPU/combine-reg-or-const.ll | 2 +-
llvm/test/CodeGen/AMDGPU/s-barrier.ll | 2 +-
9 files changed, 166 insertions(+), 166 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index 5c60eb696f6b2..f7f86f01d2665 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -207,8 +207,8 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
; GFX7-NEXT: s_and_b32 s5, s16, 0xffff
; GFX7-NEXT: s_lshl_b32 s4, s4, 16
-; GFX7-NEXT: s_or_b32 s4, s5, s4
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: s_or_b32 s5, s5, s4
+; GFX7-NEXT: v_mov_b32_e32 v0, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_add_v2i16:
@@ -232,8 +232,8 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_and_b32 s5, 0xffff, s16
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s4, s5, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_or_b32 s5, s5, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: s_add_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index 57755c6856858..856cb29e1ce4a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
@@ -452,9 +452,9 @@ define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {
; GFX7-NEXT: s_lshl_b32 s2, s0, 8
; GFX7-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX7-NEXT: v_alignbit_b32 v0, s1, v0, 24
-; GFX7-NEXT: s_or_b32 s2, s3, s2
+; GFX7-NEXT: s_or_b32 s3, s3, s2
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: s_and_b32 s0, 0xffff, s2
+; GFX7-NEXT: s_and_b32 s0, 0xffff, s3
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_or_b32_e32 v0, s0, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
index 5c57d355959ef..5e0b6f35358cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
@@ -526,65 +526,65 @@ define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2,
; GFX10-NEXT: s_mov_b32 s0, exec_lo
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: s_and_b32 s2, s0, 1
-; GFX10-NEXT: s_xor_b32 s0, vcc_lo, s0
+; GFX10-NEXT: s_xor_b32 s5, vcc_lo, s0
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: ; implicit-def: $sgpr2
; GFX10-NEXT: s_cselect_b32 s3, exec_lo, 0
; GFX10-NEXT: s_branch .LBB6_2
; GFX10-NEXT: .LBB6_1: ; %Flow2
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
-; GFX10-NEXT: s_and_b32 s4, exec_lo, s5
-; GFX10-NEXT: s_mov_b32 s0, exec_lo
-; GFX10-NEXT: s_or_b32 s1, s4, s1
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
+; GFX10-NEXT: s_and_b32 s0, exec_lo, s4
+; GFX10-NEXT: s_mov_b32 s5, exec_lo
+; GFX10-NEXT: s_or_b32 s1, s0, s1
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_cbranch_execz .LBB6_8
; GFX10-NEXT: .LBB6_2: ; %irr.guard
; GFX10-NEXT: ; =>This Loop Header: Depth=1
; GFX10-NEXT: ; Child Loop BB6_6 Depth 2
-; GFX10-NEXT: s_mov_b32 s4, exec_lo
-; GFX10-NEXT: s_and_saveexec_b32 s5, s0
-; GFX10-NEXT: s_xor_b32 s5, exec_lo, s5
+; GFX10-NEXT: s_mov_b32 s0, exec_lo
+; GFX10-NEXT: s_and_saveexec_b32 s4, s5
+; GFX10-NEXT: s_xor_b32 s4, exec_lo, s4
; GFX10-NEXT: ; %bb.3: ; %.loopexit
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
-; GFX10-NEXT: v_cmp_gt_i32_e64 s0, v5, v0
+; GFX10-NEXT: v_cmp_gt_i32_e64 s7, v5, v0
+; GFX10-NEXT: s_mov_b32 s5, exec_lo
; GFX10-NEXT: s_mov_b32 s6, exec_lo
-; GFX10-NEXT: s_mov_b32 s7, exec_lo
-; GFX10-NEXT: s_xor_b32 s6, vcc_lo, s6
+; GFX10-NEXT: s_xor_b32 s5, vcc_lo, s5
; GFX10-NEXT: s_andn2_b32 s3, s3, exec_lo
-; GFX10-NEXT: s_or_b32 s6, s0, s6
-; GFX10-NEXT: s_and_b32 s0, exec_lo, s0
-; GFX10-NEXT: s_xor_b32 s6, s6, s7
-; GFX10-NEXT: s_andn2_b32 s4, s4, exec_lo
-; GFX10-NEXT: s_and_b32 s6, exec_lo, s6
-; GFX10-NEXT: s_or_b32 s3, s3, s0
-; GFX10-NEXT: s_or_b32 s4, s4, s6
+; GFX10-NEXT: s_or_b32 s5, s7, s5
+; GFX10-NEXT: s_andn2_b32 s0, s0, exec_lo
+; GFX10-NEXT: s_xor_b32 s5, s5, s6
+; GFX10-NEXT: s_and_b32 s6, exec_lo, s7
+; GFX10-NEXT: s_and_b32 s5, exec_lo, s5
+; GFX10-NEXT: s_or_b32 s3, s3, s6
+; GFX10-NEXT: s_or_b32 s0, s0, s5
; GFX10-NEXT: ; %bb.4: ; %Flow1
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: s_andn2_b32 s0, s2, exec_lo
-; GFX10-NEXT: s_and_b32 s2, exec_lo, s3
-; GFX10-NEXT: s_mov_b32 s5, exec_lo
-; GFX10-NEXT: s_or_b32 s2, s0, s2
-; GFX10-NEXT: s_and_saveexec_b32 s6, s4
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_and_b32 s5, exec_lo, s3
+; GFX10-NEXT: s_mov_b32 s4, exec_lo
+; GFX10-NEXT: s_or_b32 s2, s2, s5
+; GFX10-NEXT: s_and_saveexec_b32 s5, s0
; GFX10-NEXT: s_cbranch_execz .LBB6_1
; GFX10-NEXT: ; %bb.5: ; %.preheader
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
; GFX10-NEXT: v_cmp_le_i32_e64 s0, v4, v0
-; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: s_mov_b32 s6, 0
; GFX10-NEXT: .LBB6_6: ; %.inner_loop
; GFX10-NEXT: ; Parent Loop BB6_2 Depth=1
; GFX10-NEXT: ; => This Inner Loop Header: Depth=2
; GFX10-NEXT: s_and_b32 s7, exec_lo, s0
-; GFX10-NEXT: s_or_b32 s4, s7, s4
-; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
+; GFX10-NEXT: s_or_b32 s6, s7, s6
+; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s6
; GFX10-NEXT: s_cbranch_execnz .LBB6_6
; GFX10-NEXT: ; %bb.7: ; %Flow
; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: s_andn2_b32 s0, s5, exec_lo
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX10-NEXT: s_andn2_b32 s0, s4, exec_lo
; GFX10-NEXT: s_and_b32 s4, exec_lo, 0
-; GFX10-NEXT: s_or_b32 s5, s0, s4
+; GFX10-NEXT: s_or_b32 s4, s0, s4
; GFX10-NEXT: s_branch .LBB6_1
; GFX10-NEXT: .LBB6_8: ; %.exit
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
index fa72eb72fd723..1f5cd4ab1c6d0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -122,7 +122,7 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX11-NEXT: s_and_b32 s4, s1, 0x1ff
; GFX11-NEXT: s_addk_i32 s2, 0xfc10
; GFX11-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX11-NEXT: s_or_b32 s0, s4, s0
+; GFX11-NEXT: s_or_b32 s4, s4, s0
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s3, s0
@@ -140,9 +140,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX11-NEXT: s_cmp_lg_u32 s4, s5
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s4, s6, s4
+; GFX11-NEXT: s_or_b32 s6, s6, s4
; GFX11-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-NEXT: s_cselect_b32 s0, s4, s0
+; GFX11-NEXT: s_cselect_b32 s0, s6, s0
; GFX11-NEXT: s_and_b32 s4, s0, 7
; GFX11-NEXT: s_lshr_b32 s0, s0, 2
; GFX11-NEXT: s_cmp_eq_u32 s4, 3
@@ -150,8 +150,8 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX11-NEXT: s_cmp_gt_i32 s4, 5
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s4, s5, s4
-; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: s_or_b32 s5, s5, s4
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s0, s0, s4
@@ -162,9 +162,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s1, s1, 0x8000
-; GFX11-NEXT: s_or_b32 s0, s1, s0
+; GFX11-NEXT: s_or_b32 s1, s1, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, s1
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptrunc_f64_to_f16_uniform:
@@ -174,7 +174,7 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX12-NEXT: s_and_b32 s4, s1, 0x1ff
; GFX12-NEXT: s_addk_co_i32 s2, 0xfc10
; GFX12-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX12-NEXT: s_or_b32 s0, s4, s0
+; GFX12-NEXT: s_or_b32 s4, s4, s0
; GFX12-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_or_b32 s0, s3, s0
@@ -192,9 +192,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX12-NEXT: s_cmp_lg_u32 s4, s5
; GFX12-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s4, s6, s4
+; GFX12-NEXT: s_or_b32 s6, s6, s4
; GFX12-NEXT: s_cmp_lt_i32 s2, 1
-; GFX12-NEXT: s_cselect_b32 s0, s4, s0
+; GFX12-NEXT: s_cselect_b32 s0, s6, s0
; GFX12-NEXT: s_and_b32 s4, s0, 7
; GFX12-NEXT: s_lshr_b32 s0, s0, 2
; GFX12-NEXT: s_cmp_eq_u32 s4, 3
@@ -202,8 +202,8 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX12-NEXT: s_cmp_gt_i32 s4, 5
; GFX12-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s4, s5, s4
-; GFX12-NEXT: s_cmp_lg_u32 s4, 0
+; GFX12-NEXT: s_or_b32 s5, s5, s4
+; GFX12-NEXT: s_cmp_lg_u32 s5, 0
; GFX12-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_add_co_i32 s0, s0, s4
@@ -214,9 +214,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX12-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_and_b32 s1, s1, 0x8000
-; GFX12-NEXT: s_or_b32 s0, s1, s0
+; GFX12-NEXT: s_or_b32 s1, s1, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: v_mov_b32_e32 v0, s1
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fptrunc_f64_to_f16_uniform:
@@ -227,7 +227,7 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX1250-NEXT: s_and_b32 s4, s1, 0x1ff
; GFX1250-NEXT: s_addk_co_i32 s2, 0xfc10
; GFX1250-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX1250-NEXT: s_or_b32 s0, s4, s0
+; GFX1250-NEXT: s_or_b32 s4, s4, s0
; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_or_b32 s0, s3, s0
@@ -245,9 +245,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX1250-NEXT: s_cmp_lg_u32 s4, s5
; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s4, s6, s4
+; GFX1250-NEXT: s_or_b32 s6, s6, s4
; GFX1250-NEXT: s_cmp_lt_i32 s2, 1
-; GFX1250-NEXT: s_cselect_b32 s0, s4, s0
+; GFX1250-NEXT: s_cselect_b32 s0, s6, s0
; GFX1250-NEXT: s_and_b32 s4, s0, 7
; GFX1250-NEXT: s_lshr_b32 s0, s0, 2
; GFX1250-NEXT: s_cmp_eq_u32 s4, 3
@@ -255,8 +255,8 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX1250-NEXT: s_cmp_gt_i32 s4, 5
; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s4, s5, s4
-; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1250-NEXT: s_or_b32 s5, s5, s4
+; GFX1250-NEXT: s_cmp_lg_u32 s5, 0
; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_add_co_i32 s0, s0, s4
@@ -267,9 +267,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX1250-NEXT: s_lshr_b32 s1, s1, 16
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s1, s1, 0x8000
-; GFX1250-NEXT: s_or_b32 s0, s1, s0
+; GFX1250-NEXT: s_or_b32 s1, s1, s0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: v_mov_b32_e32 v0, s1
; GFX1250-NEXT: ; return to shader part epilog
%result = fptrunc double %a to half
ret half %result
@@ -306,9 +306,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX11-NEXT: v_and_b32_e32 v4, 7, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v4
+; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
+; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
@@ -356,9 +356,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX12-NEXT: v_and_b32_e32 v4, 7, v3
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 2, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX12-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX12-NEXT: v_cmp_eq_u32_e64 s0, 3, v4
+; GFX12-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
+; GFX12-NEXT: s_or_b32 s0, s0, vcc_lo
; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -406,9 +406,9 @@ define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
; GFX1250-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 2, v3 :: v_dual_bitop2_b32 v4, 7, v3 bitop3:0x40
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX1250-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX1250-NEXT: v_cmp_eq_u32_e64 s0, 3, v4
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
+; GFX1250-NEXT: s_or_b32 s0, s0, vcc_lo
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
index a75ac906cb1c0..20b7e5f093918 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
@@ -95,7 +95,7 @@ define amdgpu_kernel void @bfe_i32_arg_imm_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, 59, s3
+; GFX6-NEXT: s_or_b32 s3, s3, 59
; GFX6-NEXT: s_bfe_i32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
@@ -114,8 +114,8 @@ define amdgpu_kernel void @bfe_i32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s4, s2, 63
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, s4, s3
-; GFX6-NEXT: s_bfe_i32 s3, 0x7b, s3
+; GFX6-NEXT: s_or_b32 s4, s4, s3
+; GFX6-NEXT: s_bfe_i32 s3, 0x7b, s4
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
index 91402df2100bc..d7c4c1dfb4180 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
@@ -78,8 +78,8 @@ define amdgpu_kernel void @bfe_u32_arg_arg_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s4, s3, 63
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, s4, s3
-; GFX6-NEXT: s_bfe_u32 s3, s2, s3
+; GFX6-NEXT: s_or_b32 s4, s4, s3
+; GFX6-NEXT: s_bfe_u32 s3, s2, s4
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
@@ -114,7 +114,7 @@ define amdgpu_kernel void @bfe_u32_arg_imm_arg(ptr addrspace(1) %out, i32 %src0,
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, 59, s3
+; GFX6-NEXT: s_or_b32 s3, s3, 59
; GFX6-NEXT: s_bfe_u32 s3, s2, s3
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
@@ -133,8 +133,8 @@ define amdgpu_kernel void @bfe_u32_imm_arg_arg(ptr addrspace(1) %out, i32 %src1,
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_and_b32 s4, s2, 63
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_or_b32 s3, s4, s3
-; GFX6-NEXT: s_bfe_u32 s3, 0x7b, s3
+; GFX6-NEXT: s_or_b32 s4, s4, s3
+; GFX6-NEXT: s_bfe_u32 s3, 0x7b, s4
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index ccc46cc5df39e..c4a3fb1f052cb 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -1306,8 +1306,8 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s19, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: s_or_b32 s6, s6, s5
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s5, s20, 0xff
; SI-NEXT: s_lshl_b32 s6, s21, 8
; SI-NEXT: s_or_b32 s5, s5, s6
@@ -1315,8 +1315,8 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s23, 24
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_or_b32 s5, s5, s6
+; SI-NEXT: s_or_b32 s7, s7, s6
+; SI-NEXT: s_or_b32 s5, s5, s7
; SI-NEXT: s_and_b32 s6, s24, 0xff
; SI-NEXT: s_lshl_b32 s7, s25, 8
; SI-NEXT: s_or_b32 s6, s6, s7
@@ -1324,8 +1324,8 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s8, s27, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_or_b32 s6, s6, s7
+; SI-NEXT: s_or_b32 s8, s8, s7
+; SI-NEXT: s_or_b32 s6, s6, s8
; SI-NEXT: s_cbranch_execnz .LBB7_3
; SI-NEXT: .LBB7_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -1419,9 +1419,9 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s5, s18, 0xff
; VI-NEXT: s_lshl_b32 s6, s19, 8
; VI-NEXT: s_addk_i32 s4, 0x300
-; VI-NEXT: s_or_b32 s5, s6, s5
+; VI-NEXT: s_or_b32 s6, s6, s5
; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s20, 0xff
@@ -1431,9 +1431,9 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s6, s22, 0xff
; VI-NEXT: s_lshl_b32 s7, s23, 8
; VI-NEXT: s_addk_i32 s5, 0x300
-; VI-NEXT: s_or_b32 s6, s7, s6
+; VI-NEXT: s_or_b32 s7, s7, s6
; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_lshl_b32 s6, s7, 16
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_or_b32 s5, s6, s5
; VI-NEXT: s_and_b32 s6, s24, 0xff
@@ -1443,9 +1443,9 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s7, s26, 0xff
; VI-NEXT: s_lshl_b32 s8, s27, 8
; VI-NEXT: s_addk_i32 s6, 0x300
-; VI-NEXT: s_or_b32 s7, s8, s7
+; VI-NEXT: s_or_b32 s8, s8, s7
; VI-NEXT: s_and_b32 s6, s6, 0xffff
-; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s8, 16
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: s_add_i32 s4, s4, 0x3000000
; VI-NEXT: s_add_i32 s5, s5, 0x3000000
@@ -1554,26 +1554,26 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: s_and_b32 s6, s2, 0xff
; GFX11-NEXT: s_lshl_b32 s8, s3, 8
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s5, s6, s8
+; GFX11-NEXT: s_or_b32 s6, s6, s8
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_lshl_b32 s6, s17, 8
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s6, 16
; GFX11-NEXT: s_and_b32 s8, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s19, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s6, s17, 8
+; GFX11-NEXT: s_or_b32 s8, s8, s9
; GFX11-NEXT: s_or_b32 s5, s5, s6
-; GFX11-NEXT: s_or_b32 s6, s8, s9
+; GFX11-NEXT: s_lshl_b32 s6, s8, 16
; GFX11-NEXT: s_and_b32 s8, s20, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s21, 8
; GFX11-NEXT: s_and_b32 s10, s22, 0xff
; GFX11-NEXT: s_lshl_b32 s11, s23, 8
; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_or_b32 s9, s10, s11
+; GFX11-NEXT: s_or_b32 s10, s10, s11
; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s8, s8, 0xffff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_or_b32 s6, s8, s9
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7
@@ -3275,10 +3275,10 @@ define inreg <6 x i16> @bitcast_v3i32_to_v6i16_scalar(<3 x i32> inreg %a, i32 in
; SI-NEXT: s_or_b32 s6, s6, s7
; SI-NEXT: s_and_b32 s7, s18, 0xffff
; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_or_b32 s4, s7, s4
+; SI-NEXT: s_or_b32 s7, s7, s4
; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_mov_b32_e32 v1, s6
-; SI-NEXT: v_mov_b32_e32 v2, s4
+; SI-NEXT: v_mov_b32_e32 v2, s7
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB17_4:
; SI-NEXT: ; implicit-def: $sgpr6
@@ -4589,8 +4589,8 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s19, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: s_or_b32 s6, s6, s5
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s5, s20, 0xff
; SI-NEXT: s_lshl_b32 s6, s21, 8
; SI-NEXT: s_or_b32 s5, s5, s6
@@ -4598,8 +4598,8 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s23, 24
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_or_b32 s5, s5, s6
+; SI-NEXT: s_or_b32 s7, s7, s6
+; SI-NEXT: s_or_b32 s5, s5, s7
; SI-NEXT: s_and_b32 s6, s24, 0xff
; SI-NEXT: s_lshl_b32 s7, s25, 8
; SI-NEXT: s_or_b32 s6, s6, s7
@@ -4607,8 +4607,8 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s8, s27, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_or_b32 s6, s6, s7
+; SI-NEXT: s_or_b32 s8, s8, s7
+; SI-NEXT: s_or_b32 s6, s6, s8
; SI-NEXT: s_cbranch_execnz .LBB23_3
; SI-NEXT: .LBB23_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -4702,9 +4702,9 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; VI-NEXT: s_and_b32 s5, s18, 0xff
; VI-NEXT: s_lshl_b32 s6, s19, 8
; VI-NEXT: s_addk_i32 s4, 0x300
-; VI-NEXT: s_or_b32 s5, s6, s5
+; VI-NEXT: s_or_b32 s6, s6, s5
; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s20, 0xff
@@ -4714,9 +4714,9 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; VI-NEXT: s_and_b32 s6, s22, 0xff
; VI-NEXT: s_lshl_b32 s7, s23, 8
; VI-NEXT: s_addk_i32 s5, 0x300
-; VI-NEXT: s_or_b32 s6, s7, s6
+; VI-NEXT: s_or_b32 s7, s7, s6
; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_lshl_b32 s6, s7, 16
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_or_b32 s5, s6, s5
; VI-NEXT: s_and_b32 s6, s24, 0xff
@@ -4726,9 +4726,9 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; VI-NEXT: s_and_b32 s7, s26, 0xff
; VI-NEXT: s_lshl_b32 s8, s27, 8
; VI-NEXT: s_addk_i32 s6, 0x300
-; VI-NEXT: s_or_b32 s7, s8, s7
+; VI-NEXT: s_or_b32 s8, s8, s7
; VI-NEXT: s_and_b32 s6, s6, 0xffff
-; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s8, 16
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: s_add_i32 s4, s4, 0x3000000
; VI-NEXT: s_add_i32 s5, s5, 0x3000000
@@ -4837,26 +4837,26 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX11-NEXT: s_and_b32 s6, s2, 0xff
; GFX11-NEXT: s_lshl_b32 s8, s3, 8
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s5, s6, s8
+; GFX11-NEXT: s_or_b32 s6, s6, s8
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_lshl_b32 s6, s17, 8
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s6, 16
; GFX11-NEXT: s_and_b32 s8, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s19, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s6, s17, 8
+; GFX11-NEXT: s_or_b32 s8, s8, s9
; GFX11-NEXT: s_or_b32 s5, s5, s6
-; GFX11-NEXT: s_or_b32 s6, s8, s9
+; GFX11-NEXT: s_lshl_b32 s6, s8, 16
; GFX11-NEXT: s_and_b32 s8, s20, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s21, 8
; GFX11-NEXT: s_and_b32 s10, s22, 0xff
; GFX11-NEXT: s_lshl_b32 s11, s23, 8
; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_or_b32 s9, s10, s11
+; GFX11-NEXT: s_or_b32 s10, s10, s11
; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s8, s8, 0xffff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_or_b32 s6, s8, s9
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7
@@ -7520,9 +7520,9 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: s_and_b32 s5, s18, 0xff
; VI-NEXT: s_lshl_b32 s6, s19, 8
; VI-NEXT: s_addk_i32 s4, 0x300
-; VI-NEXT: s_or_b32 s5, s6, s5
+; VI-NEXT: s_or_b32 s6, s6, s5
; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s20, 0xff
@@ -7532,9 +7532,9 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: s_and_b32 s6, s22, 0xff
; VI-NEXT: s_lshl_b32 s7, s23, 8
; VI-NEXT: s_addk_i32 s5, 0x300
-; VI-NEXT: s_or_b32 s6, s7, s6
+; VI-NEXT: s_or_b32 s7, s7, s6
; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_lshl_b32 s6, s7, 16
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_or_b32 s5, s6, s5
; VI-NEXT: s_and_b32 s6, s24, 0xff
@@ -7544,9 +7544,9 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: s_and_b32 s7, s26, 0xff
; VI-NEXT: s_lshl_b32 s8, s27, 8
; VI-NEXT: s_addk_i32 s6, 0x300
-; VI-NEXT: s_or_b32 s7, s8, s7
+; VI-NEXT: s_or_b32 s8, s8, s7
; VI-NEXT: s_and_b32 s6, s6, 0xffff
-; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s8, 16
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: s_add_i32 s4, s4, 0x3000000
; VI-NEXT: s_add_i32 s5, s5, 0x3000000
@@ -7655,26 +7655,26 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: s_and_b32 s6, s2, 0xff
; GFX11-NEXT: s_lshl_b32 s7, s3, 8
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s5, s6, s7
+; GFX11-NEXT: s_or_b32 s6, s6, s7
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_lshl_b32 s6, s17, 8
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s6, 16
; GFX11-NEXT: s_and_b32 s7, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s19, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s6, s17, 8
+; GFX11-NEXT: s_or_b32 s7, s7, s9
; GFX11-NEXT: s_or_b32 s5, s5, s6
-; GFX11-NEXT: s_or_b32 s6, s7, s9
+; GFX11-NEXT: s_lshl_b32 s6, s7, 16
; GFX11-NEXT: s_and_b32 s7, s20, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s21, 8
; GFX11-NEXT: s_and_b32 s10, s22, 0xff
; GFX11-NEXT: s_lshl_b32 s11, s23, 8
; GFX11-NEXT: s_or_b32 s7, s7, s9
-; GFX11-NEXT: s_or_b32 s9, s10, s11
+; GFX11-NEXT: s_or_b32 s10, s10, s11
; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_or_b32 s6, s7, s9
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s8
@@ -9399,9 +9399,9 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: s_and_b32 s5, s18, 0xff
; VI-NEXT: s_lshl_b32 s6, s19, 8
; VI-NEXT: s_addk_i32 s4, 0x300
-; VI-NEXT: s_or_b32 s5, s6, s5
+; VI-NEXT: s_or_b32 s6, s6, s5
; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s20, 0xff
@@ -9411,9 +9411,9 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: s_and_b32 s6, s22, 0xff
; VI-NEXT: s_lshl_b32 s7, s23, 8
; VI-NEXT: s_addk_i32 s5, 0x300
-; VI-NEXT: s_or_b32 s6, s7, s6
+; VI-NEXT: s_or_b32 s7, s7, s6
; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_lshl_b32 s6, s7, 16
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_or_b32 s5, s6, s5
; VI-NEXT: s_and_b32 s6, s24, 0xff
@@ -9423,9 +9423,9 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: s_and_b32 s7, s26, 0xff
; VI-NEXT: s_lshl_b32 s8, s27, 8
; VI-NEXT: s_addk_i32 s6, 0x300
-; VI-NEXT: s_or_b32 s7, s8, s7
+; VI-NEXT: s_or_b32 s8, s8, s7
; VI-NEXT: s_and_b32 s6, s6, 0xffff
-; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s8, 16
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: s_add_i32 s4, s4, 0x3000000
; VI-NEXT: s_add_i32 s5, s5, 0x3000000
@@ -9534,26 +9534,26 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: s_and_b32 s6, s2, 0xff
; GFX11-NEXT: s_lshl_b32 s7, s3, 8
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s5, s6, s7
+; GFX11-NEXT: s_or_b32 s6, s6, s7
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_lshl_b32 s6, s17, 8
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s6, 16
; GFX11-NEXT: s_and_b32 s7, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s19, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s6, s17, 8
+; GFX11-NEXT: s_or_b32 s7, s7, s9
; GFX11-NEXT: s_or_b32 s5, s5, s6
-; GFX11-NEXT: s_or_b32 s6, s7, s9
+; GFX11-NEXT: s_lshl_b32 s6, s7, 16
; GFX11-NEXT: s_and_b32 s7, s20, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s21, 8
; GFX11-NEXT: s_and_b32 s10, s22, 0xff
; GFX11-NEXT: s_lshl_b32 s11, s23, 8
; GFX11-NEXT: s_or_b32 s7, s7, s9
-; GFX11-NEXT: s_or_b32 s9, s10, s11
+; GFX11-NEXT: s_or_b32 s10, s10, s11
; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_or_b32 s6, s7, s9
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s8
@@ -10833,9 +10833,9 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s5, s18, 0xff
; VI-NEXT: s_lshl_b32 s6, s19, 8
; VI-NEXT: s_addk_i32 s4, 0x300
-; VI-NEXT: s_or_b32 s5, s6, s5
+; VI-NEXT: s_or_b32 s6, s6, s5
; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s5, 16
+; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s20, 0xff
@@ -10845,9 +10845,9 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s6, s22, 0xff
; VI-NEXT: s_lshl_b32 s7, s23, 8
; VI-NEXT: s_addk_i32 s5, 0x300
-; VI-NEXT: s_or_b32 s6, s7, s6
+; VI-NEXT: s_or_b32 s7, s7, s6
; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_lshl_b32 s6, s7, 16
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_or_b32 s5, s6, s5
; VI-NEXT: s_and_b32 s6, s24, 0xff
@@ -10857,9 +10857,9 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b32 s7, s26, 0xff
; VI-NEXT: s_lshl_b32 s8, s27, 8
; VI-NEXT: s_addk_i32 s6, 0x300
-; VI-NEXT: s_or_b32 s7, s8, s7
+; VI-NEXT: s_or_b32 s8, s8, s7
; VI-NEXT: s_and_b32 s6, s6, 0xffff
-; VI-NEXT: s_lshl_b32 s7, s7, 16
+; VI-NEXT: s_lshl_b32 s7, s8, 16
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: s_add_i32 s4, s4, 0x3000000
; VI-NEXT: s_add_i32 s5, s5, 0x3000000
@@ -10968,26 +10968,26 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: s_and_b32 s6, s2, 0xff
; GFX11-NEXT: s_lshl_b32 s7, s3, 8
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s5, s6, s7
+; GFX11-NEXT: s_or_b32 s6, s6, s7
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_lshl_b32 s6, s17, 8
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s6, 16
; GFX11-NEXT: s_and_b32 s7, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s19, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s5, s16, 0xff
+; GFX11-NEXT: s_lshl_b32 s6, s17, 8
+; GFX11-NEXT: s_or_b32 s7, s7, s9
; GFX11-NEXT: s_or_b32 s5, s5, s6
-; GFX11-NEXT: s_or_b32 s6, s7, s9
+; GFX11-NEXT: s_lshl_b32 s6, s7, 16
; GFX11-NEXT: s_and_b32 s7, s20, 0xff
; GFX11-NEXT: s_lshl_b32 s9, s21, 8
; GFX11-NEXT: s_and_b32 s10, s22, 0xff
; GFX11-NEXT: s_lshl_b32 s11, s23, 8
; GFX11-NEXT: s_or_b32 s7, s7, s9
-; GFX11-NEXT: s_or_b32 s9, s10, s11
+; GFX11-NEXT: s_or_b32 s10, s10, s11
; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 16
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_or_b32 s6, s7, s9
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s8
diff --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
index c167834470e3b..83e62cbb9b6fb 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
@@ -27,7 +27,7 @@ define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocaptu
; CHECK-NEXT: s_addc_u32 s1, s3, s5
; CHECK-NEXT: s_bfe_u32 s2, s6, 0xd0003
; CHECK-NEXT: s_add_i32 s2, s2, s7
-; CHECK-NEXT: s_or_b32 s2, s2, 0xc0
+; CHECK-NEXT: s_addk_i32 s2, 0xc0
; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: v_mov_b32_e32 v1, s1
; CHECK-NEXT: v_mov_b32_e32 v2, s2
diff --git a/llvm/test/CodeGen/AMDGPU/s-barrier.ll b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
index 35b86998c9cac..82885b07e569c 100644
--- a/llvm/test/CodeGen/AMDGPU/s-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
@@ -88,7 +88,7 @@ define amdgpu_kernel void @kernel1(ptr addrspace(1) %out, ptr addrspace(3) %in)
; GFX12-SDAG-NEXT: s_lshr_b32 s2, s2, 4
; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-SDAG-NEXT: s_and_b32 s2, s2, 63
-; GFX12-SDAG-NEXT: s_or_b32 s3, 0x90000, s2
+; GFX12-SDAG-NEXT: s_or_b32 s3, s2, 0x90000
; GFX12-SDAG-NEXT: s_cmp_eq_u32 0, 0
; GFX12-SDAG-NEXT: s_mov_b32 m0, s3
; GFX12-SDAG-NEXT: s_barrier_init m0
>From 389afe33386fef67125535f738b460e1f4d92fc1 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Mon, 26 Jan 2026 14:48:16 +0200
Subject: [PATCH 5/5] Correctly formatted file
---
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index b1b2de5cdd178..32fc9c4d8c73d 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -948,9 +948,8 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
}
}
} else {
- Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32)
- ? AMDGPU::S_ADDK_I32
- : AMDGPU::S_MULK_I32;
+ Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? AMDGPU::S_ADDK_I32
+ : AMDGPU::S_MULK_I32;
}
if (Opc != 0) {
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