[llvm] [RISCV] Run combineOrToBitfieldInsert after DAG legalize (PR #177830)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/177830

>From 1e91d994999f1665e498fc19fd1da80cd30fc9c1 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Sat, 24 Jan 2026 15:07:52 +0530
Subject: [PATCH 1/3] Pre-commit test

---
 llvm/test/CodeGen/RISCV/xqcibm-insert.ll | 28 ++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
index 234bd233ec9af..6c0dcb925b45d 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
@@ -401,3 +401,31 @@ define i32 @bseti_i32_10(i32 %a) nounwind {
   %or = or i32 %a, 1024
   ret i32 %or
 }
+
+define i1 @no_insbi_known_bits(i32 %arg) {
+; RV32I-LABEL: no_insbi_known_bits:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32IXQCIBM-LABEL: no_insbi_known_bits:
+; RV32IXQCIBM:       # %bb.0:
+; RV32IXQCIBM-NEXT:    qc.insbi a0, -1, 7, 24
+; RV32IXQCIBM-NEXT:    qc.extu a0, a0, 7, 24
+; RV32IXQCIBM-NEXT:    addi a0, a0, -127
+; RV32IXQCIBM-NEXT:    seqz a0, a0
+; RV32IXQCIBM-NEXT:    ret
+;
+; RV32IXQCIBMZBS-LABEL: no_insbi_known_bits:
+; RV32IXQCIBMZBS:       # %bb.0:
+; RV32IXQCIBMZBS-NEXT:    qc.insbi a0, -1, 7, 24
+; RV32IXQCIBMZBS-NEXT:    qc.extu a0, a0, 7, 24
+; RV32IXQCIBMZBS-NEXT:    addi a0, a0, -127
+; RV32IXQCIBMZBS-NEXT:    seqz a0, a0
+; RV32IXQCIBMZBS-NEXT:    ret
+  %a = or i32 %arg, 2147483647
+  %b = call i32 @llvm.bswap.i32(i32 %a)
+  %and = and i32 %b, 127
+  %res = icmp eq i32 %and, 127
+  ret i1 %res
+}

>From f633ade70289032a8e7d19c50dabae7016f80098 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Sun, 25 Jan 2026 10:37:36 +0530
Subject: [PATCH 2/3] Run combineOrToBitfieldInsert after legalizer

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp |  7 ++++---
 llvm/test/CodeGen/RISCV/xqcibm-insert.ll    | 10 ++--------
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0148a7de56fd8..4034a93405c05 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17051,8 +17051,6 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                                 const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
 
-  if (SDValue V = combineOrToBitfieldInsert(N, DAG, Subtarget))
-    return V;
   if (SDValue V = combineOrAndToBitfieldInsert(N, DAG, Subtarget))
     return V;
   if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
@@ -17060,9 +17058,12 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
     return V;
 
-  if (DCI.isAfterLegalizeDAG())
+  if (DCI.isAfterLegalizeDAG()) {
+    if (SDValue V = combineOrToBitfieldInsert(N, DAG, Subtarget))
+    return V;
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
+  }
 
   // Look for Or of CZERO_EQZ/NEZ with same condition which is the select idiom.
   // We may be able to pull a common operation out of the true and false value.
diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
index 6c0dcb925b45d..043a184d34ccd 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
@@ -410,18 +410,12 @@ define i1 @no_insbi_known_bits(i32 %arg) {
 ;
 ; RV32IXQCIBM-LABEL: no_insbi_known_bits:
 ; RV32IXQCIBM:       # %bb.0:
-; RV32IXQCIBM-NEXT:    qc.insbi a0, -1, 7, 24
-; RV32IXQCIBM-NEXT:    qc.extu a0, a0, 7, 24
-; RV32IXQCIBM-NEXT:    addi a0, a0, -127
-; RV32IXQCIBM-NEXT:    seqz a0, a0
+; RV32IXQCIBM-NEXT:    li a0, 1
 ; RV32IXQCIBM-NEXT:    ret
 ;
 ; RV32IXQCIBMZBS-LABEL: no_insbi_known_bits:
 ; RV32IXQCIBMZBS:       # %bb.0:
-; RV32IXQCIBMZBS-NEXT:    qc.insbi a0, -1, 7, 24
-; RV32IXQCIBMZBS-NEXT:    qc.extu a0, a0, 7, 24
-; RV32IXQCIBMZBS-NEXT:    addi a0, a0, -127
-; RV32IXQCIBMZBS-NEXT:    seqz a0, a0
+; RV32IXQCIBMZBS-NEXT:    li a0, 1
 ; RV32IXQCIBMZBS-NEXT:    ret
   %a = or i32 %arg, 2147483647
   %b = call i32 @llvm.bswap.i32(i32 %a)

>From 3462f5a20fa0f55f29c5e6c084941deb257ed9c5 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Sun, 25 Jan 2026 10:47:47 +0530
Subject: [PATCH 3/3] clang-format

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4034a93405c05..436ce16784c75 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17060,7 +17060,7 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
 
   if (DCI.isAfterLegalizeDAG()) {
     if (SDValue V = combineOrToBitfieldInsert(N, DAG, Subtarget))
-    return V;
+      return V;
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;
   }