[llvm] [RISCV] Rename RVInstV->RVInstVUnary. NFC (PR #177900)
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Sun Jan 25 21:52:28 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
I'd RVInstV to be a prefix name for vector related classes.
---
Full diff: https://github.com/llvm/llvm-project/pull/177900.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormatsV.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+17-17)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index a19cd6450ebce..af103b07bd42f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -162,8 +162,8 @@ class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
let RVVConstraint = VMConstraint;
}
-class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
- dag ins, string opcodestr, string argstr>
+class RVInstVUnary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
+ dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> vs2;
bits<5> vd;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index de46bcdd51c4f..9dc5128dd0933 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -572,9 +572,9 @@ class VMACVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
// op vd, vs2, vm (use vs1 as instruction encoding)
class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
- : RVInstV<funct6, vs1, opv, (outs VR:$vd),
- (ins VR:$vs2, VMaskOp:$vm),
- opcodestr, "$vd, $vs2$vm">;
+ : RVInstVUnary<funct6, vs1, opv, (outs VR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
//===----------------------------------------------------------------------===//
@@ -1641,15 +1641,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask in {
// Vector mask population count vcpop
-def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2, VMaskOp:$vm),
- "vcpop.m", "$vd, $vs2$vm">,
+def VCPOP_M : RVInstVUnary<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "vcpop.m", "$vd, $vs2$vm">,
SchedUnaryMC<"WriteVMPopV", "ReadVMPopV">;
// vfirst find-first-set mask bit
-def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2, VMaskOp:$vm),
- "vfirst.m", "$vd, $vs2$vm">,
+def VFIRST_M : RVInstVUnary<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2, VMaskOp:$vm),
+ "vfirst.m", "$vd, $vs2$vm">,
SchedUnaryMC<"WriteVMFFSV", "ReadVMFFSV">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint, ElementsDependOn = EltDepsVLMask
@@ -1675,14 +1675,14 @@ defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
let vs2 = 0 in
-def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
- (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
+def VID_V : RVInstVUnary<0b010100, 0b10001, OPMVV, (outs VR:$vd),
+ (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
SchedNullaryMC<"WriteVIdxV">;
// Integer Scalar Move Instructions
let vm = 1, RVVConstraint = NoConstraint in {
-def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
- (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
+def VMV_X_S : RVInstVUnary<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
Sched<[WriteVMovXS, ReadVMovXS]>;
let Constraints = "$vd = $vd_wb" in
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
@@ -1699,8 +1699,8 @@ let Predicates = [HasVInstructionsAnyF] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
RVVConstraint = NoConstraint in {
// Floating-Point Scalar Move Instructions
-def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
- (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
+def VFMV_F_S : RVInstVUnary<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
+ (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
Sched<[WriteVMovFS, ReadVMovFS]>;
let Constraints = "$vd = $vd_wb" in
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
@@ -1751,8 +1751,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
// A future extension may relax the vector register alignment restrictions.
foreach n = [1, 2, 4, 8] in {
defvar vrc = !cast<VReg>(!if(!eq(n, 1), "VR", "VRM"#n));
- def VMV#n#R_V : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
- (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
+ def VMV#n#R_V : RVInstVUnary<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
+ (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
VMVRSched<n> {
let Uses = [VTYPE];
let vm = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 39a7aeda94707..daf8550e4cb45 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -119,8 +119,8 @@ let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos",
let vm = 0, vs2=0, Inst<6-0> = OPC_CUSTOM_2.Value,
isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def RI_VZERO : RVInstV<0b000000, 0b00000, OPCFG, (outs VR:$vd),
- (ins), "ri.vzero.v", "$vd">;
+def RI_VZERO : RVInstVUnary<0b000000, 0b00000, OPCFG, (outs VR:$vd),
+ (ins), "ri.vzero.v", "$vd">;
def RI_VINSERT : CustomRivosVXI<0b010000, OPMVX, (outs VR:$vd_wb),
(ins VR:$vd, GPR:$rs1, uimm5:$imm),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 5a5a9edebd925..01ba3a7c27e67 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -96,8 +96,8 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
// regardless of tail policy
class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
string opcodestr>
- : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
- opcodestr, "$vd, $vs2"> {
+ : RVInstVUnary<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
+ opcodestr, "$vd, $vs2"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
``````````
</details>
https://github.com/llvm/llvm-project/pull/177900
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