[llvm] [RISCV] Add a tablegen base class for RVInstV* to reduce duplication. NFC (PR #177898)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/177898.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrFormatsV.td (+17-50) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index a19cd6450ebce..dfea2c84d5d5d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -83,18 +83,15 @@ class RVInstVSetVL<dag outs, dag ins, string opcodestr, string argstr>
   let Defs = [VL, VTYPE];
 }
 
-class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
-               string opcodestr, string argstr>
+class RVInstVBase<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+                  string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
-  bits<5> vs2;
-  bits<5> vs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
-  let Inst{24-20} = vs2;
-  let Inst{19-15} = vs1;
+  // Inst{24-15} provide by subclasses
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Inst{6-0} = OPC_OP_V.Value;
@@ -103,82 +100,52 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
   let RVVConstraint = VMConstraint;
 }
 
+class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+               string opcodestr, string argstr>
+    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
+  bits<5> vs2;
+  bits<5> vs1;
+
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+}
+
 class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
   bits<5> vs2;
   bits<5> rs1;
-  bits<5> vd;
-  bit vm;
 
-  let Inst{31-26} = funct6;
-  let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = opv.Value;
-  let Inst{11-7} = vd;
-  let Inst{6-0} = OPC_OP_V.Value;
-
-  let Uses = [VL, VTYPE];
-  let RVVConstraint = VMConstraint;
 }
 
 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
   bits<5> rs1;
-  bits<5> vd;
-  bit vm;
 
-  let Inst{31-26} = funct6;
-  let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = opv.Value;
-  let Inst{11-7} = vd;
-  let Inst{6-0} = OPC_OP_V.Value;
-
-  let Uses = [VL, VTYPE];
-  let RVVConstraint = VMConstraint;
 }
 
 class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
                 string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInstVBase<funct6, OPIVI, outs, ins, opcodestr, argstr> {
   bits<5> vs2;
   bits<5> imm;
-  bits<5> vd;
-  bit vm;
 
-  let Inst{31-26} = funct6;
-  let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm;
-  let Inst{14-12} = OPIVI.Value;
-  let Inst{11-7} = vd;
-  let Inst{6-0} = OPC_OP_V.Value;
-
-  let Uses = [VL, VTYPE];
-  let RVVConstraint = VMConstraint;
 }
 
 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
               dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
   bits<5> vs2;
-  bits<5> vd;
-  bit vm;
 
-  let Inst{31-26} = funct6;
-  let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
-  let Inst{14-12} = opv.Value;
-  let Inst{11-7} = vd;
-  let Inst{6-0} = OPC_OP_V.Value;
-
-  let Uses = [VL, VTYPE];
-  let RVVConstraint = VMConstraint;
 }
 
 class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,

``````````

</details>


https://github.com/llvm/llvm-project/pull/177898