[llvm] [RISC-V][sanitizers][NFCI] Add documentation on which sanitizers probably work (PR #177679)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 23 12:51:23 PST 2026


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Thurston Dang (thurstond)

<details>
<summary>Changes</summary>

Docs requested in https://github.com/llvm/llvm-project/issues/172375

---
Full diff: https://github.com/llvm/llvm-project/pull/177679.diff


1 Files Affected:

- (modified) llvm/docs/RISCVUsage.rst (+13) 


``````````diff
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 97442c0cc5e75..6d19fd758d42f 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -612,3 +612,16 @@ Clang's ``-msmall-data-limit=`` option controls what the threshold size is (in b
 The small data limit threshold is also used to separate small constants into sections with names starting with ``.srodata``. LLD does not place these with the ``.sdata`` and ``.sbss`` sections as ``.srodata`` sections are read only and the other two are writable. Instead the ``.srodata`` sections are placed adjacent to ``.rodata``.
 
 Data suggests that these options can produce significant improvements across a range of benchmarks.
+
+Sanitizer Support
+=================
+
+* UBSan is not platform-specific, and should work out of the box.
+
+* ASan and TSan already have shadow mappings defined for RISC-V, and are likely to work.
+
+* HWASan may work on very new versions of LLVM (e.g., after https://github.com/llvm/llvm-project/pull/176616), though RISC-V Pointer Masking (also very new) is needed as well to make it run efficiently.
+
+* MTE: N/A - there is currently no ratified RISC-V memory tagging spec.
+
+* MSan is unlikely to work: there are currently no RISC-V-specific shadow mappings (this is probably easy to fix; perhaps the default Linux 64-bit mapping will work) and MSan does not explicitly handle any of the `@llvm.riscv.*` intrinsics (this is significantly more work to fix). Some intrinsics will be handled correctly anyway, if the RISC-V intrinsic is auto-upgraded into cross-platform LLVM intrinsics. Some others will be "heuristically" handled (possibly incorrectly). The rest will default to the "strict" handler, which checks that all the parameters are fully initialized.

``````````

</details>


https://github.com/llvm/llvm-project/pull/177679


More information about the llvm-commits mailing list