[llvm] DAG: Use poison in more vector legalization contexts (PR #177580)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 23 05:27:24 PST 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/177580
>From 202746056c1efd93fe4f68177b4c5d38cff29817 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 11 Nov 2025 18:39:00 -0800
Subject: [PATCH] DAG: Use poison in more vector legalization contexts
---
.../SelectionDAG/LegalizeVectorTypes.cpp | 61 ++++++-------
.../AArch64/sve-load-store-legalisation.ll | 85 +------------------
2 files changed, 33 insertions(+), 113 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 1a7cec8fc7565..c8b91751af159 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2050,7 +2050,7 @@ SDValue DAGTypeLegalizer::UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE) {
}
for (; i < ResNE; ++i)
- Scalars.push_back(DAG.getUNDEF(EltVT));
+ Scalars.push_back(DAG.getPOISON(EltVT));
// Build a new factor node to connect the chain back together.
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
@@ -2678,7 +2678,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS(SDNode *N, SDValue &Lo,
std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
std::tie(LoMask, HiMask) = SplitMask(Mask);
- SDValue UndefPassthru = DAG.getUNDEF(LoVT);
+ SDValue UndefPassthru = DAG.getPOISON(LoVT);
Lo = DAG.getNode(ISD::VECTOR_COMPRESS, DL, LoVT, Lo, LoMask, UndefPassthru);
Hi = DAG.getNode(ISD::VECTOR_COMPRESS, DL, HiVT, Hi, HiMask, UndefPassthru);
@@ -3361,7 +3361,7 @@ void DAGTypeLegalizer::SplitVecRes_VP_REVERSE(SDNode *N, SDValue &Lo,
SDValue TrueMask = DAG.getBoolConstant(true, DL, Mask.getValueType(), VT);
SDValue Store = DAG.getStridedStoreVP(DAG.getEntryNode(), DL, Val, StorePtr,
- DAG.getUNDEF(PtrVT), Stride, TrueMask,
+ DAG.getPOISON(PtrVT), Stride, TrueMask,
EVL, MemVT, StoreMMO, ISD::UNINDEXED);
SDValue Load = DAG.getLoadVP(VT, DL, Store, StackPtr, Mask, EVL, LoadMMO);
@@ -3403,15 +3403,16 @@ void DAGTypeLegalizer::SplitVecRes_VP_SPLICE(SDNode *N, SDValue &Lo,
Alignment);
SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, EVL1);
+ SDValue PoisonPtr = DAG.getPOISON(PtrVT);
SDValue TrueMask = DAG.getBoolConstant(true, DL, Mask.getValueType(), VT);
- SDValue StoreV1 = DAG.getStoreVP(DAG.getEntryNode(), DL, V1, StackPtr,
- DAG.getUNDEF(PtrVT), TrueMask, EVL1,
- V1.getValueType(), StoreMMO, ISD::UNINDEXED);
+ SDValue StoreV1 =
+ DAG.getStoreVP(DAG.getEntryNode(), DL, V1, StackPtr, PoisonPtr, TrueMask,
+ EVL1, V1.getValueType(), StoreMMO, ISD::UNINDEXED);
SDValue StoreV2 =
- DAG.getStoreVP(StoreV1, DL, V2, StackPtr2, DAG.getUNDEF(PtrVT), TrueMask,
- EVL2, V2.getValueType(), StoreMMO, ISD::UNINDEXED);
+ DAG.getStoreVP(StoreV1, DL, V2, StackPtr2, PoisonPtr, TrueMask, EVL2,
+ V2.getValueType(), StoreMMO, ISD::UNINDEXED);
SDValue Load;
if (Imm >= 0) {
@@ -5303,7 +5304,7 @@ static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI,
if (!VT.isVector()) {
// Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
- SDValue VecOp = DAG.getUNDEF(NextVT);
+ SDValue VecOp = DAG.getPOISON(NextVT);
unsigned NumToInsert = ConcatEnd - Idx - 1;
for (unsigned i = 0, OpIdx = Idx + 1; i < NumToInsert; i++, OpIdx++)
VecOp = DAG.getInsertVectorElt(dl, VecOp, ConcatOps[OpIdx], i);
@@ -5311,7 +5312,7 @@ static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI,
ConcatEnd = Idx + 2;
} else {
// Vector type, create a CONCAT_VECTORS of type NextVT
- SDValue undefVec = DAG.getUNDEF(VT);
+ SDValue undefVec = DAG.getPOISON(VT);
unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
unsigned RealVals = ConcatEnd - Idx - 1;
@@ -5337,7 +5338,7 @@ static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI,
// add undefs of size MaxVT until ConcatOps grows to length of WidenVT
unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
if (NumOps != ConcatEnd ) {
- SDValue UndefVal = DAG.getUNDEF(MaxVT);
+ SDValue UndefVal = DAG.getPOISON(MaxVT);
for (unsigned j = ConcatEnd; j < NumOps; ++j)
ConcatOps[j] = UndefVal;
}
@@ -5494,7 +5495,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_StrictFP(SDNode *N) {
EVT::getVectorVT(*DAG.getContext(), OpVT.getVectorElementType(),
WidenVT.getVectorElementCount());
Oper = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
- DAG.getUNDEF(WideOpVT), Oper,
+ DAG.getPOISON(WideOpVT), Oper,
DAG.getVectorIdxConstant(0, dl));
}
}
@@ -5595,12 +5596,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo) {
WideOvVT.getVectorNumElements());
SDValue Zero = DAG.getVectorIdxConstant(0, DL);
- WideLHS = DAG.getNode(
- ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
- N->getOperand(0), Zero);
- WideRHS = DAG.getNode(
- ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
- N->getOperand(1), Zero);
+ SDValue Poison = DAG.getPOISON(WideResVT);
+
+ WideLHS = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideResVT, Poison,
+ N->getOperand(0), Zero);
+ WideRHS = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideResVT, Poison,
+ N->getOperand(1), Zero);
}
SDVTList WideVTs = DAG.getVTList(WideResVT, WideOvVT);
@@ -6293,7 +6294,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
// Read back the sub-vector setting the remaining lanes to poison.
StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, InVT, VT, Idx);
return DAG.getMaskedLoad(
- WidenVT, dl, Ch, StackPtr, DAG.getUNDEF(StackPtr.getValueType()), Mask,
+ WidenVT, dl, Ch, StackPtr, DAG.getPOISON(StackPtr.getValueType()), Mask,
DAG.getPOISON(WidenVT), VT, LoadMMO, ISD::UNINDEXED, ISD::NON_EXTLOAD);
}
@@ -6595,7 +6596,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
// scalable vectors, so for scalable vectors, we still use vp.load
// but manually merge the load result with the passthru using vp.select.
(N->getPassThru()->isUndef() || VT.isScalableVector())) {
- Mask = DAG.getInsertSubvector(dl, DAG.getUNDEF(WideMaskVT), Mask, 0);
+ Mask = DAG.getInsertSubvector(dl, DAG.getPOISON(WideMaskVT), Mask, 0);
SDValue EVL = DAG.getElementCount(dl, TLI.getVPExplicitVectorLengthTy(),
VT.getVectorElementCount());
SDValue NewLoad =
@@ -6801,7 +6802,7 @@ SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
} else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
EVT SubVT = Mask->getValueType(0);
- SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
+ SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getPOISON(SubVT));
SubOps[0] = Mask;
Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
}
@@ -7333,7 +7334,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
"We can't have the same type as we started with!");
if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
- InOp = DAG.getInsertSubvector(DL, DAG.getUNDEF(FixedVT), InOp, 0);
+ InOp = DAG.getInsertSubvector(DL, DAG.getPOISON(FixedVT), InOp, 0);
else
InOp = DAG.getExtractSubvector(DL, FixedVT, InOp, 0);
break;
@@ -7668,7 +7669,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(SDNode *N) {
SDValue SubVecPtr =
TLI.getVectorSubVecPointer(DAG, StackPtr, VT, OrigVT, N->getOperand(2));
Ch = DAG.getMaskedStore(Ch, DL, SubVec, SubVecPtr,
- DAG.getUNDEF(SubVecPtr.getValueType()), Mask, VT,
+ DAG.getPOISON(SubVecPtr.getValueType()), Mask, VT,
StoreMMO, ISD::UNINDEXED, ISD::NON_EXTLOAD);
// Read back the result.
@@ -7888,7 +7889,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
if (TLI.isOperationLegalOrCustom(ISD::VP_STORE, WideVT) &&
TLI.isTypeLegal(WideMaskVT)) {
- Mask = DAG.getInsertSubvector(dl, DAG.getUNDEF(WideMaskVT), Mask, 0);
+ Mask = DAG.getInsertSubvector(dl, DAG.getPOISON(WideMaskVT), Mask, 0);
SDValue EVL = DAG.getElementCount(dl, TLI.getVPExplicitVectorLengthTy(),
VT.getVectorElementCount());
return DAG.getStoreVP(MST->getChain(), dl, StVal, MST->getBasePtr(),
@@ -8488,7 +8489,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
for (; j != End-Idx; ++j)
WidenOps[j] = ConcatOps[Idx+j];
for (; j != NumOps; ++j)
- WidenOps[j] = DAG.getUNDEF(LdTy);
+ WidenOps[j] = DAG.getPOISON(LdTy);
ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
WidenOps);
@@ -8506,7 +8507,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
unsigned NumOps =
WidenWidth.getKnownMinValue() / LdTy.getSizeInBits().getKnownMinValue();
SmallVector<SDValue, 16> WidenOps(NumOps);
- SDValue UndefVal = DAG.getUNDEF(LdTy);
+ SDValue UndefVal = DAG.getPOISON(LdTy);
{
unsigned i = 0;
for (; i != End-Idx; ++i)
@@ -8561,7 +8562,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
}
// Fill the rest with undefs.
- SDValue UndefVal = DAG.getUNDEF(EltVT);
+ SDValue UndefVal = DAG.getPOISON(EltVT);
for (; i != WidenNumElts; ++i)
Ops[i] = UndefVal;
@@ -8681,8 +8682,8 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
if (WidenEC.hasKnownScalarFactor(InEC)) {
unsigned NumConcat = WidenEC.getKnownScalarFactor(InEC);
SmallVector<SDValue, 16> Ops(NumConcat);
- SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
- DAG.getUNDEF(InVT);
+ SDValue FillVal =
+ FillWithZeroes ? DAG.getConstant(0, dl, InVT) : DAG.getPOISON(InVT);
Ops[0] = InOp;
for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = FillVal;
@@ -8707,7 +8708,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
for (Idx = 0; Idx < MinNumElts; ++Idx)
Ops[Idx] = DAG.getExtractVectorElt(dl, EltVT, InOp, Idx);
- SDValue UndefVal = DAG.getUNDEF(EltVT);
+ SDValue UndefVal = DAG.getPOISON(EltVT);
for (; Idx < WidenNumElts; ++Idx)
Ops[Idx] = UndefVal;
diff --git a/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll b/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
index 584753bffdbe0..5d18deb229a1f 100644
--- a/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+++ b/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
@@ -287,61 +287,12 @@ define void @sve_load_store_nxv18i8(ptr %a, ptr %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: rdvl x8, #1
+; CHECK-NEXT: ldr z1, [x0]
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, x8]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpklo z1.s, z0.h
-; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
-; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpkhi z1.s, z0.h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: uzp1 z1.s, z0.s, z1.s
-; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
-; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpkhi z1.s, z0.h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s
-; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpklo z2.s, z1.h
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: uzp1 z2.s, z0.s, z2.s
-; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpklo z2.s, z1.h
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uunpklo z2.d, z2.s
-; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
-; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpkhi z2.s, z1.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: uzp1 z2.s, z0.s, z2.s
-; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpkhi z2.s, z1.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uunpklo z2.d, z2.s
-; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
-; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h
-; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
-; CHECK-NEXT: ldr z1, [x0]
-; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: st1b { z0.d }, p0, [x1, x8]
@@ -382,18 +333,6 @@ define void @sve_load_store_nxv20i8(ptr %a, ptr %b) {
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uzp1 z1.h, z0.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uzp1 z1.h, z1.h, z0.h
-; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: st1b { z0.s }, p0, [x1, #4, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 20 x i8>, ptr %a
@@ -435,15 +374,7 @@ define void @sve_load_store_nxv22i8(ptr %a, ptr %b) {
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uzp1 z1.h, z0.h, z1.h
-; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b
-; CHECK-NEXT: uunpkhi z1.h, z1.b
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uzp1 z1.h, z1.h, z0.h
-; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
+; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z1.s, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
@@ -805,18 +736,6 @@ define void @sve_load_store_nxv10i16(ptr %a, ptr %b) {
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
-; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: uzp1 z1.s, z0.s, z1.s
-; CHECK-NEXT: uzp1 z1.h, z0.h, z1.h
-; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s
-; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: st1h { z0.d }, p0, [x1, #4, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 10 x i16>, ptr %a
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