[llvm] 7184229 - [NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 23 00:19:08 PST 2026
Author: Sam Elliott
Date: 2026-01-23T00:19:03-08:00
New Revision: 7184229feafb6695e2b82adda805ccb5f82a1717
URL: https://github.com/llvm/llvm-project/commit/7184229feafb6695e2b82adda805ccb5f82a1717
DIFF: https://github.com/llvm/llvm-project/commit/7184229feafb6695e2b82adda805ccb5f82a1717.diff
LOG: [NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
This Change makes `RegState` into an enum class, with bitwise operators.
It also:
- Updates declarations of flag variables/arguments/returns from
`unsigned` to `RegState`.
- Updates empty RegState initializers from 0 to `{}`.
If this is causing problems in downstream code:
- Adopt the `RegState getXXXRegState(bool)` functions instead of using a
ternary operator such as `bool ? RegState::XXX : 0`.
- Adopt the `bool hasRegState(RegState, RegState)` function instead of
using a bitwise check of the flags.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/lib/CodeGen/SplitKit.cpp
llvm/lib/CodeGen/TailDuplicator.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMFastISel.cpp
llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
llvm/lib/Target/X86/X86FastISel.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
llvm/lib/Target/X86/X86TileConfig.cpp
llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
llvm/test/TableGen/GlobalISelEmitter/Subreg.td
llvm/test/TableGen/GlobalISelEmitter/dead-def.td
llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
llvm/test/TableGen/GlobalISelEmitter/input-discard.td
llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
llvm/test/TableGen/GlobalISelEmitter/optional-def.td
llvm/test/TableGen/GlobalISelEmitter/output-discard.td
llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
llvm/tools/llvm-exegesis/lib/Assembler.cpp
llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index a50a0a04fe2bc..78b189d44e285 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -1157,7 +1157,7 @@ bool GIMatchTableExecutor::executeMatchTable(
uint16_t SubRegIdx = readU16();
assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
- 0, SubRegIdx);
+ {}, SubRegIdx);
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
<< NewInsnID << "], MIs[" << OldInsnID << "], "
@@ -1168,13 +1168,14 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIR_AddImplicitDef: {
uint64_t InsnID = readULEB();
uint16_t RegNum = readU16();
- uint16_t Flags = readU16();
+ RegState Flags = static_cast<RegState>(readU16());
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
Flags |= RegState::Implicit;
OutMIs[InsnID].addDef(RegNum, Flags);
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
- << InsnID << "], " << RegNum << ")\n");
+ << InsnID << "], " << RegNum << ", "
+ << static_cast<uint16_t>(Flags) << ")\n");
break;
}
@@ -1192,13 +1193,13 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIR_AddRegister: {
uint64_t InsnID = readULEB();
uint16_t RegNum = readU16();
- uint16_t RegFlags = readU16();
+ RegState RegFlags = static_cast<RegState>(readU16());
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
OutMIs[InsnID].addReg(RegNum, RegFlags);
DEBUG_WITH_TYPE(TgtExecutor::getName(),
- dbgs()
- << CurrentIdx << ": GIR_AddRegister(OutMIs[" << InsnID
- << "], " << RegNum << ", " << RegFlags << ")\n");
+ dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
+ << InsnID << "], " << RegNum << ", "
+ << static_cast<uint16_t>(RegFlags) << ")\n");
break;
}
case GIR_AddIntrinsicID: {
@@ -1260,9 +1261,9 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIR_AddTempSubRegister: {
uint64_t InsnID = readULEB();
uint64_t TempRegID = readULEB();
- uint16_t TempRegFlags = 0;
+ RegState TempRegFlags = {};
if (MatcherOpcode != GIR_AddSimpleTempRegister)
- TempRegFlags = readU16();
+ TempRegFlags = static_cast<RegState>(readU16());
uint16_t SubReg = 0;
if (MatcherOpcode == GIR_AddTempSubRegister)
SubReg = readU16();
@@ -1276,7 +1277,7 @@ bool GIMatchTableExecutor::executeMatchTable(
dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs[" << InsnID
<< "], TempRegisters[" << TempRegID << "]";
if (SubReg) dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
- dbgs() << ", " << TempRegFlags << ")\n");
+ dbgs() << ", " << static_cast<uint16_t>(TempRegFlags) << ")\n");
break;
}
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index eb9bcfb7c01a3..1a33d760fb59e 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -20,6 +20,7 @@
#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -39,10 +40,14 @@ namespace llvm {
class MCInstrDesc;
class MDNode;
-namespace RegState {
-
-// Keep this in sync with the table in MIRLangRef.rst.
-enum {
+/// Flags to represent properties of register accesses.
+///
+/// These used to be represented with `unsigned`, but the underlying type of
+/// this enum class is `uint16_t` because these flags are serialized into 2-byte
+/// fields in the GlobalISel table emitters.
+///
+/// Keep this in sync with the table in MIRLangReg.rst
+enum class RegState : uint16_t {
/// No Specific Flags
NoFlags = 0x0,
// Reserved value, to detect if someone is passing `true` rather than this
@@ -67,48 +72,49 @@ enum {
InternalRead = 0x100,
/// Register that may be renamed.
Renamable = 0x200,
+
+ LLVM_MARK_AS_BITMASK_ENUM(Renamable),
+
// Combinations of above flags
DefineNoRead = Define | Undef,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
-} // end namespace RegState
-
-constexpr unsigned getDefRegState(bool B) {
+constexpr RegState getDefRegState(bool B) {
return B ? RegState::Define : RegState::NoFlags;
}
-constexpr unsigned getImplRegState(bool B) {
+constexpr RegState getImplRegState(bool B) {
return B ? RegState::Implicit : RegState::NoFlags;
}
-constexpr unsigned getKillRegState(bool B) {
+constexpr RegState getKillRegState(bool B) {
return B ? RegState::Kill : RegState::NoFlags;
}
-constexpr unsigned getDeadRegState(bool B) {
+constexpr RegState getDeadRegState(bool B) {
return B ? RegState::Dead : RegState::NoFlags;
}
-constexpr unsigned getUndefRegState(bool B) {
+constexpr RegState getUndefRegState(bool B) {
return B ? RegState::Undef : RegState::NoFlags;
}
-constexpr unsigned getEarlyClobberRegState(bool B) {
+constexpr RegState getEarlyClobberRegState(bool B) {
return B ? RegState::EarlyClobber : RegState::NoFlags;
}
-constexpr unsigned getDebugRegState(bool B) {
+constexpr RegState getDebugRegState(bool B) {
return B ? RegState::Debug : RegState::NoFlags;
}
-constexpr unsigned getInternalReadRegState(bool B) {
+constexpr RegState getInternalReadRegState(bool B) {
return B ? RegState::InternalRead : RegState::NoFlags;
}
-constexpr unsigned getRenamableRegState(bool B) {
+constexpr RegState getRenamableRegState(bool B) {
return B ? RegState::Renamable : RegState::NoFlags;
}
-constexpr bool hasRegState(unsigned Value, unsigned Test) {
+constexpr bool hasRegState(RegState Value, RegState Test) {
return (Value & Test) == Test;
}
/// Get all register state flags from machine operand \p RegOp.
-inline unsigned getRegState(const MachineOperand &RegOp) {
+inline RegState getRegState(const MachineOperand &RegOp) {
assert(RegOp.isReg() && "Not a register operand");
return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
@@ -190,7 +196,7 @@ class MachineInstrBuilder {
Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
/// Add a new virtual register operand.
- const MachineInstrBuilder &addReg(Register RegNo, unsigned Flags = 0,
+ const MachineInstrBuilder &addReg(Register RegNo, RegState Flags = {},
unsigned SubReg = 0) const {
assert(!hasRegState(Flags, RegState::_Reserved) &&
"Passing in 'true' to addReg is forbidden! Use enums instead.");
@@ -209,14 +215,14 @@ class MachineInstrBuilder {
}
/// Add a virtual register definition operand.
- const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
+ const MachineInstrBuilder &addDef(Register RegNo, RegState Flags = {},
unsigned SubReg = 0) const {
return addReg(RegNo, Flags | RegState::Define, SubReg);
}
/// Add a virtual register use operand. It is an error for Flags to contain
/// `RegState::Define` when calling this function.
- const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
+ const MachineInstrBuilder &addUse(Register RegNo, RegState Flags = {},
unsigned SubReg = 0) const {
assert(!hasRegState(Flags, RegState::Define) &&
"Misleading addUse defines register, use addReg instead.");
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 59b52d3bdb6c4..91fddce7e7e47 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2195,7 +2195,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
unsigned SrcSubReg,
Register Dst) const {
return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
- .addReg(Src, 0, SrcSubReg);
+ .addReg(Src, {}, SrcSubReg);
}
/// Returns a \p outliner::OutlinedFunction struct containing target-specific
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 1071cf00aa843..05bbf4bc64dff 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -452,7 +452,7 @@ class MIParser {
bool parseVirtualRegister(VRegInfo *&Info);
bool parseNamedVirtualRegister(VRegInfo *&Info);
bool parseRegister(Register &Reg, VRegInfo *&VRegInfo);
- bool parseRegisterFlag(unsigned &Flags);
+ bool parseRegisterFlag(RegState &Flags);
bool parseRegisterClassOrBank(VRegInfo &RegInfo);
bool parseSubRegisterIndex(unsigned &SubReg);
bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx);
@@ -1658,8 +1658,8 @@ bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
llvm_unreachable("Unexpected register kind");
}
-bool MIParser::parseRegisterFlag(unsigned &Flags) {
- const unsigned OldFlags = Flags;
+bool MIParser::parseRegisterFlag(RegState &Flags) {
+ const RegState OldFlags = Flags;
switch (Token.kind()) {
case MIToken::kw_implicit:
Flags |= RegState::Implicit;
@@ -1768,7 +1768,7 @@ bool MIParser::assignRegisterTies(MachineInstr &MI,
bool MIParser::parseRegisterOperand(MachineOperand &Dest,
std::optional<unsigned> &TiedDefIdx,
bool IsDef) {
- unsigned Flags = getDefRegState(IsDef);
+ RegState Flags = getDefRegState(IsDef);
while (Token.isRegisterFlag()) {
if (parseRegisterFlag(Flags))
return true;
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 10621f8b1a4c4..a28bdd3aefc4e 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -919,7 +919,7 @@ bool PeepholeOptimizer::optimizeExtInstr(
Register NewVR = MRI->createVirtualRegister(RC);
BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVR)
- .addReg(DstReg, 0, SubIdx);
+ .addReg(DstReg, {}, SubIdx);
if (UseSrcSubIdx)
UseMO->setSubReg(0);
@@ -1104,7 +1104,7 @@ static MachineInstr &insertPHI(MachineRegisterInfo &MRI,
unsigned MBBOpIdx = 2;
for (const RegSubRegPair &RegPair : SrcRegs) {
- MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
+ MIB.addReg(RegPair.Reg, {}, RegPair.SubReg);
MIB.addMBB(OrigPHI.getOperand(MBBOpIdx).getMBB());
// Since we're extended the lifetime of RegPair.Reg, clear the
// kill flags to account for that and make RegPair.Reg reaches
@@ -1300,7 +1300,7 @@ MachineInstr &PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
MachineInstr *NewCopy =
BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg)
- .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
+ .addReg(NewSrc.Reg, {}, NewSrc.SubReg);
if (Def.SubReg) {
NewCopy->getOperand(0).setSubReg(Def.SubReg);
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 982f31ca78f51..2482a0da1e0fe 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -322,7 +322,7 @@ void RenameIndependentSubregs::computeMainRangesFixFlags(
for (LiveInterval::SubRange &SR : LI.subranges())
UsedMask |= SR.LaneMask;
SmallVector<unsigned> SubRegIdxs;
- unsigned Flags = 0;
+ RegState Flags = {};
unsigned SubReg = 0;
// TODO: Handle SubRegIdxs.size() > 1
if (TRI.getCoveringSubRegIndexes(MRI->getRegClass(Reg), UsedMask,
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index f8e1b08276b52..3247a18bde637 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -2176,7 +2176,8 @@ Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, Register Op0,
const TargetRegisterClass *RC = MRI.getRegClass(Op0);
MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
- ResultReg).addReg(Op0, 0, Idx);
+ ResultReg)
+ .addReg(Op0, {}, Idx);
return ResultReg;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 4ad721bf21959..bb203f6367b5b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -568,7 +568,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
TII->get(TargetOpcode::COPY), VRBase);
if (Reg.isVirtual())
- CopyMI.addReg(Reg, 0, SubIdx);
+ CopyMI.addReg(Reg, {}, SubIdx);
else
CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
}
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index e7fdceb7f4923..0834e23a98efc 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -526,10 +526,13 @@ SlotIndex SplitEditor::buildSingleSubRegCopy(
MachineBasicBlock::iterator InsertBefore, unsigned SubIdx,
LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) {
bool FirstCopy = !Def.isValid();
- MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
- .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
- | getInternalReadRegState(!FirstCopy), SubIdx)
- .addReg(FromReg, 0, SubIdx);
+ MachineInstr *CopyMI =
+ BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
+ .addReg(ToReg,
+ RegState::Define | getUndefRegState(FirstCopy) |
+ getInternalReadRegState(!FirstCopy),
+ SubIdx)
+ .addReg(FromReg, {}, SubIdx);
CopyMI->setFlag(MachineInstr::LRSplit);
SlotIndexes &Indexes = *LIS.getSlotIndexes();
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
index 109444bda083e..b059f28e3c9b3 100644
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -461,7 +461,7 @@ void TailDuplicator::duplicateInstruction(
Register NewReg = MRI->createVirtualRegister(OrigRC);
BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(), TII->get(TargetOpcode::COPY),
NewReg)
- .addReg(VI->second.Reg, 0, VI->second.SubReg);
+ .addReg(VI->second.Reg, {}, VI->second.SubReg);
LocalVRMap.erase(VI);
LocalVRMap.try_emplace(Reg, NewReg, 0);
MO.setReg(NewReg);
@@ -1072,7 +1072,7 @@ void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
for (auto &CI : CopyInfos) {
auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
- .addReg(CI.second.Reg, 0, CI.second.SubReg);
+ .addReg(CI.second.Reg, {}, CI.second.SubReg);
Copies.push_back(C);
}
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 98cf4ad6bb6d3..ff339d4a23915 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1605,7 +1605,7 @@ void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,
TII->get(TargetOpcode::COPY), RegA);
// If this operand is folding a truncation, the truncation now moves to the
// copy so that the register classes remain valid for the operands.
- MIB.addReg(RegB, 0, SubRegB);
+ MIB.addReg(RegB, {}, SubRegB);
const TargetRegisterClass *RC = MRI->getRegClass(RegB);
if (SubRegB) {
if (RegA.isVirtual()) {
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index c7efe20599d8a..27d5940c808d2 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -137,7 +137,7 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
unsigned BitSize) {
MachineInstr &MI = *MBBI;
Register DstReg = MI.getOperand(0).getReg();
- unsigned RenamableState =
+ RegState RenamableState =
getRenamableRegState(MI.getOperand(0).isRenamable());
uint64_t Imm = MI.getOperand(1).getImm();
@@ -617,7 +617,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
}
// Preserve undef state until DOP's reg is defined.
- unsigned DOPRegState = getUndefRegState(MI.getOperand(DOPIdx).isUndef());
+ RegState DOPRegState = getUndefRegState(MI.getOperand(DOPIdx).isUndef());
//
// Create the destructive operation (if required)
@@ -641,7 +641,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
// After the movprfx, the destructive operand is same as Dst
DOPIdx = 0;
- DOPRegState = 0;
+ DOPRegState = {};
// Create the additional LSL to zero the lanes when the DstReg is not
// unique. Zeros the lanes in z0 that aren't active in p0 with sequence
@@ -662,7 +662,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
.addReg(DstReg, RegState::Define)
.addReg(MI.getOperand(DOPIdx).getReg(), DOPRegState);
DOPIdx = 0;
- DOPRegState = 0;
+ DOPRegState = {};
}
//
@@ -792,7 +792,7 @@ bool AArch64ExpandPseudo::expandSVESpillFill(MachineBasicBlock &MBB,
assert((Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI ||
Opc == AArch64::LDR_PXI || Opc == AArch64::STR_PXI) &&
"Unexpected opcode");
- unsigned RState =
+ RegState RState =
getDefRegState(Opc == AArch64::LDR_ZXI || Opc == AArch64::LDR_PXI);
unsigned sub0 = (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI)
? AArch64::zsub0
@@ -1297,7 +1297,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
.add(MI.getOperand(3));
transferImpOps(MI, I, I);
} else {
- unsigned RegState =
+ RegState RegState =
getRenamableRegState(MI.getOperand(1).isRenamable()) |
getKillRegState(
MI.getOperand(1).isKill() &&
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 284b6074abb9e..e524c98984ee7 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1535,7 +1535,7 @@ StackOffset AArch64FrameLowering::resolveFrameOffsetReference(
return StackOffset::getFixed(Offset) + SVEAreaOffset;
}
-static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
+static RegState getPrologueDeath(MachineFunction &MF, unsigned Reg) {
// Do not set a kill flag on values that are also marked as live-in. This
// happens with the @llvm-returnaddress intrinsic and with arguments passed in
// callee saved registers.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c1165a7ca4011..755db8790003e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4108,7 +4108,7 @@ MachineInstr *AArch64InstrInfo::emitLdStWithAddr(MachineInstr &MemI,
if (RC->hasSuperClassEq(&AArch64::GPR64RegClass)) {
OffsetReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
BuildMI(MBB, MemI, DL, get(TargetOpcode::COPY), OffsetReg)
- .addReg(AM.ScaledReg, 0, AArch64::sub_32);
+ .addReg(AM.ScaledReg, {}, AArch64::sub_32);
}
auto B =
BuildMI(MBB, MemI, DL, get(Opcode))
@@ -5320,7 +5320,7 @@ bool AArch64InstrInfo::shouldClusterMemOps(
static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
MCRegister Reg, unsigned SubIdx,
- unsigned State,
+ RegState State,
const TargetRegisterInfo *TRI) {
if (!SubIdx)
return MIB.addReg(Reg, State);
@@ -5359,7 +5359,7 @@ void AArch64InstrInfo::copyPhysRegTuple(MachineBasicBlock &MBB,
for (; SubReg != End; SubReg += Incr) {
const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
- AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
+ AddSubReg(MIB, SrcReg, Indices[SubReg], {}, TRI);
AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index d25db89cca358..6d7c986eccffc 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -804,7 +804,7 @@ bool AArch64MIPeepholeOpt::visitUBFMXri(MachineInstr &MI) {
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::COPY),
SrcReg32)
- .addReg(SrcReg64, 0, AArch64::sub_32);
+ .addReg(SrcReg64, {}, AArch64::sub_32);
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::UBFMWri),
DstReg32)
.addReg(SrcReg32)
diff --git a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
index b4a4f4ce86e33..6b42323448bb9 100644
--- a/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
@@ -184,8 +184,8 @@ struct AArch64SIMDInstrOpt : public MachineFunctionPass {
/// Example of such instructions.
/// %dest = REG_SEQUENCE %st2_src1, dsub0, %st2_src2, dsub1;
/// Return true when the instruction is processed successfully.
- bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
- unsigned* StRegKill, unsigned NumArg) const;
+ bool processSeqRegInst(MachineInstr *DefiningMI, unsigned *StReg,
+ RegState *StRegKill, unsigned NumArg) const;
/// Load/Store Interleaving instructions are not always beneficial.
/// Replace them by ZIP instructionand classical load/store.
@@ -431,15 +431,15 @@ bool AArch64SIMDInstrOpt::optimizeVectElement(MachineInstr &MI) {
// Get the operands of the current SIMD arithmetic instruction.
Register MulDest = MI.getOperand(0).getReg();
Register SrcReg0 = MI.getOperand(1).getReg();
- unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill());
+ RegState Src0IsKill = getKillRegState(MI.getOperand(1).isKill());
Register SrcReg1 = MI.getOperand(2).getReg();
- unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill());
+ RegState Src1IsKill = getKillRegState(MI.getOperand(2).isKill());
unsigned DupDest;
// Instructions of interest have either 4 or 5 operands.
if (MI.getNumOperands() == 5) {
Register SrcReg2 = MI.getOperand(3).getReg();
- unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill());
+ RegState Src2IsKill = getKillRegState(MI.getOperand(3).isKill());
unsigned LaneNumber = MI.getOperand(4).getImm();
// Create a new DUP instruction. Note that if an equivalent DUP instruction
// has already been created before, then use that one instead of creating
@@ -505,7 +505,8 @@ bool AArch64SIMDInstrOpt::optimizeVectElement(MachineInstr &MI) {
bool AArch64SIMDInstrOpt::optimizeLdStInterleave(MachineInstr &MI) {
unsigned SeqReg, AddrReg;
- unsigned StReg[4], StRegKill[4];
+ unsigned StReg[4];
+ RegState StRegKill[4];
MachineInstr *DefiningMI;
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock &MBB = *MI.getParent();
@@ -632,7 +633,9 @@ bool AArch64SIMDInstrOpt::optimizeLdStInterleave(MachineInstr &MI) {
/// %dest = REG_SEQUENCE %st2_src1, dsub0, %st2_src2, dsub1;
/// Return true when the instruction is processed successfully.
bool AArch64SIMDInstrOpt::processSeqRegInst(MachineInstr *DefiningMI,
- unsigned* StReg, unsigned* StRegKill, unsigned NumArg) const {
+ unsigned *StReg,
+ RegState *StRegKill,
+ unsigned NumArg) const {
assert(DefiningMI != nullptr);
if (DefiningMI->getOpcode() != AArch64::REG_SEQUENCE)
return false;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 61352086bab9f..7605bbea51f56 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -937,7 +937,7 @@ static bool copySubReg(MachineInstr &I, MachineRegisterInfo &MRI,
MachineIRBuilder MIB(I);
auto SubRegCopy =
- MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg);
+ MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, {}, SubReg);
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(SubRegCopy.getReg(0));
@@ -2807,7 +2807,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
if (SrcRB.getID() == AArch64::GPRRegBankID) {
auto NewI =
MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
- .addUse(SrcReg, 0,
+ .addUse(SrcReg, {},
Offset == 0 ? AArch64::sube64 : AArch64::subo64);
constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *NewI,
AArch64::GPR64RegClass, NewI->getOperand(0));
@@ -2839,7 +2839,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator()));
MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
- .addReg(DstReg, 0, AArch64::sub_32);
+ .addReg(DstReg, {}, AArch64::sub_32);
RBI.constrainGenericRegister(I.getOperand(0).getReg(),
AArch64::GPR32RegClass, MRI);
I.getOperand(0).setReg(DstReg);
@@ -2982,7 +2982,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
// Emit a subreg copy of 32 bits.
Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
MIB.buildInstr(TargetOpcode::COPY, {NewVal}, {})
- .addReg(I.getOperand(0).getReg(), 0, AArch64::sub_32);
+ .addReg(I.getOperand(0).getReg(), {}, AArch64::sub_32);
I.getOperand(0).setReg(NewVal);
}
I.setDesc(TII.get(Opcodes[Log2_32(MemSizeInBytes)]));
@@ -3016,7 +3016,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
// Generate a subreg copy.
auto Copy = MIB.buildInstr(TargetOpcode::COPY, {MemTy}, {})
- .addReg(ValReg, 0, SubReg)
+ .addReg(ValReg, {}, SubReg)
.getReg(0);
RBI.constrainGenericRegister(Copy, *RC, MRI);
LdSt.getOperand(0).setReg(Copy);
@@ -3154,7 +3154,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
assert(!ShiftTy.isVector() && "unexpected vector shift ty");
// Insert a subregister copy to implement a 64->32 trunc
auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
- .addReg(ShiftReg, 0, AArch64::sub_32);
+ .addReg(ShiftReg, {}, AArch64::sub_32);
MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
I.getOperand(2).setReg(Trunc.getReg(0));
}
@@ -3833,7 +3833,7 @@ AArch64InstructionSelector::emitNarrowVector(Register DstReg, Register SrcReg,
return nullptr;
}
auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
- .addReg(SrcReg, 0, SubReg);
+ .addReg(SrcReg, {}, SubReg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
return Copy;
}
@@ -3971,7 +3971,7 @@ MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
// If the lane index is 0, we just use a subregister COPY.
if (LaneIdx == 0) {
auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {})
- .addReg(VecReg, 0, ExtractSubReg);
+ .addReg(VecReg, {}, ExtractSubReg);
RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
return &*Copy;
}
@@ -4153,7 +4153,7 @@ bool AArch64InstructionSelector::selectUnmergeValues(MachineInstr &I,
// Perform the first copy separately as a subregister copy.
Register CopyTo = I.getOperand(0).getReg();
auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})
- .addReg(InsertRegs[0], 0, ExtractSubReg);
+ .addReg(InsertRegs[0], {}, ExtractSubReg);
constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);
// Now, perform the remaining copies as vector lane copies.
@@ -5184,7 +5184,7 @@ bool AArch64InstructionSelector::selectShuffleVector(
auto Copy =
MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
- .addReg(TBL1.getReg(0), 0, AArch64::dsub);
+ .addReg(TBL1.getReg(0), {}, AArch64::dsub);
RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
I.eraseFromParent();
return true;
@@ -5699,7 +5699,7 @@ AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
.buildInstr(AArch64::MOVIv2d_ns, {&AArch64::FPR128RegClass}, {})
.addImm(0);
auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {Dst}, {})
- .addReg(Mov.getReg(0), 0, AArch64::dsub);
+ .addReg(Mov.getReg(0), {}, AArch64::dsub);
RBI.constrainGenericRegister(Dst, AArch64::FPR64RegClass, MRI);
return &*Copy;
}
@@ -5923,7 +5923,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
Register Reg = MRI.createVirtualRegister(RC);
Register DstReg = I.getOperand(0).getReg();
- MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg);
+ MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, {}, SubReg);
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(Reg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
@@ -5975,7 +5975,7 @@ bool AArch64InstructionSelector::selectVectorLoadIntrinsic(unsigned Opc,
Register SelectedLoadDst = Load->getOperand(0).getReg();
for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
auto Vec = MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(Idx)}, {})
- .addReg(SelectedLoadDst, 0, SubReg + Idx);
+ .addReg(SelectedLoadDst, {}, SubReg + Idx);
// Emit the subreg copies and immediately select them.
// FIXME: We should refactor our copy code into an emitCopy helper and
// clean up uses of this pattern elsewhere in the selector.
@@ -6026,7 +6026,7 @@ bool AArch64InstructionSelector::selectVectorLoadLaneIntrinsic(
{Narrow ? DstOp(&AArch64::FPR128RegClass)
: DstOp(I.getOperand(Idx).getReg())},
{})
- .addReg(SelectedLoadDst, 0, SubReg + Idx);
+ .addReg(SelectedLoadDst, {}, SubReg + Idx);
Register WideReg = Vec.getReg(0);
// Emit the subreg copies and immediately select them.
selectCopy(*Vec, TII, MRI, TRI, RBI);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index db0b6cbdae036..e239e6f56cb44 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -365,7 +365,7 @@ AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
Register Reg = MO.getReg();
BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
- .addReg(Reg, 0, ComposedSubIdx);
+ .addReg(Reg, {}, ComposedSubIdx);
return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
MO.isKill(), MO.isDead(), MO.isUndef(),
@@ -652,7 +652,7 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
*SrcRC, I.getOperand(1));
const DebugLoc &DL = I.getDebugLoc();
BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY), DstReg)
- .addReg(SrcReg, 0, SubReg);
+ .addReg(SrcReg, {}, SubReg);
I.eraseFromParent();
return true;
@@ -725,7 +725,7 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
for (int I = 0, E = NumDst; I != E; ++I) {
MachineOperand &Dst = MI.getOperand(I);
BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
- .addReg(SrcReg, 0, SubRegs[I]);
+ .addReg(SrcReg, {}, SubRegs[I]);
// Make sure the subregister index is valid for the source register.
SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
@@ -2508,7 +2508,7 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
const DebugLoc &DL = I.getDebugLoc();
MachineBasicBlock *MBB = I.getParent();
BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), DstReg)
- .addReg(SrcReg, 0, AMDGPU::lo16);
+ .addReg(SrcReg, {}, AMDGPU::lo16);
I.eraseFromParent();
return true;
}
@@ -2520,9 +2520,9 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
Register LoReg = MRI->createVirtualRegister(DstRC);
Register HiReg = MRI->createVirtualRegister(DstRC);
BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg)
- .addReg(SrcReg, 0, AMDGPU::sub0);
+ .addReg(SrcReg, {}, AMDGPU::sub0);
BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg)
- .addReg(SrcReg, 0, AMDGPU::sub1);
+ .addReg(SrcReg, {}, AMDGPU::sub1);
if (IsVALU && STI.hasSDWA()) {
// Write the low 16-bits of the high element into the high 16-bits of the
@@ -2714,18 +2714,18 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
unsigned SubReg = InReg ? AMDGPU::sub0 : AMDGPU::NoSubRegister;
if (Signed) {
BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg)
- .addReg(SrcReg, 0, SubReg)
- .addImm(31)
- .setOperandDead(3); // Dead scc
+ .addReg(SrcReg, {}, SubReg)
+ .addImm(31)
+ .setOperandDead(3); // Dead scc
} else {
BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
.addImm(0);
}
BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
- .addReg(SrcReg, 0, SubReg)
- .addImm(AMDGPU::sub0)
- .addReg(HiReg)
- .addImm(AMDGPU::sub1);
+ .addReg(SrcReg, {}, SubReg)
+ .addImm(AMDGPU::sub0)
+ .addReg(HiReg)
+ .addImm(AMDGPU::sub1);
I.eraseFromParent();
return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass,
*MRI);
@@ -2743,10 +2743,10 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
- .addReg(SrcReg, 0, SubReg)
- .addImm(AMDGPU::sub0)
- .addReg(UndefReg)
- .addImm(AMDGPU::sub1);
+ .addReg(SrcReg, {}, SubReg)
+ .addImm(AMDGPU::sub0)
+ .addReg(UndefReg)
+ .addImm(AMDGPU::sub1);
BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
.addReg(ExtReg)
@@ -2880,9 +2880,9 @@ bool AMDGPUInstructionSelector::selectG_FNEG(MachineInstr &MI) const {
Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg)
- .addReg(Src, 0, AMDGPU::sub0);
+ .addReg(Src, {}, AMDGPU::sub0);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
- .addReg(Src, 0, AMDGPU::sub1);
+ .addReg(Src, {}, AMDGPU::sub1);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), ConstReg)
.addImm(0x80000000);
@@ -2922,9 +2922,9 @@ bool AMDGPUInstructionSelector::selectG_FABS(MachineInstr &MI) const {
return false;
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg)
- .addReg(Src, 0, AMDGPU::sub0);
+ .addReg(Src, {}, AMDGPU::sub0);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
- .addReg(Src, 0, AMDGPU::sub1);
+ .addReg(Src, {}, AMDGPU::sub1);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), ConstReg)
.addImm(0x7fffffff);
@@ -3199,9 +3199,9 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
// Extract the subregisters from the source pointer.
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
- .addReg(SrcReg, 0, AMDGPU::sub0);
+ .addReg(SrcReg, {}, AMDGPU::sub0);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
- .addReg(SrcReg, 0, AMDGPU::sub1);
+ .addReg(SrcReg, {}, AMDGPU::sub1);
Register MaskedLo, MaskedHi;
@@ -3214,7 +3214,7 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
MaskedLo = MRI->createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo)
- .addReg(MaskReg, 0, AMDGPU::sub0);
+ .addReg(MaskReg, {}, AMDGPU::sub0);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedLo)
.addReg(LoReg)
.addReg(MaskLo);
@@ -3228,7 +3228,7 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
MaskedHi = MRI->createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi)
- .addReg(MaskReg, 0, AMDGPU::sub1);
+ .addReg(MaskReg, {}, AMDGPU::sub1);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedHi)
.addReg(HiReg)
.addReg(MaskHi);
@@ -3316,8 +3316,8 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
unsigned Opc = Is64 ? AMDGPU::S_MOVRELS_B64 : AMDGPU::S_MOVRELS_B32;
BuildMI(*BB, &MI, DL, TII.get(Opc), DstReg)
- .addReg(SrcReg, 0, SubReg)
- .addReg(SrcReg, RegState::Implicit);
+ .addReg(SrcReg, {}, SubReg)
+ .addReg(SrcReg, RegState::Implicit);
MI.eraseFromParent();
return true;
}
@@ -3329,8 +3329,8 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
.addReg(IdxReg);
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::V_MOVRELS_B32_e32), DstReg)
- .addReg(SrcReg, 0, SubReg)
- .addReg(SrcReg, RegState::Implicit);
+ .addReg(SrcReg, {}, SubReg)
+ .addReg(SrcReg, RegState::Implicit);
MI.eraseFromParent();
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7470fecd3c03f..f3988047b8053 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1870,11 +1870,11 @@ bool AMDGPURegisterBankInfo::buildVCopy(MachineIRBuilder &B, Register DstReg,
Register TmpReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
B.buildInstr(AMDGPU::V_MOV_B32_e32)
- .addDef(TmpReg0)
- .addUse(SrcReg, 0, AMDGPU::sub0);
+ .addDef(TmpReg0)
+ .addUse(SrcReg, {}, AMDGPU::sub0);
B.buildInstr(AMDGPU::V_MOV_B32_e32)
- .addDef(TmpReg1)
- .addUse(SrcReg, 0, AMDGPU::sub1);
+ .addDef(TmpReg1)
+ .addUse(SrcReg, {}, AMDGPU::sub1);
B.buildInstr(AMDGPU::REG_SEQUENCE)
.addDef(DstReg)
.addUse(TmpReg0)
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 1d6f2ec3b3aa5..6ba669f076085 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -43,6 +43,7 @@
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 9838f1b1ef32a..f2ce5bf2b79cc 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -16,6 +16,7 @@
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/TargetParser/TargetParser.h"
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index ebc90eeb9e3f2..d02f52355635a 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -2262,8 +2262,8 @@ bool RewriteMFMAFormStage::rewrite(
MachineInstrBuilder VGPRCopy =
BuildMI(*RD->getParent(), std::next(RD->getIterator()),
RD->getDebugLoc(), TII->get(TargetOpcode::COPY))
- .addDef(MappedReg, 0, 0)
- .addUse(Src2Reg, 0, 0);
+ .addDef(MappedReg, {}, 0)
+ .addUse(Src2Reg, {}, 0);
DAG.LIS->InsertMachineInstrInMaps(*VGPRCopy);
// If this reaching def was the last MI in the region, update the
@@ -2345,8 +2345,8 @@ bool RewriteMFMAFormStage::rewrite(
MachineInstrBuilder VGPRCopy =
BuildMI(*RD->getParent(), std::next(RD->getIterator()),
RD->getDebugLoc(), TII->get(TargetOpcode::COPY))
- .addDef(MappedReg, 0, 0)
- .addUse(DstReg, 0, 0);
+ .addDef(MappedReg, {}, 0)
+ .addUse(DstReg, {}, 0);
DAG.LIS->InsertMachineInstrInMaps(*VGPRCopy);
// If this reaching def was the last MI in the region, update the
@@ -2381,8 +2381,8 @@ bool RewriteMFMAFormStage::rewrite(
MachineInstrBuilder VGPRCopy =
BuildMI(*UseInst->getParent(), UseInst->getIterator(),
UseInst->getDebugLoc(), TII->get(TargetOpcode::COPY))
- .addDef(NewUseReg, 0, 0)
- .addUse(DstReg, 0, 0);
+ .addDef(NewUseReg, {}, 0)
+ .addUse(DstReg, {}, 0);
DAG.LIS->InsertMachineInstrInMaps(*VGPRCopy);
// Since we know this use has only one reaching def, we can replace the
// use reg.
@@ -2424,8 +2424,8 @@ bool RewriteMFMAFormStage::rewrite(
MachineInstrBuilder VGPRCopy =
BuildMI(*UseInst->getParent(), UseInst->getIterator(),
UseInst->getDebugLoc(), TII->get(TargetOpcode::COPY))
- .addDef(NewUseReg, 0, 0)
- .addUse(RUDst.first, 0, 0);
+ .addDef(NewUseReg, {}, 0)
+ .addUse(RUDst.first, {}, 0);
DAG.LIS->InsertMachineInstrInMaps(*VGPRCopy);
// If this UseInst was the first MI in the region, update the region
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 5ae02d025989b..074c404349234 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1129,7 +1129,7 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_16RegClass);
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), Undef);
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), VReg32)
- .addReg(SrcReg, 0, SubReg)
+ .addReg(SrcReg, {}, SubReg)
.addImm(AMDGPU::lo16)
.addReg(Undef)
.addImm(AMDGPU::hi16);
@@ -1140,7 +1140,7 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
TII->get(AMDGPU::V_READFIRSTLANE_B32);
const TargetRegisterClass *OpRC = TII->getRegClass(ReadFirstLaneDesc, 1);
BuildMI(*MBB, MI, MI->getDebugLoc(), ReadFirstLaneDesc, DstReg)
- .addReg(SrcReg, 0, SubReg);
+ .addReg(SrcReg, {}, SubReg);
const TargetRegisterClass *ConstrainRC =
SubReg == AMDGPU::NoSubRegister
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 74cfcd7b80565..43cf49a1a3dc3 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2433,7 +2433,7 @@ bool SIFoldOperandsImpl::tryFoldRegSequence(MachineInstr &MI) {
} else { // This is a copy
MachineInstr *SubDef = MRI->getVRegDef(Def->getReg());
SubDef->getOperand(1).setIsKill(false);
- RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());
+ RS.addReg(SubDef->getOperand(1).getReg(), {}, Def->getSubReg());
}
RS.addImm(SubIdx);
}
@@ -2757,7 +2757,7 @@ bool SIFoldOperandsImpl::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
MachineInstr *VGPRCopy =
BuildMI(*DefMBB, ++Def->getIterator(), Def->getDebugLoc(),
TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), TempVGPR)
- .addReg(Reg, /* flags */ 0, SubReg);
+ .addReg(Reg, /* flags */ {}, SubReg);
// Copy back to an AGPR and use that instead of the AGPR subreg in all MOs.
Register TempAGPR = MRI->createVirtualRegister(ARC);
diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index 6b13b06590102..e9aec826f5c72 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -33,7 +33,7 @@ MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15),
namespace {
class SIFormMemoryClausesImpl {
- using RegUse = DenseMap<unsigned, std::pair<unsigned, LaneBitmask>>;
+ using RegUse = DenseMap<unsigned, std::pair<RegState, LaneBitmask>>;
bool canBundle(const MachineInstr &MI, const RegUse &Defs,
const RegUse &Uses) const;
@@ -132,8 +132,8 @@ static bool isValidClauseInst(const MachineInstr &MI, bool IsVMEMClause) {
return true;
}
-static unsigned getMopState(const MachineOperand &MO) {
- unsigned S = 0;
+static RegState getMopState(const MachineOperand &MO) {
+ RegState S = {};
if (MO.isImplicit())
S |= RegState::Implicit;
if (MO.isDead())
@@ -234,7 +234,7 @@ void SIFormMemoryClausesImpl::collectRegUses(const MachineInstr &MI,
: LaneBitmask::getAll();
RegUse &Map = MO.isDef() ? Defs : Uses;
- unsigned State = getMopState(MO);
+ RegState State = getMopState(MO);
auto [Loc, Inserted] = Map.try_emplace(Reg, State, Mask);
if (!Inserted) {
Loc->second.first |= State;
@@ -349,7 +349,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
continue;
// Collect the register operands we should extend the live ranges of.
- SmallVector<std::tuple<unsigned, unsigned>> KillOps;
+ SmallVector<std::tuple<RegState, unsigned>> KillOps;
const LiveInterval &LI = LIS->getInterval(R.first);
if (!LI.hasSubRanges()) {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e9c46e53affe4..657eec1d93076 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5080,7 +5080,7 @@ emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI,
// Compare the just read M0 value to all possible Idx values.
BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
.addReg(CurrentIdxReg)
- .addReg(Idx.getReg(), 0, Idx.getSubReg());
+ .addReg(Idx.getReg(), {}, Idx.getSubReg());
// Update EXEC, save the original EXEC value to VCC.
BuildMI(LoopBB, I, DL, TII->get(LMC.AndSaveExecOpc), NewExec)
@@ -5281,7 +5281,7 @@ static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
- .addReg(SrcReg, 0, SubReg)
+ .addReg(SrcReg, {}, SubReg)
.addReg(SrcReg, RegState::Implicit);
}
@@ -5315,7 +5315,7 @@ static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
.addImm(SubReg);
} else {
BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
- .addReg(SrcReg, 0, SubReg)
+ .addReg(SrcReg, {}, SubReg)
.addReg(SrcReg, RegState::Implicit);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 82df7cd7b443c..2e7a81a9ef3ee 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2983,11 +2983,11 @@ void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
MCCtx.createTempSymbol("offset_hi", /*AlwaysAddSuffix=*/true);
BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub0)
- .addReg(PCReg, 0, AMDGPU::sub0)
+ .addReg(PCReg, {}, AMDGPU::sub0)
.addSym(OffsetLo, MO_FAR_BRANCH_OFFSET);
BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub1)
- .addReg(PCReg, 0, AMDGPU::sub1)
+ .addReg(PCReg, {}, AMDGPU::sub1)
.addSym(OffsetHi, MO_FAR_BRANCH_OFFSET);
ApplyHazardWorkarounds();
@@ -3407,15 +3407,13 @@ void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
MachineInstr *Select;
if (SelOp == AMDGPU::V_CNDMASK_B32_e32) {
- Select =
- BuildMI(MBB, I, DL, get(SelOp), DstElt)
- .addReg(FalseReg, 0, SubIdx)
- .addReg(TrueReg, 0, SubIdx);
+ Select = BuildMI(MBB, I, DL, get(SelOp), DstElt)
+ .addReg(FalseReg, {}, SubIdx)
+ .addReg(TrueReg, {}, SubIdx);
} else {
- Select =
- BuildMI(MBB, I, DL, get(SelOp), DstElt)
- .addReg(TrueReg, 0, SubIdx)
- .addReg(FalseReg, 0, SubIdx);
+ Select = BuildMI(MBB, I, DL, get(SelOp), DstElt)
+ .addReg(TrueReg, {}, SubIdx)
+ .addReg(FalseReg, {}, SubIdx);
}
preserveCondRegFlags(Select->getOperand(3), Cond[1]);
@@ -6222,7 +6220,7 @@ unsigned SIInstrInfo::buildExtractSubReg(
unsigned NewSubIdx = RI.composeSubRegIndices(SuperReg.getSubReg(), SubIdx);
BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
- .addReg(SuperReg.getReg(), 0, NewSubIdx);
+ .addReg(SuperReg.getReg(), {}, NewSubIdx);
return SubReg;
}
@@ -6818,7 +6816,7 @@ Register SIInstrInfo::readlaneVGPRToSGPR(
Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
- .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
+ .addReg(SrcReg, {}, RI.getSubRegFromChannel(i));
SRegs.push_back(SGPR);
}
@@ -7046,7 +7044,7 @@ emitLoadScalarOpsFromVGPRLoop(const SIInstrInfo &TII,
ScalarOp->setIsKill();
} else {
SmallVector<Register, 8> ReadlanePieces;
- unsigned VScalarOpUndef = getUndefRegState(ScalarOp->isUndef());
+ RegState VScalarOpUndef = getUndefRegState(ScalarOp->isUndef());
assert(NumSubRegs % 2 == 0 && NumSubRegs <= 32 &&
"Unhandled register size");
@@ -7574,18 +7572,18 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
// NewVaddrLo = RsrcPtr:sub0 + VAddr:sub0
const DebugLoc &DL = MI.getDebugLoc();
BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_CO_U32_e64), NewVAddrLo)
- .addDef(CondReg0)
- .addReg(RsrcPtr, 0, AMDGPU::sub0)
- .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
- .addImm(0);
+ .addDef(CondReg0)
+ .addReg(RsrcPtr, {}, AMDGPU::sub0)
+ .addReg(VAddr->getReg(), {}, AMDGPU::sub0)
+ .addImm(0);
// NewVaddrHi = RsrcPtr:sub1 + VAddr:sub1
BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e64), NewVAddrHi)
- .addDef(CondReg1, RegState::Dead)
- .addReg(RsrcPtr, 0, AMDGPU::sub1)
- .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
- .addReg(CondReg0, RegState::Kill)
- .addImm(0);
+ .addDef(CondReg1, RegState::Dead)
+ .addReg(RsrcPtr, {}, AMDGPU::sub1)
+ .addReg(VAddr->getReg(), {}, AMDGPU::sub1)
+ .addReg(CondReg0, RegState::Kill)
+ .addImm(0);
// NewVaddr = {NewVaddrHi, NewVaddrLo}
BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
@@ -7658,9 +7656,9 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
// NewVaddr = {NewVaddrHi, NewVaddrLo}
BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
NewVAddr)
- .addReg(RsrcPtr, 0, AMDGPU::sub0)
+ .addReg(RsrcPtr, {}, AMDGPU::sub0)
.addImm(AMDGPU::sub0)
- .addReg(RsrcPtr, 0, AMDGPU::sub1)
+ .addReg(RsrcPtr, {}, AMDGPU::sub1)
.addImm(AMDGPU::sub1);
} else {
// Legalize a VGPR Rsrc and soffset together.
@@ -8175,7 +8173,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
.add(Inst.getOperand(1));
BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
.addImm(0) // src0_modifiers
- .addReg(TmpReg, 0, AMDGPU::hi16)
+ .addReg(TmpReg, {}, AMDGPU::hi16)
.addImm(0) // clamp
.addImm(0) // omod
.addImm(0); // op_sel0
@@ -9151,7 +9149,7 @@ void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,
Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32_e64), MidRegLo)
- .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
+ .addReg(Inst.getOperand(1).getReg(), {}, AMDGPU::sub0)
.addImm(0)
.addImm(BitWidth);
@@ -9175,14 +9173,14 @@ void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,
Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
- .addImm(31)
- .addReg(Src.getReg(), 0, AMDGPU::sub0);
+ .addImm(31)
+ .addReg(Src.getReg(), {}, AMDGPU::sub0);
BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
- .addReg(Src.getReg(), 0, AMDGPU::sub0)
- .addImm(AMDGPU::sub0)
- .addReg(TmpReg)
- .addImm(AMDGPU::sub1);
+ .addReg(Src.getReg(), {}, AMDGPU::sub0)
+ .addImm(AMDGPU::sub0)
+ .addReg(TmpReg)
+ .addImm(AMDGPU::sub1);
MRI.replaceRegWith(Dest.getReg(), ResultReg);
addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
@@ -9309,32 +9307,32 @@ void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,
switch (Inst.getOpcode()) {
case AMDGPU::S_PACK_LL_B32_B16:
NewMI
- .addReg(SrcReg0, 0,
+ .addReg(SrcReg0, {},
isSrc0Reg16 ? AMDGPU::NoSubRegister : AMDGPU::lo16)
.addImm(AMDGPU::lo16)
- .addReg(SrcReg1, 0,
+ .addReg(SrcReg1, {},
isSrc1Reg16 ? AMDGPU::NoSubRegister : AMDGPU::lo16)
.addImm(AMDGPU::hi16);
break;
case AMDGPU::S_PACK_LH_B32_B16:
NewMI
- .addReg(SrcReg0, 0,
+ .addReg(SrcReg0, {},
isSrc0Reg16 ? AMDGPU::NoSubRegister : AMDGPU::lo16)
.addImm(AMDGPU::lo16)
- .addReg(SrcReg1, 0, AMDGPU::hi16)
+ .addReg(SrcReg1, {}, AMDGPU::hi16)
.addImm(AMDGPU::hi16);
break;
case AMDGPU::S_PACK_HL_B32_B16:
- NewMI.addReg(SrcReg0, 0, AMDGPU::hi16)
+ NewMI.addReg(SrcReg0, {}, AMDGPU::hi16)
.addImm(AMDGPU::lo16)
- .addReg(SrcReg1, 0,
+ .addReg(SrcReg1, {},
isSrc1Reg16 ? AMDGPU::NoSubRegister : AMDGPU::lo16)
.addImm(AMDGPU::hi16);
break;
case AMDGPU::S_PACK_HH_B32_B16:
- NewMI.addReg(SrcReg0, 0, AMDGPU::hi16)
+ NewMI.addReg(SrcReg0, {}, AMDGPU::hi16)
.addImm(AMDGPU::lo16)
- .addReg(SrcReg1, 0, AMDGPU::hi16)
+ .addReg(SrcReg1, {}, AMDGPU::hi16)
.addImm(AMDGPU::hi16);
break;
default:
@@ -10542,7 +10540,7 @@ MachineInstr *SIInstrInfo::createPHISourceCopy(
InsPt++;
return BuildMI(MBB, InsPt, DL,
get(AMDGPU::LaneMaskConstants::get(ST).MovTermOpc), Dst)
- .addReg(Src, 0, SrcSubReg)
+ .addReg(Src, {}, SrcSubReg)
.addReg(AMDGPU::EXEC, RegState::Implicit);
}
return TargetInstrInfo::createPHISourceCopy(MBB, InsPt, DL, Src, SrcSubReg,
@@ -11184,7 +11182,7 @@ void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,
MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass
: &AMDGPU::VReg_64_Align2RegClass);
BuildMI(*BB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewVR)
- .addReg(DataReg, 0, Op.getSubReg())
+ .addReg(DataReg, {}, Op.getSubReg())
.addImm(AMDGPU::sub0)
.addReg(Undef)
.addImm(AMDGPU::sub1);
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index dc1592e5fb82a..9610cd6c9d2e0 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -1385,7 +1385,7 @@ void SILoadStoreOptimizer::copyToDestRegs(
BuildMI(*MBB, InsertBefore, DL, CopyDesc)
.add(*Dest0) // Copy to same destination including flags and sub reg.
- .addReg(DestReg, 0, SubRegIdx0);
+ .addReg(DestReg, {}, SubRegIdx0);
BuildMI(*MBB, InsertBefore, DL, CopyDesc)
.add(*Dest1)
.addReg(DestReg, RegState::Kill, SubRegIdx1);
@@ -1459,7 +1459,7 @@ SILoadStoreOptimizer::mergeRead2Pair(CombineInfo &CI, CombineInfo &Paired,
Register BaseReg = AddrReg->getReg();
unsigned BaseSubReg = AddrReg->getSubReg();
- unsigned BaseRegFlags = 0;
+ RegState BaseRegFlags = {};
if (CI.BaseOff) {
Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
@@ -1470,7 +1470,7 @@ SILoadStoreOptimizer::mergeRead2Pair(CombineInfo &CI, CombineInfo &Paired,
TII->getAddNoCarry(*MBB, InsertBefore, DL, BaseReg)
.addReg(ImmReg)
- .addReg(AddrReg->getReg(), 0, BaseSubReg)
+ .addReg(AddrReg->getReg(), {}, BaseSubReg)
.addImm(0); // clamp bit
BaseSubReg = 0;
}
@@ -1545,7 +1545,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
Register BaseReg = AddrReg->getReg();
unsigned BaseSubReg = AddrReg->getSubReg();
- unsigned BaseRegFlags = 0;
+ RegState BaseRegFlags = {};
if (CI.BaseOff) {
Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
@@ -1556,7 +1556,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
TII->getAddNoCarry(*MBB, InsertBefore, DL, BaseReg)
.addReg(ImmReg)
- .addReg(AddrReg->getReg(), 0, BaseSubReg)
+ .addReg(AddrReg->getReg(), {}, BaseSubReg)
.addImm(0); // clamp bit
BaseSubReg = 0;
}
@@ -2185,21 +2185,21 @@ Register SILoadStoreOptimizer::computeBase(MachineInstr &MI,
Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
MachineInstr *LoHalf =
- BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0)
- .addReg(CarryReg, RegState::Define)
- .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg)
- .add(OffsetLo)
- .addImm(0); // clamp bit
+ BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0)
+ .addReg(CarryReg, RegState::Define)
+ .addReg(Addr.Base.LoReg, {}, Addr.Base.LoSubReg)
+ .add(OffsetLo)
+ .addImm(0); // clamp bit
(void)LoHalf;
LLVM_DEBUG(dbgs() << " "; LoHalf->dump(););
MachineInstr *HiHalf =
- BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1)
- .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
- .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg)
- .add(OffsetHi)
- .addReg(CarryReg, RegState::Kill)
- .addImm(0); // clamp bit
+ BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1)
+ .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
+ .addReg(Addr.Base.HiReg, {}, Addr.Base.HiSubReg)
+ .add(OffsetHi)
+ .addReg(CarryReg, RegState::Kill)
+ .addImm(0); // clamp bit
(void)HiHalf;
LLVM_DEBUG(dbgs() << " "; HiHalf->dump(););
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 64f2b08672030..96c2f6530fe4c 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1733,8 +1733,8 @@ void SIRegisterInfo::buildSpillLoadStore(
: Register(getSubReg(ValueReg,
getSubRegFromChannel(RegOffset / 4, NumRegs)));
- unsigned SOffsetRegState = 0;
- unsigned SrcDstRegState = getDefRegState(!IsStore);
+ RegState SOffsetRegState = {};
+ RegState SrcDstRegState = getDefRegState(!IsStore);
const bool IsLastSubReg = i + 1 == e;
const bool IsFirstSubReg = i == 0;
if (IsLastSubReg) {
@@ -1774,7 +1774,7 @@ void SIRegisterInfo::buildSpillLoadStore(
}
if ((IsSubReg || NeedSuperRegImpOperand) && (IsFirstSubReg || IsLastSubReg)) {
NeedSuperRegImpOperand = true;
- unsigned State = SrcDstRegState;
+ RegState State = SrcDstRegState;
if (!IsLastSubReg || (Lane != LaneE))
State &= ~RegState::Kill;
if (!IsFirstSubReg || (Lane != LaneS))
@@ -1897,7 +1897,7 @@ void SIRegisterInfo::buildSpillLoadStore(
MIB->setAsmPrinterFlag(MachineInstr::ReloadReuse);
}
- bool IsSrcDstDef = SrcDstRegState & RegState::Define;
+ bool IsSrcDstDef = hasRegState(SrcDstRegState, RegState::Define);
bool PartialReloadCopy = (RemEltSize != EltSize) && !IsStore;
if (NeedSuperRegImpOperand &&
(IsFirstSubReg || (IsLastSubReg && !IsSrcDstDef))) {
@@ -2069,13 +2069,13 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
SB.prepare();
// SubReg carries the "Kill" flag when SubReg == SB.SuperReg.
- unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
+ RegState SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
// Per VGPR helper data
auto PVD = SB.getPerVGPRData();
for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
- unsigned TmpVGPRFlags = RegState::Undef;
+ RegState TmpVGPRFlags = RegState::Undef;
// Write sub registers into the VGPR
for (unsigned i = Offset * PVD.PerVGPR,
@@ -2092,7 +2092,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
.addReg(SubReg, SubKillState)
.addImm(i % PVD.PerVGPR)
.addReg(SB.TmpVGPR, TmpVGPRFlags);
- TmpVGPRFlags = 0;
+ TmpVGPRFlags = {};
if (Indexes) {
if (i == 0)
@@ -2105,7 +2105,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
// TODO: Can we detect this and skip the spill?
if (SB.NumSubRegs > 1) {
// The last implicit use of the SB.SuperReg carries the "Kill" flag.
- unsigned SuperKillState = 0;
+ RegState SuperKillState = {};
if (i + 1 == SB.NumSubRegs)
SuperKillState |= getKillRegState(SB.IsKill);
WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
@@ -2215,10 +2215,10 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI,
RS);
SB.prepare();
// Generate the spill of SGPR to SB.TmpVGPR.
- unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
+ RegState SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
auto PVD = SB.getPerVGPRData();
for (unsigned Offset = 0; Offset < PVD.NumVGPRs; ++Offset) {
- unsigned TmpVGPRFlags = RegState::Undef;
+ RegState TmpVGPRFlags = RegState::Undef;
// Write sub registers into the VGPR
for (unsigned i = Offset * PVD.PerVGPR,
e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
@@ -2234,12 +2234,12 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI,
.addReg(SubReg, SubKillState)
.addImm(i % PVD.PerVGPR)
.addReg(SB.TmpVGPR, TmpVGPRFlags);
- TmpVGPRFlags = 0;
+ TmpVGPRFlags = {};
// There could be undef components of a spilled super register.
// TODO: Can we detect this and skip the spill?
if (SB.NumSubRegs > 1) {
// The last implicit use of the SB.SuperReg carries the "Kill" flag.
- unsigned SuperKillState = 0;
+ RegState SuperKillState = {};
if (i + 1 == SB.NumSubRegs)
SuperKillState |= getKillRegState(SB.IsKill);
WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
@@ -2668,7 +2668,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (NumDefs == 2)
AddI32.add(MI->getOperand(1));
- unsigned MaterializedRegFlags =
+ RegState MaterializedRegFlags =
getKillRegState(MaterializedReg != FrameReg);
if (isVGPRClass(getPhysRegBaseClass(MaterializedReg))) {
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 57f1096579669..5b32bd0b72a59 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -806,10 +806,10 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
Y1 = getSubRegForIndex(Y, Ysub, I);
auto *MIB = BuildMI(MBB, MovX->getIterator(), MovT.getDebugLoc(),
TII->get(AMDGPU::V_SWAP_B32))
- .addDef(X1.Reg, 0, X1.SubReg)
- .addDef(Y1.Reg, 0, Y1.SubReg)
- .addReg(Y1.Reg, 0, Y1.SubReg)
- .addReg(X1.Reg, 0, X1.SubReg)
+ .addDef(X1.Reg, {}, X1.SubReg)
+ .addDef(Y1.Reg, {}, Y1.SubReg)
+ .addReg(Y1.Reg, {}, Y1.SubReg)
+ .addReg(X1.Reg, {}, X1.SubReg)
.getInstr();
Swaps.push_back(MIB);
}
diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
index f6705669714da..cd775dd5aa7a6 100644
--- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp
+++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
@@ -432,11 +432,8 @@ unsigned A15SDOptimizer::createExtractSubreg(
const DebugLoc &DL, unsigned DReg, unsigned Lane,
const TargetRegisterClass *TRC) {
Register Out = MRI->createVirtualRegister(TRC);
- BuildMI(MBB,
- InsertBefore,
- DL,
- TII->get(TargetOpcode::COPY), Out)
- .addReg(DReg, 0, Lane);
+ BuildMI(MBB, InsertBefore, DL, TII->get(TargetOpcode::COPY), Out)
+ .addReg(DReg, {}, Lane);
return Out;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 402a4e30fe3ca..103744cdf90aa 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -932,7 +932,7 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
const MachineInstrBuilder &ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB,
unsigned Reg,
unsigned SubIdx,
- unsigned State) const {
+ RegState State) const {
if (!SubIdx)
return MIB.addReg(Reg, State);
@@ -1012,7 +1012,7 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (Subtarget.hasV5TEOps()) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
- AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
+ AddDReg(MIB, SrcReg, ARM::gsub_1, {});
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
@@ -1023,7 +1023,7 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
- AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
+ AddDReg(MIB, SrcReg, ARM::gsub_1, {});
}
} else
llvm_unreachable("Unknown reg class!");
@@ -1074,8 +1074,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, {});
+ AddDReg(MIB, SrcReg, ARM::dsub_2, {});
}
} else
llvm_unreachable("Unknown reg class!");
@@ -1106,9 +1106,9 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, {});
+ AddDReg(MIB, SrcReg, ARM::dsub_3, {});
}
} else
llvm_unreachable("Unknown reg class!");
@@ -1126,13 +1126,13 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_7, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, {});
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, {});
+ AddDReg(MIB, SrcReg, ARM::dsub_7, {});
} else
llvm_unreachable("Unknown reg class!");
break;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index ab94a113233dc..60ef40b459097 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -238,7 +238,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
const MachineInstr &Orig) const override;
const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
- unsigned SubIdx, unsigned State) const;
+ unsigned SubIdx, RegState State) const;
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
const MachineRegisterInfo *MRI) const override;
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index f4f07b4c19560..14e4c19a8ac1a 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -802,8 +802,8 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
// Add the subregs as sources of the new instruction.
- unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
- getKillRegState(MO.isKill()));
+ RegState SrcFlags =
+ (getUndefRegState(MO.isUndef()) | getKillRegState(MO.isKill()));
MIB.addReg(D0, SrcFlags);
if (NumRegs > 1)
MIB.addReg(D1, SrcFlags);
@@ -881,7 +881,7 @@ void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) {
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
- unsigned Flags = getKillRegState(MI.getOperand(0).isKill()) |
+ RegState Flags = getKillRegState(MI.getOperand(0).isKill()) |
getDefRegState(MI.getOperand(0).isDef());
Register SrcReg = MI.getOperand(0).getReg();
@@ -1962,7 +1962,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
/// single GPRPair register), Thumb's take two separate registers so we need to
/// extract the subregs from the pair.
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
- unsigned Flags, bool IsThumb,
+ RegState Flags, bool IsThumb,
const TargetRegisterInfo *TRI) {
if (IsThumb) {
Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
@@ -2044,7 +2044,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
// bne .Lloadcmp
unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
- unsigned Flags = getKillRegState(New.isDead());
+ RegState Flags = getKillRegState(New.isDead());
addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
@@ -2218,7 +2218,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
} else {
// Use move to satisfy constraints
unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
- unsigned MO1Flags = getRegState(MI.getOperand(1)) & ~RegState::Kill;
+ RegState MO1Flags = getRegState(MI.getOperand(1)) & ~RegState::Kill;
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc))
.addReg(DstReg,
RegState::Define |
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 62288248088e9..b5244bfb9a80d 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2805,7 +2805,7 @@ Register ARMFastISel::ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
if (setsCPSR)
MIB.addReg(ARM::CPSR, RegState::Define);
SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
- MIB.addReg(SrcReg, isKill * RegState::Kill)
+ MIB.addReg(SrcReg, getKillRegState(isKill))
.addImm(ImmEnc)
.add(predOps(ARMCC::AL));
if (hasS)
diff --git a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
index 0bb637edbae96..547205f900039 100644
--- a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
+++ b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
@@ -408,7 +408,7 @@ void ARMFixCortexA57AES1742098::insertAESFixup(
// The def and the uses are still marked as Renamable if the original register
// was, to avoid having to rummage through all the other uses and defs and
// unset their renamable bits.
- unsigned Renamable = getRenamableRegState(OperandToFixup->isRenamable());
+ RegState Renamable = getRenamableRegState(OperandToFixup->isRenamable());
BuildMI(*FixupLoc.Block, FixupLoc.InsertionPt, DebugLoc(),
TII->get(ARM::VORRq))
.addReg(RegToFixup, RegState::Define | Renamable)
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 76da9692fd9f6..206404ffb7b89 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -197,7 +197,7 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
- AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
+ AddDReg(MIB, SrcReg, ARM::gsub_1, {});
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
return;
}
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 904b080478e9f..5fbb14650d757 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -2005,8 +2005,8 @@ static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
ShrExtendReg = MRI.createVirtualRegister(&AVR::GPR8RegClass);
Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass);
BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp)
- .addReg(Regs[0].first, 0, Regs[0].second)
- .addReg(Regs[0].first, 0, Regs[0].second);
+ .addReg(Regs[0].first, {}, Regs[0].second)
+ .addReg(Regs[0].first, {}, Regs[0].second);
BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), ShrExtendReg)
.addReg(Tmp)
.addReg(Tmp);
@@ -2054,7 +2054,7 @@ static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
Register SwapReg = MRI.createVirtualRegister(&AVR::LD8RegClass);
BuildMI(*BB, MI, dl, TII.get(AVR::SWAPRd), SwapReg)
- .addReg(Regs[Idx].first, 0, Regs[Idx].second);
+ .addReg(Regs[Idx].first, {}, Regs[Idx].second);
if (I != 0) {
Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass);
BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R)
@@ -2090,12 +2090,12 @@ static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
Register InSubreg = Regs[I].second;
if (I == (ssize_t)Regs.size() - 1) { // first iteration
BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Out)
- .addReg(In, 0, InSubreg)
- .addReg(In, 0, InSubreg);
+ .addReg(In, {}, InSubreg)
+ .addReg(In, {}, InSubreg);
} else {
BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), Out)
- .addReg(In, 0, InSubreg)
- .addReg(In, 0, InSubreg);
+ .addReg(In, {}, InSubreg)
+ .addReg(In, {}, InSubreg);
}
Regs[I] = std::pair(Out, 0);
}
@@ -2109,9 +2109,9 @@ static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
Register InSubreg = Regs[I].second;
if (I == 0) {
unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
- BuildMI(*BB, MI, dl, TII.get(Opc), Out).addReg(In, 0, InSubreg);
+ BuildMI(*BB, MI, dl, TII.get(Opc), Out).addReg(In, {}, InSubreg);
} else {
- BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), Out).addReg(In, 0, InSubreg);
+ BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), Out).addReg(In, {}, InSubreg);
}
Regs[I] = std::pair(Out, 0);
}
@@ -2172,26 +2172,26 @@ AVRTargetLowering::insertWideShift(MachineInstr &MI,
(Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
// Use the resulting registers starting with the least significant byte.
BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
- .addReg(Registers[3].first, 0, Registers[3].second)
+ .addReg(Registers[3].first, {}, Registers[3].second)
.addImm(AVR::sub_lo)
- .addReg(Registers[2].first, 0, Registers[2].second)
+ .addReg(Registers[2].first, {}, Registers[2].second)
.addImm(AVR::sub_hi);
BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
- .addReg(Registers[1].first, 0, Registers[1].second)
+ .addReg(Registers[1].first, {}, Registers[1].second)
.addImm(AVR::sub_lo)
- .addReg(Registers[0].first, 0, Registers[0].second)
+ .addReg(Registers[0].first, {}, Registers[0].second)
.addImm(AVR::sub_hi);
} else {
// Use the resulting registers starting with the most significant byte.
BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
- .addReg(Registers[0].first, 0, Registers[0].second)
+ .addReg(Registers[0].first, {}, Registers[0].second)
.addImm(AVR::sub_hi)
- .addReg(Registers[1].first, 0, Registers[1].second)
+ .addReg(Registers[1].first, {}, Registers[1].second)
.addImm(AVR::sub_lo);
BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
- .addReg(Registers[2].first, 0, Registers[2].second)
+ .addReg(Registers[2].first, {}, Registers[2].second)
.addImm(AVR::sub_hi)
- .addReg(Registers[3].first, 0, Registers[3].second)
+ .addReg(Registers[3].first, {}, Registers[3].second)
.addImm(AVR::sub_lo);
}
diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
index 666a5b6abfa4a..c9b1cbc7ae959 100644
--- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
+++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
@@ -216,7 +216,7 @@ void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI,
}
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
- .addReg(SrcReg, 0, BPF::sub_32);
+ .addReg(SrcReg, {}, BPF::sub_32);
return;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 848337457c997..2e48fe64d15ae 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1351,7 +1351,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
Register NewR = MRI.createVirtualRegister(FRC);
MachineInstr *CopyI =
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
- .addReg(RS.Reg, 0, RS.Sub);
+ .addReg(RS.Reg, {}, RS.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
// This pass can create copies between registers that don't have the
// exact same values. Updating the tracker has to involve updating
@@ -1621,7 +1621,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
if (findMatch(R, MR, AVB)) {
Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
- .addReg(MR.Reg, 0, MR.Sub);
+ .addReg(MR.Reg, {}, MR.Sub);
BT.put(BitTracker::RegisterRef(NewR), BT.get(MR));
HBS::replaceReg(R, NewR, MRI);
Forbidden.insert(R);
@@ -1640,10 +1640,10 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
auto *FRC = HBS::getFinalVRegClass(R, MRI);
Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR)
- .addReg(ML.Reg, 0, ML.Sub)
- .addImm(SubLo)
- .addReg(MH.Reg, 0, MH.Sub)
- .addImm(SubHi);
+ .addReg(ML.Reg, {}, ML.Sub)
+ .addImm(SubLo)
+ .addReg(MH.Reg, {}, MH.Sub)
+ .addImm(SubHi);
BT.put(BitTracker::RegisterRef(NewR), BT.get(R));
HBS::replaceReg(R, NewR, MRI);
Forbidden.insert(R);
@@ -2041,8 +2041,8 @@ bool BitSimplification::genPackhl(MachineInstr *MI,
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR)
- .addReg(Rs.Reg, 0, Rs.Sub)
- .addReg(Rt.Reg, 0, Rt.Sub);
+ .addReg(Rs.Reg, {}, Rs.Sub)
+ .addReg(Rt.Reg, {}, Rt.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
BT.put(BitTracker::RegisterRef(NewR), RC);
return true;
@@ -2070,13 +2070,13 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI,
if (validateReg(L, Hexagon::A2_zxth, 1)) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
- .addReg(L.Reg, 0, L.Sub);
+ .addReg(L.Reg, {}, L.Sub);
}
} else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
if (validateReg(L, Hexagon::S2_lsr_i_r, 1)) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
- .addReg(L.Reg, 0, L.Sub)
+ .addReg(L.Reg, {}, L.Sub)
.addImm(16);
}
}
@@ -2112,8 +2112,8 @@ bool BitSimplification::genCombineHalf(MachineInstr *MI,
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
BuildMI(B, At, DL, HII.get(COpc), NewR)
- .addReg(H.Reg, 0, H.Sub)
- .addReg(L.Reg, 0, L.Sub);
+ .addReg(H.Reg, {}, H.Sub)
+ .addReg(L.Reg, {}, L.Sub);
HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
BT.put(BitTracker::RegisterRef(NewR), RC);
return true;
@@ -2168,8 +2168,8 @@ bool BitSimplification::genExtractLow(MachineInstr *MI,
Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
- auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
- .addReg(RS.Reg, 0, RS.Sub);
+ auto MIB =
+ BuildMI(B, At, DL, HII.get(NewOpc), NewR).addReg(RS.Reg, {}, RS.Sub);
if (NewOpc == Hexagon::A2_andir)
MIB.addImm((1 << W) - 1);
else if (NewOpc == Hexagon::S2_extractu)
@@ -2311,8 +2311,8 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
if (!NewR) {
NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR)
- .addReg(SrcR, 0, SrcSR)
- .addImm(ImmOp);
+ .addReg(SrcR, {}, SrcSR)
+ .addImm(ImmOp);
NewMIs.push_back(NewBS);
}
if (Pos <= P) {
@@ -2372,7 +2372,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
if (P != std::numeric_limits<unsigned>::max()) {
Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
- .addReg(RR.Reg, 0, RR.Sub)
+ .addReg(RR.Reg, {}, RR.Sub)
.addImm(P);
HBS::replaceReg(RD.Reg, NewR, MRI);
BT.put(NewR, RC);
@@ -2555,8 +2555,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
Register NewR = MRI.createVirtualRegister(FRC);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
- auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
- .addReg(R, 0, SR);
+ auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR).addReg(R, {}, SR);
switch (ExtOpc) {
case Hexagon::A2_sxtb:
case Hexagon::A2_zxtb:
@@ -3096,7 +3095,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
if (!Op.isUse())
continue;
unsigned UseR = RegMap[Op.getReg()];
- MIB.addReg(UseR, 0, Op.getSubReg());
+ MIB.addReg(UseR, {}, Op.getSubReg());
}
RegMap.insert(std::make_pair(DR, NewDR));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 54c3ceacd4bbf..1dabcf32fa8e8 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -748,7 +748,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
MachineOperand &HiOperand,
MachineOperand &LoOperand) {
Register LoReg = LoOperand.getReg();
- unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
+ RegState LoRegKillFlag = getKillRegState(LoOperand.isKill());
DebugLoc DL = InsertPt->getDebugLoc();
MachineBasicBlock *BB = InsertPt->getParent();
@@ -795,7 +795,7 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
unsigned DoubleDestReg,
MachineOperand &HiOperand,
MachineOperand &LoOperand) {
- unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
+ RegState HiRegKillFlag = getKillRegState(HiOperand.isKill());
Register HiReg = HiOperand.getReg();
DebugLoc DL = InsertPt->getDebugLoc();
@@ -844,8 +844,8 @@ void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
unsigned DoubleDestReg,
MachineOperand &HiOperand,
MachineOperand &LoOperand) {
- unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
- unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
+ RegState LoRegKillFlag = getKillRegState(LoOperand.isKill());
+ RegState HiRegKillFlag = getKillRegState(HiOperand.isKill());
Register LoReg = LoOperand.getReg();
Register HiReg = HiOperand.getReg();
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 3900aac884257..6ff384cc26052 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -791,9 +791,9 @@ unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B,
DebugLoc DL = B->findBranchDebugLoc();
Register MuxR = MRI->createVirtualRegister(DRC);
BuildMI(*B, At, DL, D, MuxR)
- .addReg(PredR)
- .addReg(TR, 0, TSR)
- .addReg(FR, 0, FSR);
+ .addReg(PredR)
+ .addReg(TR, {}, TSR)
+ .addReg(FR, {}, FSR);
return MuxR;
}
@@ -990,7 +990,7 @@ void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) {
const TargetRegisterClass *RC = MRI->getRegClass(DefR);
NewR = MRI->createVirtualRegister(RC);
NonPHI = BuildMI(*B, NonPHI, DL, HII->get(TargetOpcode::COPY), NewR)
- .addReg(UseR, 0, UseSR);
+ .addReg(UseR, {}, UseSR);
}
MRI->replaceRegWith(DefR, NewR);
B->erase(I);
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index b8c764a0d3af0..fe1d714c76d97 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -639,12 +639,12 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
/// predicate.
unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
- unsigned DstState = RegState::Define | getUndefRegState(ReadUndef);
- unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
+ RegState DstState = RegState::Define | getUndefRegState(ReadUndef);
+ RegState PredState = getRegState(PredOp) & ~RegState::Kill;
MachineInstrBuilder MIB;
if (SrcOp.isReg()) {
- unsigned SrcState = getRegState(SrcOp);
+ RegState SrcState = getRegState(SrcOp);
if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
SrcState &= ~RegState::Kill;
MIB = BuildMI(B, At, DL, HII->get(Opc))
@@ -698,7 +698,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
// Copy regs to update first.
updateRegs(MI);
MI.setDesc(HII->get(TargetOpcode::COPY));
- unsigned S = getRegState(ST);
+ RegState S = getRegState(ST);
while (MI.getNumOperands() > 1)
MI.removeOperand(MI.getNumOperands()-1);
MachineFunction &MF = *MI.getParent()->getParent();
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 18fcd6a4873fb..e5f8cab15cd75 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -1408,10 +1408,10 @@ bool HexagonGenInsert::generateInserts() {
At = B.getFirstNonPHI();
BuildMI(B, At, DL, D, NewR)
- .addReg(IF.SrcR)
- .addReg(IF.InsR, 0, InsS)
- .addImm(Wdh)
- .addImm(Off);
+ .addReg(IF.SrcR)
+ .addReg(IF.InsR, {}, InsS)
+ .addImm(Wdh)
+ .addImm(Off);
MRI->clearKillFlags(IF.SrcR);
MRI->clearKillFlags(IF.InsR);
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp b/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
index a10c93704a85b..3fd34c6daad94 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
@@ -191,7 +191,7 @@ bool HexagonGenMemAbsolute::runOnMachineFunction(MachineFunction &Fn) {
if (IsLoad)
MIB->getOperand(0).setSubReg(MO0.getSubReg());
else
- MIB.addReg(LoadStoreReg, 0, MO0.getSubReg());
+ MIB.addReg(LoadStoreReg, {}, MO0.getSubReg());
LLVM_DEBUG(dbgs() << "Replaced with " << *MIB << "\n");
// Erase the instructions that got replaced.
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 5344ed8446efc..db72ae58c2966 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -248,7 +248,7 @@ RegSubRegPair HexagonGenPredicate::getPredRegFor(const RegSubRegPair &Reg) {
if (isConvertibleToPredForm(DefI)) {
MachineBasicBlock::iterator DefIt = DefI;
BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
- .addReg(Reg.Reg, 0, Reg.SubReg);
+ .addReg(Reg.Reg, {}, Reg.SubReg);
G2P.insert(std::make_pair(Reg, RegSubRegPair(NewPR)));
LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegSubRegPair(NewPR), *TRI)
<< '\n');
@@ -401,7 +401,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
for (unsigned i = 1; i < NumOps; ++i) {
RegSubRegPair GPR = getRegSubRegPair(MI->getOperand(i));
RegSubRegPair Pred = getPredRegFor(GPR);
- MIB.addReg(Pred.Reg, 0, Pred.SubReg);
+ MIB.addReg(Pred.Reg, {}, Pred.SubReg);
}
LLVM_DEBUG(dbgs() << "generated: " << *MIB);
@@ -410,7 +410,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
const TargetRegisterClass *RC = MRI->getRegClass(OutR.Reg);
Register NewOutR = MRI->createVirtualRegister(RC);
BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
- .addReg(NewPR.Reg, 0, NewPR.SubReg);
+ .addReg(NewPR.Reg, {}, NewPR.SubReg);
MRI->replaceRegWith(OutR.Reg, NewOutR);
MI->eraseFromParent();
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index e65de5658d204..bc6b73645b94f 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -455,7 +455,8 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
return false;
Register PredR;
- unsigned PredPos, PredRegFlags;
+ unsigned PredPos;
+ RegState PredRegFlags;
if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
return false;
@@ -642,7 +643,8 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
// to the header.
bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
Register PredReg;
- unsigned PredPos, PredRegFlags;
+ unsigned PredPos;
+ RegState PredRegFlags;
if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
return nullptr;
MachineInstr *CondI = MRI->getVRegDef(PredReg);
@@ -921,11 +923,10 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
BuildMI(*PH, InsertPos, DL, SubD, SubR);
if (RegToReg)
- SubIB.addReg(End->getReg(), 0, End->getSubReg())
- .addReg(Start->getReg(), 0, Start->getSubReg());
+ SubIB.addReg(End->getReg(), {}, End->getSubReg())
+ .addReg(Start->getReg(), {}, Start->getSubReg());
else
- SubIB.addImm(EndV)
- .addReg(Start->getReg(), 0, Start->getSubReg());
+ SubIB.addImm(EndV).addReg(Start->getReg(), {}, Start->getSubReg());
DistR = SubR;
} else {
// If the loop has been unrolled, we should use the original loop count
@@ -940,8 +941,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
Register SubR = MRI->createVirtualRegister(IntRC);
MachineInstrBuilder SubIB =
BuildMI(*PH, InsertPos, DL, SubD, SubR);
- SubIB.addReg(End->getReg(), 0, End->getSubReg())
- .addImm(-StartV);
+ SubIB.addReg(End->getReg(), {}, End->getSubReg()).addImm(-StartV);
DistR = SubR;
}
}
@@ -960,8 +960,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
Register AddR = MRI->createVirtualRegister(IntRC);
MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
BuildMI(*PH, InsertPos, DL, AddD, AddR)
- .addReg(DistR, 0, DistSR)
- .addImm(AdjV);
+ .addReg(DistR, {}, DistSR)
+ .addImm(AdjV);
AdjR = AddR;
AdjSR = 0;
@@ -982,8 +982,8 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
Register LsrR = MRI->createVirtualRegister(IntRC);
const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
- .addReg(AdjR, 0, AdjSR)
- .addImm(Shift);
+ .addReg(AdjR, {}, AdjSR)
+ .addImm(Shift);
CountR = LsrR;
CountSR = 0;
@@ -1004,7 +1004,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
Register DistCheckR = MRI->createVirtualRegister(PredRC);
const MCInstrDesc &DistCheckD = TII->get(Hexagon::C2_cmpgti);
BuildMI(*PH, InsertPos, DL, DistCheckD, DistCheckR)
- .addReg(DistR, 0, DistSR)
+ .addReg(DistR, {}, DistSR)
.addImm((CmpLess) ? 0 : -1);
// Generate:
@@ -1015,14 +1015,14 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxir);
BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
.addReg(DistCheckR)
- .addReg(CountR, 0, CountSR)
+ .addReg(CountR, {}, CountSR)
.addImm(1);
} else {
const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxri);
BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
.addReg(DistCheckR)
.addImm(1)
- .addReg(CountR, 0, CountSR);
+ .addReg(CountR, {}, CountSR);
}
MuxSR = 0;
}
@@ -1285,7 +1285,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
// Create a copy of the loop count register.
Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
- .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
+ .addReg(TripCount->getReg(), {}, TripCount->getSubReg());
// Add the Loop instruction to the beginning of the loop.
BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
.addReg(CountReg);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 9f258a2b05c52..363f9fd69e3b9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -713,7 +713,7 @@ void HexagonTargetLowering::AdjustHvxInstrPostInstrSelection(
Register SplatV = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
const MachineOperand &InpOp = MI.getOperand(1);
BuildMI(MB, At, DL, TII.get(Hexagon::S2_vsplatrb), SplatV)
- .addReg(InpOp.getReg(), 0, InpOp.getSubReg());
+ .addReg(InpOp.getReg(), {}, InpOp.getSubReg());
Register OutV = MI.getOperand(0).getReg();
BuildMI(MB, At, DL, TII.get(Hexagon::V6_lvsplatw), OutV)
.addReg(SplatV);
@@ -756,8 +756,8 @@ void HexagonTargetLowering::AdjustHvxInstrPostInstrSelection(
Register SplatV = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
const MachineOperand &InpOp = MI.getOperand(1);
BuildMI(MB, At, DL, TII.get(Hexagon::A2_combine_ll), SplatV)
- .addReg(InpOp.getReg(), 0, InpOp.getSubReg())
- .addReg(InpOp.getReg(), 0, InpOp.getSubReg());
+ .addReg(InpOp.getReg(), {}, InpOp.getSubReg())
+ .addReg(InpOp.getReg(), {}, InpOp.getSubReg());
Register OutV = MI.getOperand(0).getReg();
BuildMI(MB, At, DL, TII.get(Hexagon::V6_lvsplatw), OutV).addReg(SplatV);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index d9c334bd385ee..9f511efdfb461 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -677,11 +677,11 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
// New value jump
// (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
// (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
- unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
+ RegState Flags1 = getUndefRegState(Cond[1].isUndef());
LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
<< printMBBReference(MBB););
if (Cond[2].isReg()) {
- unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
+ RegState Flags2 = getUndefRegState(Cond[2].isUndef());
BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
} else if(Cond[2].isImm()) {
@@ -692,7 +692,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
} else {
assert((Cond.size() == 2) && "Malformed cond vector");
const MachineOperand &RO = Cond[1];
- unsigned Flags = getUndefRegState(RO.isUndef());
+ RegState Flags = getUndefRegState(RO.isUndef());
BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
}
return 1;
@@ -716,7 +716,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
} else {
const MachineOperand &RO = Cond[1];
- unsigned Flags = getUndefRegState(RO.isUndef());
+ RegState Flags = getUndefRegState(RO.isUndef());
BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
}
BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
@@ -864,7 +864,7 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool RenamableDest,
bool RenamableSrc) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
- unsigned KillFlag = getKillRegState(KillSrc);
+ RegState KillFlag = getKillRegState(KillSrc);
if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
@@ -928,8 +928,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
getLiveInRegsAt(LiveAtMI, *I);
Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
- unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
- unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
+ RegState UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
+ RegState UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
.addReg(SrcHi, KillFlag | UndefHi)
.addReg(SrcLo, KillFlag | UndefLo);
@@ -969,7 +969,7 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
- unsigned KillFlag = getKillRegState(isKill);
+ RegState KillFlag = getKillRegState(isKill);
MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
@@ -1146,9 +1146,9 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
getLiveInRegsAt(LiveIn, MI);
- unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
- unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
- unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
+ RegState UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
+ RegState UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
+ RegState Kill = getKillRegState(MI.getOperand(1).isKill());
BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
.addReg(SrcHi, UndefHi)
.addReg(SrcLo, Kill | UndefLo);
@@ -1352,13 +1352,13 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Register Rs = Op2.getReg();
Register Rt = Op3.getReg();
DebugLoc DL = MI.getDebugLoc();
- unsigned K1 = getKillRegState(Op1.isKill());
- unsigned K2 = getKillRegState(Op2.isKill());
- unsigned K3 = getKillRegState(Op3.isKill());
+ RegState K1 = getKillRegState(Op1.isKill());
+ RegState K2 = getKillRegState(Op2.isKill());
+ RegState K3 = getKillRegState(Op3.isKill());
if (Rd != Rs)
BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
- .addReg(Pu, (Rd == Rt) ? K1 : 0)
- .addReg(Rs, K2);
+ .addReg(Pu, (Rd == Rt) ? K1 : RegState::NoFlags)
+ .addReg(Rs, K2);
if (Rd != Rt)
BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
.addReg(Pu, K1)
@@ -1375,11 +1375,11 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
Register PReg = Op1.getReg();
assert(Op1.getSubReg() == 0);
- unsigned PState = getRegState(Op1);
+ RegState PState = getRegState(Op1);
if (Op0.getReg() != Op2.getReg()) {
- unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
- : PState;
+ RegState S =
+ Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
.add(Op0)
.addReg(PReg, S)
@@ -1408,11 +1408,11 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
Register PReg = Op1.getReg();
assert(Op1.getSubReg() == 0);
- unsigned PState = getRegState(Op1);
+ RegState PState = getRegState(Op1);
if (Op0.getReg() != Op2.getReg()) {
- unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
- : PState;
+ RegState S =
+ Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
@@ -1717,7 +1717,8 @@ bool HexagonInstrInfo::PredicateInstruction(
}
Register PredReg;
- unsigned PredRegPos, PredRegFlags;
+ unsigned PredRegPos;
+ RegState PredRegFlags = {};
bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
(void)GotPredReg;
assert(GotPredReg);
@@ -4581,7 +4582,8 @@ short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
}
bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
- Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
+ Register &PredReg, unsigned &PredRegPos,
+ RegState &PredRegFlags) const {
if (Cond.empty())
return false;
assert(Cond.size() == 2);
@@ -4592,7 +4594,7 @@ bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
PredReg = Cond[1].getReg();
PredRegPos = 1;
// See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
- PredRegFlags = 0;
+ PredRegFlags = {};
if (Cond[1].isImplicit())
PredRegFlags = RegState::Implicit;
if (Cond[1].isUndef())
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index de982cb56e67e..4535fd6b71ef6 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -471,7 +471,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
int getMinValue(const MachineInstr &MI) const;
short getNonExtOpcode(const MachineInstr &MI) const;
bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
- unsigned &PredRegPos, unsigned &PredRegFlags) const;
+ unsigned &PredRegPos, RegState &PredRegFlags) const;
short getPseudoInstrPair(const MachineInstr &MI) const;
short getRegForm(const MachineInstr &MI) const;
unsigned getSize(const MachineInstr &MI) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
index c9cb4499b1ea0..dbc8a05496ac0 100644
--- a/llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
@@ -164,7 +164,7 @@ bool HexagonQFPOptimizer::optimizeQfp(MachineInstr *MI,
bool HexagonQFPOptimizer::optimizeQfpOneOp(MachineInstr *MI,
MachineBasicBlock *MBB) {
- unsigned Op0F = 0;
+ RegState Op0F = {};
auto It = QFPInstMap.find(MI->getOpcode());
if (It == QFPInstMap.end())
return false;
@@ -210,8 +210,8 @@ bool HexagonQFPOptimizer::optimizeQfpOneOp(MachineInstr *MI,
bool HexagonQFPOptimizer::optimizeQfpTwoOp(MachineInstr *MI,
MachineBasicBlock *MBB) {
- unsigned Op0F = 0;
- unsigned Op1F = 0;
+ RegState Op0F = {};
+ RegState Op1F = {};
auto It = QFPInstMap.find(MI->getOpcode());
if (It == QFPInstMap.end())
return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index ad05d5363ba1e..6a901013106d8 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -627,7 +627,7 @@ void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
unsigned AdrX = PostInc ? (Load ? 2 : 1)
: (Load ? 1 : 0);
MachineOperand &AdrOp = MI->getOperand(AdrX);
- unsigned RSA = getRegState(AdrOp);
+ RegState RSA = getRegState(AdrOp);
MachineOperand &ValOp = Load ? MI->getOperand(0)
: (PostInc ? MI->getOperand(3)
: MI->getOperand(2));
@@ -754,7 +754,7 @@ void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
assert(F != PairMap.end());
const UUPair &P = F->second;
- unsigned RS = getRegState(Op1);
+ RegState RS = getRegState(Op1);
BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
.addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
@@ -788,7 +788,7 @@ void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
- unsigned RS = getRegState(Op1);
+ RegState RS = getRegState(Op1);
unsigned ShiftOpc = Left ? S2_asl_i_r
: (Signed ? S2_asr_i_r : S2_lsr_i_r);
unsigned LoSR = isub_lo;
@@ -908,8 +908,8 @@ void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
- unsigned RS1 = getRegState(Op1);
- unsigned RS2 = getRegState(Op2);
+ RegState RS1 = getRegState(Op1);
+ RegState RS2 = getRegState(Op2);
const TargetRegisterClass *IntRC = &IntRegsRegClass;
unsigned LoSR = isub_lo;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cb3a6dbb5610a..6cb0983780d9f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -7217,7 +7217,7 @@ emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB,
Register ScratchSubReg2 = MRI.createVirtualRegister(SubRC);
BuildMI(*BB, MI, DL, TII->get(LoongArch::COPY), ScratchSubReg1)
- .addReg(XSrc, 0, LoongArch::sub_128);
+ .addReg(XSrc, {}, LoongArch::sub_128);
BuildMI(*BB, MI, DL,
TII->get(HalfSize == 8 ? LoongArch::VINSGR2VR_H
: LoongArch::VINSGR2VR_B),
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index bb20f79fd6fd5..29cd837dcbe06 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -929,7 +929,7 @@ LoongArchInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
case LoongArch::XVSTELM_W:
case LoongArch::XVSTELM_D:
return BuildMI(MBB, MemI, DL, get(MemIOp))
- .addReg(MemI.getOperand(0).getReg(), 0)
+ .addReg(MemI.getOperand(0).getReg())
.addReg(AM.BaseReg)
.addImm(AM.Displacement)
.addImm(MemI.getOperand(3).getImm())
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index d23ec57d46e17..ac548021341ff 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -177,7 +177,7 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
ArrayRef<CalleeSavedInfo> CSI,
- unsigned Flags = 0) {
+ RegState Flags = {}) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
// Add the callee-saved register as live-in. Do not add if the register is
// RA and return address is taken, because it has already been added in
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 6e1eeba4c25a5..8c3740760476a 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -1800,7 +1800,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
.addReg(Ptr).addReg(MaskLSB2);
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
- .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
+ .addReg(Ptr, {}, ArePtrs64bit ? Mips::sub_32 : 0)
+ .addImm(3);
if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
@@ -1987,7 +1988,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
.addReg(Ptr).addReg(MaskLSB2);
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
- .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
+ .addReg(Ptr, {}, ArePtrs64bit ? Mips::sub_32 : 0)
+ .addImm(3);
if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 942194cf31d44..937e33bd840e6 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -230,7 +230,7 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
Register VR0 = MRI.createVirtualRegister(RC);
Register VR1 = MRI.createVirtualRegister(RC);
Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
- unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
+ RegState SrcKill = getKillRegState(I->getOperand(0).isKill());
DebugLoc DL = I->getDebugLoc();
BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
@@ -262,7 +262,7 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
Register VR0 = MRI.createVirtualRegister(RC);
Register VR1 = MRI.createVirtualRegister(RC);
- unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
+ RegState SrcKill = getKillRegState(I->getOperand(1).isKill());
Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
DebugLoc DL = I->getDebugLoc();
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 8f201e532b779..1a6ebc72684b7 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -48,7 +48,7 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MachineFunction &MF) {
MachineInstrBuilder MIB(MF, &MI);
unsigned Mask = MI.getOperand(1).getImm();
- unsigned Flag =
+ RegState Flag =
IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
if (Mask & 1)
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index 0906ab56e1671..b8342d56e72b8 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -3265,14 +3265,14 @@ MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
}
- BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
+ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, {}, Mips::sub_lo);
} else {
Register Wt = RegInfo.createVirtualRegister(
Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
: &Mips::MSA128WEvensRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
- BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
+ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, {}, Mips::sub_lo);
}
MI.eraseFromParent(); // The pseudo instruction is gone now.
@@ -3302,12 +3302,12 @@ MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
DebugLoc DL = MI.getDebugLoc();
if (Lane == 0)
- BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
+ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, {}, Mips::sub_64);
else {
Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
- BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
+ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, {}, Mips::sub_64);
}
MI.eraseFromParent(); // The pseudo instruction is gone now.
@@ -3474,7 +3474,7 @@ MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
.addReg(SrcVecReg)
.addReg(SrcVecReg)
- .addReg(LaneReg, 0, SubRegIdx);
+ .addReg(LaneReg, {}, SubRegIdx);
Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
if (IsFP) {
@@ -3503,7 +3503,7 @@ MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
.addReg(WdTmp2)
.addReg(WdTmp2)
- .addReg(LaneTmp2, 0, SubRegIdx);
+ .addReg(LaneTmp2, {}, SubRegIdx);
MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB;
@@ -3666,7 +3666,8 @@ MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
if(!UsingMips32) {
Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
- BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
+ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp)
+ .addReg(Rt, {}, Mips::sub_32);
Rt = Tmp;
}
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 4a92b1ffc4cf9..bf8c3cc46f550 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -822,7 +822,7 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
- unsigned KillSrc = getKillRegState(Src.isKill());
+ RegState KillSrc = getKillRegState(Src.isKill());
DebugLoc DL = I->getDebugLoc();
bool DstIsLarger, SrcIsLarger;
diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
index 6e01c21daba2a..ef5f93d170408 100644
--- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -301,7 +301,7 @@ void PPCCTRLoops::expandNormalLoops(MachineLoop *ML, MachineInstr *Start,
BuildMI(*Exiting, Dec, Dec->getDebugLoc(), TII->get(TargetOpcode::COPY),
Dec->getOperand(0).getReg())
- .addReg(CMPMIB->getOperand(0).getReg(), 0, PPC::sub_gt);
+ .addReg(CMPMIB->getOperand(0).getReg(), {}, PPC::sub_gt);
// Remove the pseudo instructions.
Start->eraseFromParent();
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 4068188acb653..6a858666bfda6 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -145,7 +145,7 @@ class PPCFastISel final : public FastISel {
return RC->getID() == PPC::VSSRCRegClassID;
}
Register copyRegToRegClass(const TargetRegisterClass *ToRC, Register SrcReg,
- unsigned Flag = 0, unsigned SubReg = 0) {
+ RegState Flag = {}, unsigned SubReg = 0) {
Register TmpReg = createResultReg(ToRC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
@@ -1884,7 +1884,7 @@ bool PPCFastISel::SelectTrunc(const Instruction *I) {
// The only interesting case is when we need to switch register classes.
if (SrcVT == MVT::i64)
- SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
+ SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, {}, PPC::sub_32);
updateValueMap(I, SrcReg);
return true;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d1ab7ece3eaaa..4a8b1998907cd 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13262,7 +13262,7 @@ MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
// We need use 32-bit subregister to avoid mismatch register class in 64-bit
// mode.
BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
- .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
+ .addReg(Ptr1Reg, {}, is64bit ? PPC::sub_32 : 0)
.addImm(3)
.addImm(27)
.addImm(is8bit ? 28 : 27);
@@ -14286,7 +14286,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
// We need use 32-bit subregister to avoid mismatch register class in 64-bit
// mode.
BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
- .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
+ .addReg(Ptr1Reg, {}, is64bit ? PPC::sub_32 : 0)
.addImm(3)
.addImm(27)
.addImm(is8bit ? 28 : 27);
@@ -14604,10 +14604,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Register Hi = MI.getOperand(1).getReg();
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY))
.addDef(Lo)
- .addUse(Src, 0, PPC::sub_gp8_x1);
+ .addUse(Src, {}, PPC::sub_gp8_x1);
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY))
.addDef(Hi)
- .addUse(Src, 0, PPC::sub_gp8_x0);
+ .addUse(Src, {}, PPC::sub_gp8_x0);
} else if (MI.getOpcode() == PPC::LQX_PSEUDO ||
MI.getOpcode() == PPC::STQX_PSEUDO) {
DebugLoc DL = MI.getDebugLoc();
@@ -14659,10 +14659,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
.addImm(FC);
Register Result64 = MRI.createVirtualRegister(&PPC::G8RCRegClass);
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), Result64)
- .addReg(PairResult, 0, PPC::sub_gp8_x0);
+ .addReg(PairResult, {}, PPC::sub_gp8_x0);
if (IsLwat)
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), DstReg)
- .addReg(Result64, 0, PPC::sub_32);
+ .addReg(Result64, {}, PPC::sub_32);
else
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), DstReg)
.addReg(Result64);
@@ -14685,10 +14685,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
.addImm(FC);
Register Result64 = MRI.createVirtualRegister(&PPC::G8RCRegClass);
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), Result64)
- .addReg(PairResult, 0, PPC::sub_gp8_x0);
+ .addReg(PairResult, {}, PPC::sub_gp8_x0);
if (IsLwat_Cond)
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), DstReg)
- .addReg(Result64, 0, PPC::sub_32);
+ .addReg(Result64, {}, PPC::sub_32);
else
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), DstReg)
.addReg(Result64);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7a4f3d5117245..ba9a4cfabd692 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1643,8 +1643,9 @@ void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
}
BuildMI(MBB, MI, dl, get(OpCode), DestReg)
- .addReg(FirstReg).addReg(SecondReg)
- .addReg(Cond[1].getReg(), 0, SubIdx);
+ .addReg(FirstReg)
+ .addReg(SecondReg)
+ .addReg(Cond[1].getReg(), {}, SubIdx);
}
static unsigned getCRBitValue(unsigned CRBit) {
diff --git a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
index a59da9897fe8a..e885767854b66 100644
--- a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+++ b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
@@ -223,7 +223,7 @@ static bool splitMBB(BlockSplitInfo &BSI) {
// Add the branches to ThisMBB.
BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
TII->get(NewBROpcode))
- .addReg(BSI.SplitCond->getOperand(0).getReg(), 0, BSI.SplitCondSubreg)
+ .addReg(BSI.SplitCond->getOperand(0).getReg(), {}, BSI.SplitCondSubreg)
.addMBB(NewBRTarget);
BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
TII->get(PPC::B))
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index bdd79e7e6a0db..8769bb2238980 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1075,7 +1075,8 @@ bool RISCVInstructionSelector::selectExtractSubvector(
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
return false;
- MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(SrcReg, 0, SubRegIdx);
+ MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
+ .addReg(SrcReg, {}, SubRegIdx);
MI.eraseFromParent();
return true;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 421134fb45d7c..7894f64db83dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -509,7 +509,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned KillFlag = getKillRegState(KillSrc);
+ RegState KillFlag = getKillRegState(KillSrc);
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
@@ -1012,9 +1012,9 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
for (const RISCVMatInt::Inst &Inst : Seq) {
bool LastItem = ++Num == Seq.size();
- unsigned DstRegState = getDeadRegState(DstIsDead && LastItem) |
+ RegState DstRegState = getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(DstRenamable);
- unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
+ RegState SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
getRenamableRegState(SrcRenamable);
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
index e5c0812931e66..6c80735c5ca73 100644
--- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
@@ -309,12 +309,12 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmMultiLdSt(
return false;
unsigned NewOpc;
- unsigned StartRegState;
+ RegState StartRegState;
bool AddImplicitRegs = true;
if (IsLoad) {
NewOpc = RISCV::QC_LWMI;
- StartRegState = static_cast<unsigned>(RegState::Define);
+ StartRegState = RegState::Define;
} else {
assert(SMode != StoreMode::Unknown &&
"Group should be large enough to know the store mode");
@@ -357,9 +357,9 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmMultiLdSt(
// Add implicit operands for the additional registers.
for (unsigned i = 1; i < Len; ++i) {
Register R = StartReg + i;
- unsigned State = 0;
+ RegState State;
if (IsLoad)
- State = static_cast<unsigned>(RegState::ImplicitDefine);
+ State = RegState::ImplicitDefine;
else
State = RegState::Implicit |
getKillRegState(Group[i]->getOperand(0).isKill());
@@ -425,8 +425,8 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmLdStPair(
Register NextReg = SecondOp0.getReg();
unsigned XqciOpc;
- unsigned StartRegState;
- unsigned NextRegState = 0;
+ RegState StartRegState;
+ RegState NextRegState = {};
bool AddNextReg = true;
if (Opc == RISCV::LW) {
@@ -443,8 +443,8 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmLdStPair(
return false;
XqciOpc = RISCV::QC_LWMI;
- StartRegState = static_cast<unsigned>(RegState::Define);
- NextRegState = static_cast<unsigned>(RegState::ImplicitDefine);
+ StartRegState = RegState::Define;
+ NextRegState = RegState::ImplicitDefine;
} else {
assert(Opc == RISCV::SW && "Expected a SW instruction");
if (StartReg == NextReg) {
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 43d0446fda2f2..16654125d2b52 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -82,8 +82,8 @@ void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineOperand &HighRegOp = HighPartMI->getOperand(0);
MachineOperand &LowRegOp = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
- unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
- unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
+ RegState Reg128Killed = getKillRegState(LowRegOp.isKill());
+ RegState Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
@@ -107,7 +107,7 @@ void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
// undefined. We could track liveness and skip storing an undefined
// subreg, but this is hopefully rare (discovered with llvm-stress).
// If Reg128 was killed, set kill flag on MI.
- unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+ RegState Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
} else {
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index f499e6f9d0799..d07185e1b62e1 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -353,7 +353,7 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I,
} else {
// Handle if there is no super.
BuildMI(*I.getParent(), I, DL, TII.get(TargetOpcode::COPY), DstReg)
- .addReg(Temp32, 0, X86::sub_16bit);
+ .addReg(Temp32, {}, X86::sub_16bit);
}
I.eraseFromParent();
@@ -1399,7 +1399,7 @@ bool X86InstructionSelector::emitExtractSubreg(Register DstReg, Register SrcReg,
}
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
- .addReg(SrcReg, 0, SubIdx);
+ .addReg(SrcReg, {}, SubIdx);
return true;
}
@@ -1862,7 +1862,7 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I,
if (RegTy.getSizeInBits() == 16) {
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
TypeEntry.HighInReg)
- .addReg(Zero32, 0, X86::sub_16bit);
+ .addReg(Zero32, {}, X86::sub_16bit);
} else if (RegTy.getSizeInBits() == 32) {
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
TypeEntry.HighInReg)
@@ -1904,7 +1904,7 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I,
// Now reference the 8-bit subreg of the result.
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
DstReg)
- .addReg(ResultSuperReg, 0, X86::sub_8bit);
+ .addReg(ResultSuperReg, {}, X86::sub_8bit);
} else {
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
DstReg)
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 317ee48389b66..ed9ad2b7fb45d 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1980,9 +1980,9 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
// register. Unfortunately the operations needed are not uniform enough
// to fit neatly into the table above.
if (VT == MVT::i16) {
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Copy), TypeEntry.HighInReg)
- .addReg(Zero32, 0, X86::sub_16bit);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Copy),
+ TypeEntry.HighInReg)
+ .addReg(Zero32, {}, X86::sub_16bit);
} else if (VT == MVT::i32) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(Copy), TypeEntry.HighInReg)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index e3a4e50a5277d..c99865cc2dfcd 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -6287,7 +6287,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::AVX512_512_SEXT_MASK_64: {
Register Reg = MIB.getReg(0);
Register MaskReg = MIB.getReg(1);
- unsigned MaskState = getRegState(MIB->getOperand(1));
+ RegState MaskState = getRegState(MIB->getOperand(1));
unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64)
? X86::VPTERNLOGQZrrikz
: X86::VPTERNLOGDZrrikz;
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index decf1b3e5e5f9..e0b17ce1be79d 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1926,7 +1926,7 @@ Register X86SpeculativeLoadHardeningImpl::hardenValueInRegister(
unsigned SubRegImm = SubRegImms[Log2_32(Bytes)];
Register NarrowStateReg = MRI->createVirtualRegister(RC);
BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), NarrowStateReg)
- .addReg(StateReg, 0, SubRegImm);
+ .addReg(StateReg, {}, SubRegImm);
StateReg = NarrowStateReg;
}
diff --git a/llvm/lib/Target/X86/X86TileConfig.cpp b/llvm/lib/Target/X86/X86TileConfig.cpp
index acc259cd25923..660bd0a77ab79 100644
--- a/llvm/lib/Target/X86/X86TileConfig.cpp
+++ b/llvm/lib/Target/X86/X86TileConfig.cpp
@@ -201,7 +201,7 @@ static bool tileConfig(MachineFunction &MF,
BuildMI(MBB, ++Iter, DL,
TII->get(IsRow ? X86::MOV8mr : X86::MOV16mr)),
SS, Offset)
- .addReg(R, 0, SubIdx);
+ .addReg(R, {}, SubIdx);
SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});
}
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
index 9c9b39027f8f9..850c04130b865 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
@@ -52,7 +52,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Combiner Rule #1: ReplaceTemp
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
// CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
index 365d0c9fbff49..22cb105355ab1 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
@@ -44,7 +44,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: // Combiner Rule #0: IntrinTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::0in_1out),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
@@ -65,7 +65,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: // Combiner Rule #1: SpecialIntrins
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS),
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
index a23b54afb5125..e359ddf73cd8a 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
@@ -36,7 +36,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
// CHECK-NEXT: // Combiner Rule #0: InstTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // b
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
index 9a7716e54b27f..23794fbc510ad 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
@@ -37,7 +37,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: // Combiner Rule #0: Test0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs
@@ -45,12 +45,12 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: // Combiner Rule #1: Test1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs
// CHECK: // Combiner Rule #2: Test2
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
index ef918d47b9d88..aca7e5ef42fd0 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
@@ -30,7 +30,7 @@ def Test0 : GICombineRule<
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/255,
// CHECK-NEXT: // Combiner Rule #0: Test0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/254, /*Imm*/GIMT_Encode8(42),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst
diff --git a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
index f88045ca9b00b..3bb1379b0ec27 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
@@ -128,7 +128,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp)
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index 64ca63da3b6f0..957f23e105841 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -306,7 +306,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// R19C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (complex_rr:{ *:[i32] } GPR32:{ *:[i32] }:$src2a, GPR32:{ *:[i32] }:$src2b), (select:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))) => (INSN3:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2b, GPR32:{ *:[i32] }:$src2a, (INSN4:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))
// R19C-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::INSN4),
-// R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// R19C-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3
// R19C-NEXT: GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1),
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src5a
diff --git a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
index 97790fb483933..0567c876cfe16 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
@@ -41,12 +41,12 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
// CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
@@ -67,7 +67,7 @@ def : Pat<(i32 (sext SOP:$src)),
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ZEXT),
// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
index 5203c2b4a6e4f..4427c0d4bc663 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
@@ -61,13 +61,13 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77),
// CHECK-LABEL: // (sub:{ *:[i32] } (complex:{ *:[i32] } DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2), 77:{ *:[i32] }) => (SOME_INSN2:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src1, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src2, sub1:{ *:[i32] }))
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, /*SubRegIdx*/GIMT_Encode2(2), // src2
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src1
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -85,7 +85,7 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src
// CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
@@ -105,11 +105,11 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)
// CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (SOME_INSN:{ *:[i32] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }))
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
@@ -140,12 +140,12 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME
// CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
@@ -166,7 +166,7 @@ def : Pat<(i16 (trunc (not DOP:$src))),
// CHECK-LABEL: // (trunc:{ *:[i16] } (xor:{ *:[i32] } DOP:{ *:[i32] }:$src, -1:{ *:[i32] })) => (SUBSOME_INSN:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] }))
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -182,7 +182,7 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: // (trunc:{ *:[i16] } (bitreverse:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
@@ -202,12 +202,12 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: // (trunc:{ *:[i16] } (ctpop:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (SUBSOME_INSN2:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] }))
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -238,7 +238,7 @@ def : Pat<(i32 (zext SOP:$src)),
// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } 0:{ *:[i64] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
index a8597f1d84064..f05d7ec1c5a3d 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
@@ -15,8 +15,8 @@ def : Pat<(abs i32:$x), (I1 (I2 $x))>;
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::I2),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // x
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
index 1f1b557ace608..8fa004373ef69 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
@@ -47,7 +47,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, SPECIAL:{ *:[i32] })) => (MULM_PHYS GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULM_PHYS),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
@@ -86,10 +86,10 @@ def MULM_PHYS : I<(outs), (ins GPR32:$src0, GPR32:$src1),
// GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } R0:{ *:[i32] }, SPECIAL:{ *:[i32] })) => (MULMR0_PHYS GPR32:{ *:[i32] }:$src0)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// GISEL-NEXT: GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::R0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::R0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // R0
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULMR0_PHYS),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
@@ -118,7 +118,7 @@ def MULMR0_PHYS : I<(outs), (ins GPR32:$src0),
// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
// GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
@@ -147,7 +147,7 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
// GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
diff --git a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
index 65ebfa2c5b325..b18d905b0bbf7 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
@@ -18,7 +18,7 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, srcvalue:{ *:[i32] }, i32:{ *:[i32] }:$src1) => (FOO:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GPR32:{ *:[i32] }:$src1)
// GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FOO),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
index a180431b94f6f..54b0f4412da6e 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
@@ -36,7 +36,7 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1]
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2]
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // val
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage
diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
index baf767598f82c..17cc0695a463d 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
@@ -109,7 +109,7 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (ImplicitDefInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src))
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::ImplicitDefInstr),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for MyTarget::R0*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
@@ -135,8 +135,8 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::TwoOutsInstr),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
index 8688e4f04bab9..2513161eec24f 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
@@ -40,11 +40,11 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
// CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
index 7792a97e1377e..3fc05dc368e1c 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
@@ -11,8 +11,8 @@ def s_cc_out : OptionalDefOperand<i32, (ops GPR8, FPR32), (ops (i8 B0), F0)>;
// CHECK-LABEL: // (add:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2) => (tst2:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst2),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
-// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::B0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead),
-// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::F0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead),
+// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::B0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
+// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::F0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rs2
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -22,7 +22,7 @@ def s_cc_out : OptionalDefOperand<i32, (ops GPR8, FPR32), (ops (i8 B0), F0)>;
// CHECK-LABEL: // (imm:{ *:[i32] }):$imm => (tst1:{ *:[i32] } (imm:{ *:[i32] }):$imm)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst1),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
-// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead),
+// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
index c249dcbe214e0..dfb6b1f104711 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
@@ -16,7 +16,7 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
// GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
+// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
index 323aea9e396d1..c0a9d2391b5a2 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
@@ -25,7 +25,7 @@ def I2 : I<(outs GPR32:$rd), (ins GPR32:$rs, undef_tied_2:$opt),
// CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$rs) => (I1:{ *:[i32] } i32:{ *:[i32] }:$rs)
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
-// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 163f1419b370c..7191e49c6dccd 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -162,7 +162,7 @@ void BasicBlockFiller::addInstruction(const MCInst &Inst, const DebugLoc &DL) {
const MCOperand &Op = Inst.getOperand(OpIndex);
if (Op.isReg()) {
const bool IsDef = OpIndex < MCID.getNumDefs();
- unsigned Flags = 0;
+ RegState Flags = {};
const MCOperandInfo &OpInfo = MCID.operands().begin()[OpIndex];
if (IsDef && !OpInfo.isOptionalDef())
Flags |= RegState::Define;
diff --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
index bf7f4fc21eca2..4fabe297c8e42 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -127,7 +127,7 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF
: TargetOpcode::IMPLICIT_DEF;
- unsigned State = getRegState(MO);
+ RegState State = getRegState(MO);
if (MO.getSubReg())
State |= RegState::Undef;
diff --git a/llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp b/llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
index e9d2e9a7b545f..c2ede6381b41e 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
@@ -99,7 +99,7 @@ static void removeDefsFromFunction(Oracle &O, MachineFunction &MF) {
unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF
: TargetOpcode::IMPLICIT_DEF;
- unsigned OpFlags = getRegState(MO) & ~RegState::Implicit;
+ RegState OpFlags = getRegState(MO) & ~RegState::Implicit;
InsPt = BuildMI(MBB, InsPt, DebugLoc(), TII->get(ImpDef))
.addReg(RegPair.Reg, OpFlags, RegPair.SubReg);
}
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 8540faed34e5d..bd1c3a4b9e828 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -2072,7 +2072,8 @@ void AddRegisterRenderer::emitRenderOpcodes(MatchTable &Table,
// register and flags in a single field.
if (IsDef) {
Table << MatchTable::NamedValue(
- 2, IsDead ? "RegState::Define | RegState::Dead" : "RegState::Define");
+ 2, IsDead ? "static_cast<uint16_t>(RegState::Define|RegState::Dead)"
+ : "static_cast<uint16_t>(RegState::Define)");
} else {
assert(!IsDead && "A use cannot be dead");
Table << MatchTable::IntValue(2, 0);
@@ -2105,9 +2106,10 @@ void TempRegRenderer::emitRenderOpcodes(MatchTable &Table,
Table << MatchTable::Comment("TempRegFlags");
if (IsDef) {
SmallString<32> RegFlags;
- RegFlags += "RegState::Define";
+ RegFlags += "static_cast<uint16_t>(RegState::Define";
if (IsDead)
RegFlags += "|RegState::Dead";
+ RegFlags += ")";
Table << MatchTable::NamedValue(2, RegFlags);
} else {
Table << MatchTable::IntValue(2, 0);
@@ -2300,7 +2302,8 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
<< MatchTable::Comment("InsnID")
<< MatchTable::ULEB128Value(InsnID)
<< MatchTable::NamedValue(2, Namespace, Def->getName())
- << (IsDead ? MatchTable::NamedValue(2, "RegState", "Dead")
+ << (IsDead ? MatchTable::NamedValue(
+ 2, "static_cast<unsigned>(RegState::Dead)")
: MatchTable::IntValue(2, 0))
<< MatchTable::LineBreak;
}
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