[llvm] e89a99e - [X86] Add crash regression test reported on #176932 (#177414)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-01-22T19:49:53Z
New Revision: e89a99e26db168f99e928f6a82cab0df13a77c96

URL: https://github.com/llvm/llvm-project/commit/e89a99e26db168f99e928f6a82cab0df13a77c96
DIFF: https://github.com/llvm/llvm-project/commit/e89a99e26db168f99e928f6a82cab0df13a77c96.diff

LOG: [X86] Add crash regression test reported on #176932 (#177414)

is128BitLaneRepeatedShuffleMask can't handle target shuffle masks containing SM_SentinelZero

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-pclmul.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-pclmul.ll b/llvm/test/CodeGen/X86/combine-pclmul.ll
index 1f52df3ebe91f..9101dfd90f1d4 100644
--- a/llvm/test/CodeGen/X86/combine-pclmul.ll
+++ b/llvm/test/CodeGen/X86/combine-pclmul.ll
@@ -308,3 +308,14 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_17(<8 x i64> %a0, <8 x i64> %
   %res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 17)
   ret <8 x i64> %res
 }
+
+; Ensure that target shuffle extraction can handle SM_SentinelZero.
+define <2 x i64> @pclmul_sentinel_zero(<2 x i64> %a0, <2 x i64> %a1) {
+; CHECK-LABEL: pclmul_sentinel_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %and = and <2 x i64> %a0, <i64 -1, i64 0>
+  %res = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %and, <2 x i64> %a1, i8 0)
+  ret <2 x i64> %res
+}