[llvm] [SPIR-V] Implement sample and sample_clamp intrinsics for HLSL resources (PR #177234)
Steven Perron via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 22 11:07:25 PST 2026
https://github.com/s-perron updated https://github.com/llvm/llvm-project/pull/177234
>From b9e530f20d41db9b091ab28e38f6f63e8754d7b7 Mon Sep 17 00:00:00 2001
From: Steven Perron <stevenperron at google.com>
Date: Wed, 21 Jan 2026 13:24:56 -0500
Subject: [PATCH 1/2] [SPIR-V] Implement sample and sample_clamp intrinsics for
HLSL resources
This patch implements the `sample` and `sample_clamp` intrinsics for HLSL
resources in the SPIR-V backend. It adds the necessary intrinsic definitions
in `IntrinsicsDirectX.td` and `IntrinsicsSPIRV.td`, and implements the
instruction selection logic in `SPIRVInstructionSelector.cpp`.
Key changes:
- Added `int_dx_resource_sample` and `int_dx_resource_sample_clamp` intrinsics.
- Added `int_spv_resource_sample` and `int_spv_resource_sample_clamp` intrinsics.
- Implemented `selectSampleIntrinsic` to handle `OpImageSampleImplicitLod` generation.
- Added `ResourceDimension` enum in `DXILABI.h` and `HLSLResource.h`.
- Added a new test case `llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll` to verify the implementation.
---
llvm/include/llvm/IR/IntrinsicsDirectX.td | 11 ++
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 11 ++
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 120 ++++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 3 +
.../CodeGen/SPIRV/hlsl-resources/Sample.ll | 69 ++++++++++
5 files changed, 214 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td
index f79945785566c..23627848b6214 100644
--- a/llvm/include/llvm/IR/IntrinsicsDirectX.td
+++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td
@@ -80,6 +80,17 @@ def int_dx_resource_updatecounter
def int_dx_resource_getdimensions_x
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty], [IntrReadMem]>;
+def int_dx_resource_sample
+ : DefaultAttrsIntrinsic<
+ [llvm_any_ty], [llvm_any_ty, llvm_any_ty, llvm_any_ty, llvm_any_ty],
+ [IntrReadMem]>;
+
+def int_dx_resource_sample_clamp
+ : DefaultAttrsIntrinsic<[llvm_any_ty],
+ [llvm_any_ty, llvm_any_ty, llvm_any_ty, llvm_any_ty,
+ llvm_float_ty],
+ [IntrReadMem]>;
+
// Cast between target extension handle types and dxil-style opaque handles
def int_dx_resource_casthandle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>;
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 293cb750cea98..a93e8ad0ce964 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -181,6 +181,17 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]
def int_spv_resource_getdimensions_x
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty], [IntrReadMem]>;
+ def int_spv_resource_sample
+ : DefaultAttrsIntrinsic<
+ [llvm_any_ty], [llvm_any_ty, llvm_any_ty, llvm_any_ty, llvm_any_ty],
+ [IntrReadMem]>;
+
+ def int_spv_resource_sample_clamp
+ : DefaultAttrsIntrinsic<[llvm_any_ty],
+ [llvm_any_ty, llvm_any_ty, llvm_any_ty,
+ llvm_any_ty, llvm_float_ty],
+ [IntrReadMem]>;
+
def int_spv_resource_getpointer
: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty],
[IntrNoMem]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 626393d4ecb40..73429a8528c28 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -321,6 +321,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectReadImageIntrinsic(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
+ bool selectSampleIntrinsic(Register &ResVReg, const SPIRVType *ResType,
+ MachineInstr &I) const;
bool selectImageWriteIntrinsic(MachineInstr &I) const;
bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -343,6 +345,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
const SPIRVType *ResType = nullptr) const;
Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const;
+ bool isConstantZero(Register Reg) const;
Register buildZerosValF(const SPIRVType *ResType, MachineInstr &I) const;
Register buildOnesVal(bool AllOnes, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -565,6 +568,7 @@ static bool intrinsicHasSideEffects(Intrinsic::ID ID) {
case Intrinsic::spv_resource_handlefrombinding:
case Intrinsic::spv_resource_handlefromimplicitbinding:
case Intrinsic::spv_resource_nonuniformindex:
+ case Intrinsic::spv_resource_sample:
case Intrinsic::spv_rsqrt:
case Intrinsic::spv_saturate:
case Intrinsic::spv_sdot:
@@ -3019,6 +3023,45 @@ Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType,
return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
}
+bool SPIRVInstructionSelector::isConstantZero(Register Reg) const {
+ auto IsZero = [this](Register Reg) {
+ Register R = Reg;
+ MachineInstr *Def = getDefInstrMaybeConstant(R, MRI);
+ if (!Def)
+ return false;
+
+ if (Def->getOpcode() == SPIRV::OpConstantNull)
+ return true;
+
+ if (Def->getOpcode() == TargetOpcode::G_CONSTANT ||
+ Def->getOpcode() == SPIRV::OpConstantI)
+ return getIConstVal(R, MRI) == 0;
+
+ return false;
+ };
+
+ if (IsZero(Reg))
+ return true;
+
+ MachineInstr *Def = MRI->getVRegDef(Reg);
+ if (!Def)
+ return false;
+
+ if (Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
+ (Def->getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
+ cast<GIntrinsic>(Def)->getIntrinsicID() ==
+ Intrinsic::spv_const_composite)) {
+ unsigned StartOp = Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ? 1 : 2;
+ for (unsigned i = StartOp; i < Def->getNumOperands(); ++i) {
+ if (!IsZero(Def->getOperand(i).getReg()))
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType,
MachineInstr &I) const {
// OpenCL uses nulls for Zero. In HLSL we don't use null constants.
@@ -3860,6 +3903,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::spv_resource_load_typedbuffer: {
return selectReadImageIntrinsic(ResVReg, ResType, I);
}
+ case Intrinsic::spv_resource_sample:
+ case Intrinsic::spv_resource_sample_clamp: {
+ return selectSampleIntrinsic(ResVReg, ResType, I);
+ }
case Intrinsic::spv_resource_getpointer: {
return selectResourceGetPointer(ResVReg, ResType, I);
}
@@ -4060,6 +4107,79 @@ bool SPIRVInstructionSelector::selectReadImageIntrinsic(
Pos);
}
+bool SPIRVInstructionSelector::selectSampleIntrinsic(Register &ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+ Register ImageReg = I.getOperand(2).getReg();
+ Register SamplerReg = I.getOperand(3).getReg();
+ Register CoordinateReg = I.getOperand(4).getReg();
+ std::optional<Register> OffsetReg;
+ std::optional<Register> ClampReg;
+
+ if (I.getNumOperands() > 5)
+ OffsetReg = I.getOperand(5).getReg();
+ if (I.getNumOperands() > 6)
+ ClampReg = I.getOperand(6).getReg();
+
+ DebugLoc Loc = I.getDebugLoc();
+
+ auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
+ Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
+ if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
+ *ImageDef, I)) {
+ return false;
+ }
+
+ auto *SamplerDef = cast<GIntrinsic>(getVRegDef(*MRI, SamplerReg));
+ Register NewSamplerReg =
+ MRI->createVirtualRegister(MRI->getRegClass(SamplerReg));
+ if (!loadHandleBeforePosition(
+ NewSamplerReg, GR.getSPIRVTypeForVReg(SamplerReg), *SamplerDef, I)) {
+ return false;
+ }
+
+ MachineIRBuilder MIRBuilder(I);
+ SPIRVType *SampledImageType = GR.getOrCreateOpTypeSampledImage(
+ GR.getSPIRVTypeForVReg(ImageReg), MIRBuilder);
+
+ Register SampledImageReg =
+ MRI->createVirtualRegister(GR.getRegClass(SampledImageType));
+ bool Succeed = BuildMI(*I.getParent(), I, Loc, TII.get(SPIRV::OpSampledImage))
+ .addDef(SampledImageReg)
+ .addUse(GR.getSPIRVTypeID(SampledImageType))
+ .addUse(NewImageReg)
+ .addUse(NewSamplerReg)
+ .constrainAllUses(TII, TRI, RBI);
+ if (!Succeed)
+ return false;
+
+ auto MIB =
+ BuildMI(*I.getParent(), I, Loc, TII.get(SPIRV::OpImageSampleImplicitLod))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(SampledImageReg)
+ .addUse(CoordinateReg);
+
+ uint32_t ImageOperands = 0;
+ if (OffsetReg && !isConstantZero(*OffsetReg)) {
+ ImageOperands |= 0x8; // ConstOffset
+ }
+
+ if (ClampReg) {
+ ImageOperands |= 0x80; // MinLod
+ }
+
+ if (ImageOperands != 0) {
+ MIB.addImm(ImageOperands);
+ if (ImageOperands & 0x8)
+ MIB.addUse(*OffsetReg);
+ if (ImageOperands & 0x80)
+ MIB.addUse(*ClampReg);
+ }
+
+ return MIB.constrainAllUses(TII, TRI, RBI);
+}
+
bool SPIRVInstructionSelector::generateImageReadOrFetch(
Register &ResVReg, const SPIRVType *ResType, Register ImageReg,
Register IdxReg, DebugLoc Loc, MachineInstr &Pos) const {
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index d944a018ba60d..69195500502ca 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -2128,6 +2128,9 @@ void addInstrRequirements(const MachineInstr &MI,
case SPIRV::OpSUDotAccSat:
AddDotProductRequirements(MI, Reqs, ST);
break;
+ case SPIRV::OpImageSampleImplicitLod:
+ Reqs.addCapability(SPIRV::Capability::Shader);
+ break;
case SPIRV::OpImageRead: {
Register ImageReg = MI.getOperand(2).getReg();
SPIRVType *TypeDef = ST.getSPIRVGlobalRegistry()->getResultType(
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
new file mode 100644
index 0000000000000..f4410fc5d841b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
@@ -0,0 +1,69 @@
+; RUN: llc -O0 -mtriple=spirv-vulkan-compute %s -o - | FileCheck %s
+
+; CHECK-DAG: OpCapability Shader
+
+; CHECK-DAG: %[[float:[0-9]+]] = OpTypeFloat 32
+; CHECK-DAG: %[[v4float:[0-9]+]] = OpTypeVector %[[float]] 4
+; CHECK-DAG: %[[image:[0-9]+]] = OpTypeImage %[[float]] 2D 2 0 0 1 Unknown
+; CHECK-DAG: %[[sampled_image:[0-9]+]] = OpTypeSampledImage %[[image]]
+; CHECK-DAG: %[[sampler:[0-9]+]] = OpTypeSampler
+; CHECK-DAG: %[[v2float:[0-9]+]] = OpTypeVector %[[float]] 2
+; CHECK-DAG: %[[v2int:[0-9]+]] = OpTypeVector %[[int:[0-9]+]] 2
+; CHECK-DAG: %[[coord0:[0-9]+]] = OpConstantNull %[[v2float]]
+; CHECK-DAG: %[[coord1_val:[0-9]+]] = OpConstant %[[float]] 0.5
+; CHECK-DAG: %[[coord1:[0-9]+]] = OpConstantComposite %[[v2float]] %[[coord1_val]] %[[coord1_val]]
+; CHECK-DAG: %[[offset1_val:[0-9]+]] = OpConstant %[[int]] 1
+; CHECK-DAG: %[[offset1:[0-9]+]] = OpConstantComposite %[[v2int]] %[[offset1_val]] %[[offset1_val]]
+; CHECK-DAG: %[[minlod_val:[0-9]+]] = OpConstant %[[float]] 1
+
+ at .str = private unnamed_addr constant [4 x i8] c"img\00", align 1
+ at .str.1 = private unnamed_addr constant [5 x i8] c"samp\00", align 1
+ at .str.2 = private unnamed_addr constant [4 x i8] c"out\00", align 1
+
+define void @main() {
+entry:
+ %img = tail call target("spirv.Image", float, 1, 2, 0, 0, 1, 0) @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_1_2_0_0_1_0t(i32 0, i32 0, i32 1, i32 0, ptr @.str)
+ %sampler = tail call target("spirv.Sampler") @llvm.spv.resource.handlefrombinding.tspirv.Samplert(i32 0, i32 1, i32 1, i32 0, ptr @.str.1)
+
+; CHECK: %[[img_val:[0-9]+]] = OpLoad %[[image]]
+; CHECK: %[[sampler_val:[0-9]+]] = OpLoad %[[sampler]]
+; CHECK: %[[si:[0-9]+]] = OpSampledImage %[[sampled_image]] %[[img_val]] %[[sampler_val]]
+; CHECK: %[[res0:[0-9]+]] = OpImageSampleImplicitLod %[[v4float]] %[[si]] %[[coord0]]{{[ ]*$}}
+ %res0 = call <4 x float> @llvm.spv.resource.sample.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0) %img, target("spirv.Sampler") %sampler, <2 x float> <float 0.0, float 0.0>, <2 x i32> zeroinitializer)
+
+; CHECK: %[[img_val2:[0-9]+]] = OpLoad %[[image]]
+; CHECK: %[[sampler_val2:[0-9]+]] = OpLoad %[[sampler]]
+; CHECK: %[[si2:[0-9]+]] = OpSampledImage %[[sampled_image]] %[[img_val2]] %[[sampler_val2]]
+; CHECK: %[[res1:[0-9]+]] = OpImageSampleImplicitLod %[[v4float]] %[[si2]] %[[coord1]] ConstOffset %[[offset1]]{{[ ]*$}}
+ %res1 = call <4 x float> @llvm.spv.resource.sample.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0) %img, target("spirv.Sampler") %sampler, <2 x float> <float 0.5, float 0.5>, <2 x i32> <i32 1, i32 1>)
+
+; CHECK: %[[img_val3:[0-9]+]] = OpLoad %[[image]]
+; CHECK: %[[sampler_val3:[0-9]+]] = OpLoad %[[sampler]]
+; CHECK: %[[si3:[0-9]+]] = OpSampledImage %[[sampled_image]] %[[img_val3]] %[[sampler_val3]]
+; CHECK: %[[res2:[0-9]+]] = OpImageSampleImplicitLod %[[v4float]] %[[si3]] %[[coord0]] MinLod %[[minlod_val]]{{[ ]*$}}
+ %res2 = call <4 x float> @llvm.spv.resource.sample.clamp.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0) %img, target("spirv.Sampler") %sampler, <2 x float> <float 0.0, float 0.0>, <2 x i32> zeroinitializer, float 1.0)
+
+; CHECK: %[[img_val4:[0-9]+]] = OpLoad %[[image]]
+; CHECK: %[[sampler_val4:[0-9]+]] = OpLoad %[[sampler]]
+; CHECK: %[[si4:[0-9]+]] = OpSampledImage %[[sampled_image]] %[[img_val4]] %[[sampler_val4]]
+; CHECK: %[[res3:[0-9]+]] = OpImageSampleImplicitLod %[[v4float]] %[[si4]] %[[coord1]] ConstOffset|MinLod %[[offset1]] %[[minlod_val]]{{[ ]*$}}
+ %res3 = call <4 x float> @llvm.spv.resource.sample.clamp.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0) %img, target("spirv.Sampler") %sampler, <2 x float> <float 0.5, float 0.5>, <2 x i32> <i32 1, i32 1>, float 1.0)
+
+ %tmp0 = fadd <4 x float> %res0, %res1
+ %tmp1 = fadd <4 x float> %res2, %res3
+ %res = fadd <4 x float> %tmp0, %tmp1
+
+; CHECK: %[[out_handle:[0-9]+]] = OpLoad {{.*}}
+; CHECK: OpImageWrite %[[out_handle]] {{.*}} %[[final_res:[0-9]+]]
+ %out = tail call target("spirv.Image", float, 5, 2, 0, 0, 2, 1) @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_1t(i32 0, i32 2, i32 1, i32 0, ptr @.str.2)
+ %out_ptr = call ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_f32_5_2_0_0_2_1t(target("spirv.Image", float, 5, 2, 0, 0, 2, 1) %out, i32 0)
+ store <4 x float> %res, ptr addrspace(11) %out_ptr
+ ret void
+}
+
+declare target("spirv.Image", float, 1, 2, 0, 0, 1, 0) @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_1_2_0_0_1_0t(i32, i32, i32, i32, ptr)
+declare target("spirv.Sampler") @llvm.spv.resource.handlefrombinding.tspirv.Samplert(i32, i32, i32, i32, ptr)
+declare <4 x float> @llvm.spv.resource.sample.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0), target("spirv.Sampler"), <2 x float>, <2 x i32>)
+declare <4 x float> @llvm.spv.resource.sample.clamp.v4f32.tspirv.Image_f32_1_2_0_0_1_0t.tspirv.Samplert.v2f32.v2i32(target("spirv.Image", float, 1, 2, 0, 0, 1, 0), target("spirv.Sampler"), <2 x float>, <2 x i32>, float)
+declare target("spirv.Image", float, 5, 2, 0, 0, 2, 1) @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_1t(i32, i32, i32, i32, ptr)
+declare ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.Image_f32_5_2_0_0_2_1t(target("spirv.Image", float, 5, 2, 0, 0, 2, 1), i32)
\ No newline at end of file
>From 65501d1b4e5b14ce792840c36002d4bf8f2aa946 Mon Sep 17 00:00:00 2001
From: Steven Perron <stevenperron at google.com>
Date: Thu, 22 Jan 2026 14:05:00 -0500
Subject: [PATCH 2/2] Make the isConstantZero function more specific.
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 73429a8528c28..23cfb326bc8d9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -345,7 +345,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
const SPIRVType *ResType = nullptr) const;
Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const;
- bool isConstantZero(Register Reg) const;
+ bool isScalarOrVectorIntConstantZero(Register Reg) const;
Register buildZerosValF(const SPIRVType *ResType, MachineInstr &I) const;
Register buildOnesVal(bool AllOnes, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -3023,10 +3023,17 @@ Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType,
return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
}
-bool SPIRVInstructionSelector::isConstantZero(Register Reg) const {
+bool SPIRVInstructionSelector::isScalarOrVectorIntConstantZero(
+ Register Reg) const {
+ SPIRVType *Type = GR.getSPIRVTypeForVReg(Reg);
+ if (!Type)
+ return false;
+ SPIRVType *CompType = GR.getScalarOrVectorComponentType(Type);
+ if (!CompType || CompType->getOpcode() != SPIRV::OpTypeInt)
+ return false;
+
auto IsZero = [this](Register Reg) {
- Register R = Reg;
- MachineInstr *Def = getDefInstrMaybeConstant(R, MRI);
+ MachineInstr *Def = getDefInstrMaybeConstant(Reg, MRI);
if (!Def)
return false;
@@ -3035,7 +3042,7 @@ bool SPIRVInstructionSelector::isConstantZero(Register Reg) const {
if (Def->getOpcode() == TargetOpcode::G_CONSTANT ||
Def->getOpcode() == SPIRV::OpConstantI)
- return getIConstVal(R, MRI) == 0;
+ return getIConstVal(Reg, MRI) == 0;
return false;
};
@@ -4161,7 +4168,7 @@ bool SPIRVInstructionSelector::selectSampleIntrinsic(Register &ResVReg,
.addUse(CoordinateReg);
uint32_t ImageOperands = 0;
- if (OffsetReg && !isConstantZero(*OffsetReg)) {
+ if (OffsetReg && !isScalarOrVectorIntConstantZero(*OffsetReg)) {
ImageOperands |= 0x8; // ConstOffset
}
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