[llvm] [NVPTX] Update the default SM to 7.5 (PR #176021)
Justin Fargnoli via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 22 09:59:42 PST 2026
https://github.com/justinfargnoli updated https://github.com/llvm/llvm-project/pull/176021
>From 47a62366cfd833de2d0a129264c34c4fd76dde02 Mon Sep 17 00:00:00 2001
From: Justin Fargnoli <jfargnoli at nvidia.com>
Date: Wed, 14 Jan 2026 03:04:01 +0000
Subject: [PATCH 1/3] [NVPTX] Update the default SM to 7.5
---
llvm/docs/ReleaseNotes.md | 5 +++++
llvm/lib/Target/NVPTX/NVPTXSubtarget.h | 4 ++--
llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll | 8 ++++----
llvm/test/CodeGen/NVPTX/default-sm.ll | 10 ++++++++++
llvm/test/CodeGen/NVPTX/i128.ll | 4 ++--
llvm/test/CodeGen/NVPTX/math-intrins.ll | 4 ++--
6 files changed, 25 insertions(+), 10 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/default-sm.ll
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index eb51bc1e44d94..2789932a55640 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -139,6 +139,11 @@ Changes to the LoongArch Backend
Changes to the MIPS Backend
---------------------------
+Changes to the NVPTX Backend
+----------------------------
+
+* The default SM version has been changed from `sm_30` to `sm_75`.
+
Changes to the PowerPC Backend
------------------------------
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index 5f426bf1a15f9..0bc031952901e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -289,9 +289,9 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
return getFullSmVersion() % 10 == 2 ? PTXVersion >= 88
: hasArchAccelFeatures();
}
- // If the user did not provide a target we default to the `sm_30` target.
+ // If the user did not provide a target we default to the `sm_75` target.
std::string getTargetName() const {
- return TargetName.empty() ? "sm_30" : TargetName;
+ return TargetName.empty() ? "sm_75" : TargetName;
}
bool hasTargetName() const { return !TargetName.empty(); }
diff --git a/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll b/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
index 19ec2574e32b4..41b437559aa31 100644
--- a/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
+++ b/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s | FileCheck -check-prefix=ENABLED %s
-; RUN: llc -disable-nvptx-load-store-vectorizer < %s | FileCheck -check-prefix=DISABLED %s
-; RUN: %if ptxas %{ llc < %s | %ptxas-verify %}
-; RUN: %if ptxas %{ llc -disable-nvptx-load-store-vectorizer < %s | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_30 | FileCheck -check-prefix=ENABLED %s
+; RUN: llc -disable-nvptx-load-store-vectorizer < %s -mcpu=sm_30 | FileCheck -check-prefix=DISABLED %s
+; RUN: %if ptxas-sm_30 %{ llc < %s -mcpu=sm_30 | %ptxas-verify -arch=sm_30 %}
+; RUN: %if ptxas-sm_30 %{ llc -disable-nvptx-load-store-vectorizer < %s -mcpu=sm_30 | %ptxas-verify -arch=sm_30 %}
target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/CodeGen/NVPTX/default-sm.ll b/llvm/test/CodeGen/NVPTX/default-sm.ll
new file mode 100644
index 0000000000000..5c8ee8483806a
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/default-sm.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=nvptx | FileCheck %s
+; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
+; RUN: %if ptxas-ptr32 %{ llc < %s -mtriple=nvptx | %ptxas-verify %}
+; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
+
+; CHECK: .target sm_75
+
+define void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/NVPTX/i128.ll b/llvm/test/CodeGen/NVPTX/i128.ll
index 5726c2a5bbb16..75445d625f336 100644
--- a/llvm/test/CodeGen/NVPTX/i128.ll
+++ b/llvm/test/CodeGen/NVPTX/i128.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=nvptx64-- 2>&1 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-- | %ptxas-verify %}
+; RUN: llc < %s -mtriple=nvptx64-- -mcpu=sm_30 2>&1 | FileCheck %s
+; RUN: %if ptxas-sm_30 %{ llc < %s -mtriple=nvptx64-- -mcpu=sm_30 | %ptxas-verify -arch=sm_30 %}
define i128 @srem_i128(i128 %lhs, i128 %rhs) {
; CHECK-LABEL: srem_i128(
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins.ll b/llvm/test/CodeGen/NVPTX/math-intrins.ll
index 625c93c3f0a53..a35d6ec8f17f6 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NOF16
+; RUN: llc < %s -mcpu=sm_30 | FileCheck %s --check-prefixes=CHECK,CHECK-NOF16
; RUN: llc < %s -mcpu=sm_80 -mattr +ptx70 | FileCheck %s --check-prefixes=CHECK,CHECK-F16
; RUN: llc < %s -mcpu=sm_80 -mattr +ptx70 --nvptx-no-f16-math | FileCheck %s --check-prefixes=CHECK,CHECK-SM80-NOF16
-; RUN: %if ptxas %{ llc < %s | %ptxas-verify %}
+; RUN: %if ptxas-sm_30 %{ llc < %s -mcpu=sm_30 | %ptxas-verify -arch=sm_30 %}
; RUN: %if ptxas-sm_80 %{ llc < %s -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
; RUN: %if ptxas-sm_80 %{ llc < %s -mcpu=sm_80 --nvptx-no-f16-math | %ptxas-verify -arch=sm_80 %}
>From 48b890a31c48c7845fe0b4aea40977e83eb8df06 Mon Sep 17 00:00:00 2001
From: Justin Fargnoli <jfargnoli at nvidia.com>
Date: Wed, 14 Jan 2026 22:36:37 +0000
Subject: [PATCH 2/3] Update dbg-declare-alloca.ll
---
llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll b/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
index fa42481016540..72ff20563a1b3 100644
--- a/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
+++ b/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda | FileCheck %s
; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-nvidia-cuda | %ptxas-verify %}
-; CHECK: .target sm_30, debug
+; CHECK: .target sm_75, debug
; CHECK: .visible .func use_dbg_declare()
; CHECK: .local .align 8 .b8 __local_depot0[8];
>From 2aefd094d359ab6f2acca9abc93b3e6851f207d6 Mon Sep 17 00:00:00 2001
From: Justin Fargnoli <jfargnoli at nvidia.com>
Date: Wed, 14 Jan 2026 22:44:56 +0000
Subject: [PATCH 3/3] Update ReleaseNotes.md
---
llvm/docs/ReleaseNotes.md | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 2789932a55640..c75688939baea 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -142,7 +142,9 @@ Changes to the MIPS Backend
Changes to the NVPTX Backend
----------------------------
-* The default SM version has been changed from `sm_30` to `sm_75`.
+* The default SM version has been changed from `sm_30` to `sm_75`. `sm_75` is
+ the oldest GPU variant compatible with the widest range of recent major CUDA
+ Toolkit versions (11/12/13).
Changes to the PowerPC Backend
------------------------------
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