[llvm] [NFCI][AMDGPU] Final touch before moving to `GET_SUBTARGETINFO_MACRO` (PR #177401)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 22 08:58:48 PST 2026
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/177401
None
>From b90d3848d05a316ac5f34f7088685d43e4b9c811 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Thu, 22 Jan 2026 11:25:21 -0500
Subject: [PATCH] [NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO`
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 14 ++--
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 6 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +-
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 2 +-
llvm/lib/Target/AMDGPU/BUFInstructions.td | 12 ++--
llvm/lib/Target/AMDGPU/FLATInstructions.td | 8 +--
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 24 +++----
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 64 +++++++++----------
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 18 +++---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 12 ++--
.../Target/AMDGPU/SIMachineFunctionInfo.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 57 +++++++++--------
12 files changed, 107 insertions(+), 116 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index b2c960edd02a5..7044f91195075 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1094,12 +1094,6 @@ def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
-def FeatureDumpCode : SubtargetFeature <"DumpCode",
- "DumpCode",
- "true",
- "Dump MachineInstrs in the CodeEmitter"
->;
-
def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
"DumpCode",
"true",
@@ -1153,8 +1147,8 @@ def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
// instructions.
-def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
- "FlatForGlobal",
+def FeatureUseFlatForGlobal : SubtargetFeature<"flat-for-global",
+ "UseFlatForGlobal",
"true",
"Force to generate flat instruction for global"
>;
@@ -2471,9 +2465,9 @@ def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
def HasAddPC64Inst : Predicate<"Subtarget->hasAddPC64Inst()">,
AssemblerPredicate<(any_of FeatureGFX1250Insts)>;
-def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
+def HasFlatScratchEnabled : Predicate<"Subtarget->hasFlatScratchEnabled()">;
-def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
+def NotHasFlatScratchEnabled : Predicate<"!Subtarget->hasFlatScratchEnabled()">;
def NotHasMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 682f1aa1f46e1..80bc17f91aa3b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -210,7 +210,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
if (!SPReg) {
const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>();
- if (ST.enableFlatScratch()) {
+ if (ST.hasFlatScratchEnabled()) {
// The stack is accessed unswizzled, so we can use a regular copy.
SPReg = MIRBuilder.buildCopy(PtrTy,
MFI->getStackPtrOffsetReg()).getReg(0);
@@ -739,7 +739,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
// For the fixed ABI, pass workitem IDs in the last argument register.
TLI.allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
- if (!Subtarget.enableFlatScratch())
+ if (!Subtarget.hasFlatScratchEnabled())
CCInfo.AllocateReg(Info->getScratchRSrcReg());
TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
}
@@ -1198,7 +1198,7 @@ void AMDGPUCallLowering::handleImplicitCallArguments(
const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo,
CallingConv::ID CalleeCC,
ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const {
- if (!ST.enableFlatScratch()) {
+ if (!ST.hasFlatScratchEnabled()) {
// Insert copies for the SRD. In the HSA case, this should be an identity
// copy.
auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index fd2afc903a5d3..6019b1f3e19ad 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -412,7 +412,7 @@ static unsigned maxSizeForAddrSpace(const GCNSubtarget &ST, unsigned AS,
switch (AS) {
case AMDGPUAS::PRIVATE_ADDRESS:
// FIXME: Private element size.
- return ST.enableFlatScratch() ? 128 : 32;
+ return ST.hasFlatScratchEnabled() ? 128 : 32;
case AMDGPUAS::LOCAL_ADDRESS:
return ST.useDS128() ? 128 : 64;
case AMDGPUAS::GLOBAL_ADDRESS:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 71ad229b8920b..bfbfcdf3de0dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -284,7 +284,7 @@ uint64_t AMDGPUTTIImpl::getMaxMemIntrinsicInlineSizeThreshold() const {
const FeatureBitset GCNTTIImpl::InlineFeatureIgnoreList = {
// Codegen control options which don't matter.
AMDGPU::FeatureEnableLoadStoreOpt, AMDGPU::FeatureEnableSIScheduler,
- AMDGPU::FeatureEnableUnsafeDSOffsetFolding, AMDGPU::FeatureFlatForGlobal,
+ AMDGPU::FeatureEnableUnsafeDSOffsetFolding, AMDGPU::FeatureUseFlatForGlobal,
AMDGPU::FeaturePromoteAlloca, AMDGPU::FeatureUnalignedScratchAccess,
AMDGPU::FeatureUnalignedAccessMode,
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index bb0e9380e956d..ca8099736c187 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -1990,7 +1990,7 @@ multiclass MUBUFScratchLoadPat_D16 <string Instr,
defm : MUBUFScratchLoadPat_D16_Common<Instr # "_VBUFFER", vt, ld_frag>;
}
-let OtherPredicates = [DisableFlatScratch] in {
+let OtherPredicates = [NotHasFlatScratchEnabled] in {
defm : MUBUFScratchLoadPat <"BUFFER_LOAD_SBYTE", i32, sextloadi8_private>;
defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i32, extloadi8_private>;
defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i32, zextloadi8_private>;
@@ -2009,7 +2009,7 @@ defm : MUBUFScratchLoadPat <"BUFFER_LOAD_DWORDX2", v2i32, load_private>;
defm : MUBUFScratchLoadPat <"BUFFER_LOAD_DWORDX3", v3i32, load_private>;
defm : MUBUFScratchLoadPat <"BUFFER_LOAD_DWORDX4", v4i32, load_private>;
-let OtherPredicates = [D16PreservesUnusedBits, DisableFlatScratch] in {
+let OtherPredicates = [D16PreservesUnusedBits, NotHasFlatScratchEnabled] in {
defm : MUBUFScratchLoadPat_D16<"BUFFER_LOAD_SHORT_D16_HI", v2i16, load_d16_hi_private>;
defm : MUBUFScratchLoadPat_D16<"BUFFER_LOAD_UBYTE_D16_HI", v2i16, az_extloadi8_d16_hi_private>;
defm : MUBUFScratchLoadPat_D16<"BUFFER_LOAD_SBYTE_D16_HI", v2i16, sextloadi8_d16_hi_private>;
@@ -2025,7 +2025,7 @@ defm : MUBUFScratchLoadPat_D16<"BUFFER_LOAD_UBYTE_D16", v2f16, az_extloadi8_d16_
defm : MUBUFScratchLoadPat_D16<"BUFFER_LOAD_SBYTE_D16", v2f16, sextloadi8_d16_lo_private>;
}
-} // End OtherPredicates = [DisableFlatScratch]
+} // End OtherPredicates = [NotHasFlatScratchEnabled]
multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
ValueType vt, PatFrag atomic_st> {
@@ -2094,7 +2094,7 @@ multiclass MUBUFScratchStorePat <string Instr,
defm : MUBUFScratchStorePat_Common<Instr # "_VBUFFER", vt, st, rc>;
}
-let OtherPredicates = [DisableFlatScratch] in {
+let OtherPredicates = [NotHasFlatScratchEnabled] in {
defm : MUBUFScratchStorePat <"BUFFER_STORE_BYTE", i32, truncstorei8_private>;
defm : MUBUFScratchStorePat <"BUFFER_STORE_SHORT", i32, truncstorei16_private>;
defm : MUBUFScratchStorePat <"BUFFER_STORE_BYTE", i16, truncstorei8_private>;
@@ -2109,7 +2109,7 @@ defm : MUBUFScratchStorePat <"BUFFER_STORE_DWORDX3", v3i32, store_private, VReg_
defm : MUBUFScratchStorePat <"BUFFER_STORE_DWORDX4", v4i32, store_private, VReg_128>;
-let OtherPredicates = [HasD16LoadStore, DisableFlatScratch] in {
+let OtherPredicates = [HasD16LoadStore, NotHasFlatScratchEnabled] in {
// Hiding the extract high pattern in the PatFrag seems to not
// automatically increase the complexity.
let AddedComplexity = 1 in {
@@ -2117,7 +2117,7 @@ defm : MUBUFScratchStorePat <"BUFFER_STORE_SHORT_D16_HI", i32, store_hi16_privat
defm : MUBUFScratchStorePat <"BUFFER_STORE_BYTE_D16_HI", i32, truncstorei8_hi16_private>;
}
}
-} // End OtherPredicates = [DisableFlatScratch]
+} // End OtherPredicates = [NotHasFlatScratchEnabled]
//===----------------------------------------------------------------------===//
// MTBUF Patterns
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 05594a7a7d56b..36d54309181ae 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -2452,7 +2452,7 @@ defm : FlatAtomicPat <"FLAT_ATOMIC_PK_ADD_BF16", "atomic_load_fadd_flat", v2bf16
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_PK_ADD_BF16", "atomic_load_fadd_global", v2bf16>;
-let OtherPredicates = [HasFlatScratchInsts, EnableFlatScratch] in {
+let OtherPredicates = [HasFlatScratchInsts, HasFlatScratchEnabled] in {
defm : ScratchFLATLoadPats <SCRATCH_LOAD_UBYTE, extloadi8_private, i32>;
defm : ScratchFLATLoadPats <SCRATCH_LOAD_UBYTE, zextloadi8_private, i32>;
@@ -2510,12 +2510,12 @@ defm : ScratchFLATStorePats <SCRATCH_STORE_BYTE, truncstorei8_private, i32>;
defm : ScratchFLATStorePats <SCRATCH_STORE_SHORT, truncstorei16_private, i32>;
defm : ScratchFLATStorePats <SCRATCH_STORE_DWORDX3, store_private, v3i32>;
-let OtherPredicates = [HasD16LoadStore, HasFlatScratchInsts, EnableFlatScratch] in {
+let OtherPredicates = [HasD16LoadStore, HasFlatScratchInsts, HasFlatScratchEnabled] in {
defm : ScratchFLATStorePats <SCRATCH_STORE_SHORT_D16_HI, truncstorei16_hi16_private, i32>;
defm : ScratchFLATStorePats <SCRATCH_STORE_BYTE_D16_HI, truncstorei8_hi16_private, i32>;
}
-let OtherPredicates = [D16PreservesUnusedBits, HasFlatScratchInsts, EnableFlatScratch] in {
+let OtherPredicates = [D16PreservesUnusedBits, HasFlatScratchInsts, HasFlatScratchEnabled] in {
defm : ScratchFLATLoadPats_D16 <SCRATCH_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_private, v2i16>;
defm : ScratchFLATLoadPats_D16 <SCRATCH_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_private, v2f16>;
defm : ScratchFLATLoadPats_D16 <SCRATCH_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_private, v2i16>;
@@ -2531,7 +2531,7 @@ defm : ScratchFLATLoadPats_D16 <SCRATCH_LOAD_SHORT_D16, load_d16_lo_private, v2i
defm : ScratchFLATLoadPats_D16 <SCRATCH_LOAD_SHORT_D16, load_d16_lo_private, v2f16>;
}
-} // End OtherPredicates = [HasFlatScratchInsts,EnableFlatScratch]
+} // End OtherPredicates = [HasFlatScratchInsts,HasFlatScratchEnabled]
def PrefetchLoc: SDNodeXForm<timm, [{
uint32_t V = N->getZExtValue();
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 0488968a1a2ec..da63628798776 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -119,15 +119,15 @@ GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
// that do not support ADDR64 variants of MUBUF instructions. Such targets
// cannot use a 64 bit offset with a MUBUF instruction to access the global
// address space
- if (!hasAddr64() && !FS.contains("flat-for-global") && !FlatForGlobal) {
- ToggleFeature(AMDGPU::FeatureFlatForGlobal);
- FlatForGlobal = true;
+ if (!hasAddr64() && !FS.contains("flat-for-global") && !UseFlatForGlobal) {
+ ToggleFeature(AMDGPU::FeatureUseFlatForGlobal);
+ UseFlatForGlobal = true;
}
// Unless +-flat-for-global is specified, use MUBUF instructions for global
// address space access if flat operations are not available.
- if (!hasFlat() && !FS.contains("flat-for-global") && FlatForGlobal) {
- ToggleFeature(AMDGPU::FeatureFlatForGlobal);
- FlatForGlobal = false;
+ if (!hasFlat() && !FS.contains("flat-for-global") && UseFlatForGlobal) {
+ ToggleFeature(AMDGPU::FeatureUseFlatForGlobal);
+ UseFlatForGlobal = false;
}
// Set defaults if needed.
@@ -702,7 +702,7 @@ GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,
KernargSegmentPtr = true;
bool IsAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
- if (IsAmdHsaOrMesa && !ST.enableFlatScratch())
+ if (IsAmdHsaOrMesa && !ST.hasFlatScratchEnabled())
PrivateSegmentBuffer = true;
else if (ST.isMesaGfxShader(F))
ImplicitBufferPtr = true;
@@ -720,13 +720,13 @@ GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,
}
if (ST.hasFlatAddressSpace() && AMDGPU::isEntryFunctionCC(CC) &&
- (IsAmdHsaOrMesa || ST.enableFlatScratch()) &&
- // FlatScratchInit cannot be true for graphics CC if enableFlatScratch()
- // is false.
- (ST.enableFlatScratch() ||
+ (IsAmdHsaOrMesa || ST.hasFlatScratchEnabled()) &&
+ // FlatScratchInit cannot be true for graphics CC if
+ // hasFlatScratchEnabled() is false.
+ (ST.hasFlatScratchEnabled() ||
(!AMDGPU::isGraphics(CC) &&
!F.hasFnAttribute("amdgpu-no-flat-scratch-init"))) &&
- !ST.flatScratchIsArchitected()) {
+ !ST.hasArchitectedFlatScratch()) {
FlatScratchInit = true;
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 1a6b6656eb207..f4ecdbde4703f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -288,45 +288,42 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
unsigned MaxPrivateElementSize = 0;
// Dynamically set bits that enable features.
- bool FlatForGlobal = false;
- bool SupportsXNACK = false;
-
- // This should not be used directly. 'TargetID' tracks the dynamic settings
- // for XNACK.
- bool EnableXNACK = false;
-
- bool EnableTgSplit = false;
- bool EnableCuMode = false;
- bool EnablePreciseMemory = false;
-
- // Used as options.
- bool EnableLoadStoreOpt = false;
- bool EnableUnsafeDSOffsetFolding = false;
- bool EnableSIScheduler = false;
- bool EnableDS128 = false;
- bool EnablePRTStrictNull = false;
- bool DumpCode = false;
+ bool DynamicVGPR = false;
+ bool DynamicVGPRBlockSize32 = false;
+ bool ScalarizeGlobal = false;
/// The maximum number of instructions that may be placed within an S_CLAUSE,
/// which is one greater than the maximum argument to S_CLAUSE. A value of 0
/// indicates a lack of S_CLAUSE support.
unsigned MaxHardClauseLength = 0;
- bool SupportsSRAMECC = false;
- bool DynamicVGPR = false;
- bool DynamicVGPRBlockSize32 = false;
- bool RequiresAlignVGPR = false;
+ //===--------------------------------------------------------------------===//
+ /// Controlled by subtarget features defined in AMDGPU.td
+ //===--------------------------------------------------------------------===//
+ bool DumpCode = false;
+ bool EnableCuMode = false;
+ bool EnableDS128 = false;
+ bool EnableFlatScratch = false;
+ bool EnableLoadStoreOpt = false;
+ bool EnablePreciseMemory = false;
+ bool EnablePRTStrictNull = false;
+ bool EnableSIScheduler = false;
// This should not be used directly. 'TargetID' tracks the dynamic settings
// for SRAMECC.
bool EnableSRAMECC = false;
-
- bool EnableFlatScratch = false;
- bool ScalarizeGlobal = false;
+ bool EnableTgSplit = false;
+ bool EnableUnsafeDSOffsetFolding = false;
+ bool EnableXNACK = false;
+ bool RequiresAlignVGPR = false;
bool RequiresCOV6 = false;
- bool UseBlockVGPROpsForCSR = false;
-
bool RequiresWaitsBeforeSystemScopeStores = false;
+ bool SupportsSRAMECC = false;
+ // This should not be used directly. 'TargetID' tracks the dynamic settings
+ // for XNACK.
+ bool SupportsXNACK = false;
bool UseAddPC64Inst = false;
+ bool UseBlockVGPROpsForCSR = false;
+ bool UseFlatForGlobal = false;
#define DECL_HAS_MEMBER(Name) bool Has##Name = false;
GCN_SUBTARGET_HAS_FEATURE(DECL_HAS_MEMBER)
@@ -429,7 +426,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
int getLDSBankCount() const { return LDSBankCount; }
unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
- return (ForBufferRSrc || !enableFlatScratch()) ? MaxPrivateElementSize : 16;
+ return (ForBufferRSrc || !hasFlatScratchEnabled()) ? MaxPrivateElementSize
+ : 16;
}
unsigned getConstantBusLimit(unsigned Opcode) const;
@@ -541,7 +539,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return getGeneration() >= AMDGPUSubtarget::GFX10;
}
- bool useFlatForGlobal() const { return FlatForGlobal; }
+ bool useFlatForGlobal() const { return UseFlatForGlobal; }
/// \returns If target supports ds_read/write_b128 and user enables generation
/// of ds_read/write_b128.
@@ -594,8 +592,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasFlatScratchSVSMode() const { return HasGFX940Insts || HasGFX11Insts; }
- bool enableFlatScratch() const {
- return flatScratchIsArchitected() ||
+ bool hasFlatScratchEnabled() const {
+ return hasArchitectedFlatScratch() ||
(EnableFlatScratch && hasFlatScratchInsts());
}
@@ -932,10 +930,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return getGeneration() >= AMDGPUSubtarget::GFX9;
}
- /// \returns true if the flat_scratch register is initialized by the HW.
- /// In this case it is readonly.
- bool flatScratchIsArchitected() const { return HasArchitectedFlatScratch; }
-
/// \returns true if the machine has merged shaders in which s0-s7 are
/// reserved by the hardware and user SGPRs start at s8
bool hasMergedShaders() const { return getGeneration() >= GFX9; }
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 117ea136b2fe4..0ef81a83d1be8 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -139,8 +139,8 @@ static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI,
MachineBasicBlock::iterator I, const DebugLoc &DL,
Register SpillReg, int FI, Register FrameReg,
int64_t DwordOff = 0) {
- unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
- : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
+ unsigned Opc = ST.hasFlatScratchEnabled() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
+ : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
MachineFrameInfo &FrameInfo = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -163,8 +163,8 @@ static void buildEpilogRestore(const GCNSubtarget &ST,
MachineBasicBlock::iterator I,
const DebugLoc &DL, Register SpillReg, int FI,
Register FrameReg, int64_t DwordOff = 0) {
- unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
- : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
+ unsigned Opc = ST.hasFlatScratchEnabled() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
+ : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
MachineFrameInfo &FrameInfo = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -591,7 +591,7 @@ Register SIFrameLowering::getEntryFunctionReservedScratchRsrcReg(
}
static unsigned getScratchScaleFactor(const GCNSubtarget &ST) {
- return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize();
+ return ST.hasFlatScratchEnabled() ? 1 : ST.getWavefrontSize();
}
void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
@@ -629,7 +629,7 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
// This will return `Register()` in cases where there are no actual
// uses of the SRSRC.
Register ScratchRsrcReg;
- if (!ST.enableFlatScratch())
+ if (!ST.hasFlatScratchEnabled())
ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);
// Make the selected register live throughout the function.
@@ -755,10 +755,10 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
bool NeedsFlatScratchInit =
MFI->getUserSGPRInfo().hasFlatScratchInit() &&
(MRI.isPhysRegUsed(AMDGPU::FLAT_SCR) || FrameInfo.hasCalls() ||
- (!allStackObjectsAreDead(FrameInfo) && ST.enableFlatScratch()));
+ (!allStackObjectsAreDead(FrameInfo) && ST.hasFlatScratchEnabled()));
if ((NeedsFlatScratchInit || ScratchRsrcReg) &&
- PreloadedScratchWaveOffsetReg && !ST.flatScratchIsArchitected()) {
+ PreloadedScratchWaveOffsetReg && !ST.hasArchitectedFlatScratch()) {
MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
}
@@ -1993,7 +1993,7 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
// TODO: We could try sorting the objects to find a hole in the first bytes
// rather than allocating as close to possible. This could save a lot of space
// on frames with alignment requirements.
- if (ST.enableFlatScratch()) {
+ if (ST.hasFlatScratchEnabled()) {
if (TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS,
SIInstrFlags::FlatScratch))
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 1ec0204005f12..bdfe773d03ff0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1902,7 +1902,7 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
}
if (AS == AMDGPUAS::PRIVATE_ADDRESS)
- return Subtarget->enableFlatScratch()
+ return Subtarget->hasFlatScratchEnabled()
? isLegalFlatAddressingMode(AM, AMDGPUAS::PRIVATE_ADDRESS)
: isLegalMUBUFAddressingMode(AM);
@@ -3124,7 +3124,7 @@ static void reservePrivateMemoryRegs(const TargetMachine &TM,
// the scratch registers to pass in.
bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
- if (!ST.enableFlatScratch()) {
+ if (!ST.hasFlatScratchEnabled()) {
if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
// If we have stack objects, we unquestionably need the private buffer
// resource. For the Code Object V2 ABI, this will be the first 4 user
@@ -3267,7 +3267,7 @@ SDValue SITargetLowering::LowerFormalArguments(
!Info->hasLDSKernelId() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ());
(void)UserSGPRInfo;
- if (!Subtarget->enableFlatScratch())
+ if (!Subtarget->hasFlatScratchEnabled())
assert(!UserSGPRInfo.hasFlatScratchInit());
if ((CallConv != CallingConv::AMDGPU_CS &&
CallConv != CallingConv::AMDGPU_Gfx &&
@@ -3338,7 +3338,7 @@ SDValue SITargetLowering::LowerFormalArguments(
allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
// FIXME: Sink this into allocateSpecialInputSGPRs
- if (!Subtarget->enableFlatScratch())
+ if (!Subtarget->hasFlatScratchEnabled())
CCInfo.AllocateReg(Info->getScratchRSrcReg());
allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
@@ -4250,7 +4250,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
if (!IsSibCall || IsChainCallConv) {
- if (!Subtarget->enableFlatScratch()) {
+ if (!Subtarget->hasFlatScratchEnabled()) {
SmallVector<SDValue, 4> CopyFromChains;
// In the HSA case, this should be an identity copy.
@@ -12762,7 +12762,7 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
case 16:
if (NumElements > 4 ||
- (NumElements == 3 && !Subtarget->enableFlatScratch()))
+ (NumElements == 3 && !Subtarget->hasFlatScratchEnabled()))
return SplitVectorStore(Op, DAG);
return SDValue();
default:
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index cfb386ea87446..d484d33f8d8c4 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -114,7 +114,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
FrameOffsetReg = AMDGPU::SGPR33;
StackPtrOffsetReg = AMDGPU::SGPR32;
- if (!ST.enableFlatScratch()) {
+ if (!ST.hasFlatScratchEnabled()) {
// Non-entry functions have no special inputs for now, other registers
// required for scratch access.
ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
@@ -169,7 +169,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
if (WorkItemIDZ)
WorkItemIDY = true;
- if (!ST.flatScratchIsArchitected()) {
+ if (!ST.hasArchitectedFlatScratch()) {
PrivateSegmentWaveByteOffset = true;
// HS and GS always have the scratch wave offset in SGPR5 on GFX9.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 409509120c32d..64f2b08672030 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -866,7 +866,8 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
[[fallthrough]];
}
case AMDGPU::V_ADD_U32_e64:
- // FIXME: This optimization is barely profitable enableFlatScratch as-is.
+ // FIXME: This optimization is barely profitable hasFlatScratchEnabled
+ // as-is.
//
// Much of the benefit with the MUBUF handling is we avoid duplicating the
// shift of the frame register, which isn't needed with scratch.
@@ -874,7 +875,7 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
// materializeFrameBaseRegister doesn't know the register classes of the
// uses, and unconditionally uses an s_add_i32, which will end up using a
// copy for the vector uses.
- return !ST.enableFlatScratch();
+ return !ST.hasFlatScratchEnabled();
case AMDGPU::V_ADD_CO_U32_e32:
if (ST.getConstantBusLimit(AMDGPU::V_ADD_CO_U32_e32) < 2 &&
!isFIPlusImmOrVGPR(*this, *MI))
@@ -914,12 +915,12 @@ Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
MachineFunction *MF = MBB->getParent();
const SIInstrInfo *TII = ST.getInstrInfo();
MachineRegisterInfo &MRI = MF->getRegInfo();
- unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32
- : AMDGPU::V_MOV_B32_e32;
+ unsigned MovOpc =
+ ST.hasFlatScratchEnabled() ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
Register BaseReg = MRI.createVirtualRegister(
- ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass
- : &AMDGPU::VGPR_32RegClass);
+ ST.hasFlatScratchEnabled() ? &AMDGPU::SReg_32_XEXEC_HIRegClass
+ : &AMDGPU::VGPR_32RegClass);
if (Offset == 0) {
BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
@@ -929,16 +930,16 @@ Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
- Register FIReg = MRI.createVirtualRegister(
- ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass
- : &AMDGPU::VGPR_32RegClass);
+ Register FIReg = MRI.createVirtualRegister(ST.hasFlatScratchEnabled()
+ ? &AMDGPU::SReg_32_XM0RegClass
+ : &AMDGPU::VGPR_32RegClass);
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
.addImm(Offset);
BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
.addFrameIndex(FrameIdx);
- if (ST.enableFlatScratch() ) {
+ if (ST.hasFlatScratchEnabled()) {
// FIXME: Make sure scc isn't live in.
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg)
.addReg(OffsetReg, RegState::Kill)
@@ -991,9 +992,9 @@ void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
MachineRegisterInfo &MRI = MF->getRegInfo();
// FIXME: materializeFrameBaseRegister does not know the register class of
- // the uses of the frame index, and assumes SGPR for enableFlatScratch. Emit
- // a copy so we have a legal operand and hope the register coalescer can
- // clean it up.
+ // the uses of the frame index, and assumes SGPR for hasFlatScratchEnabled.
+ // Emit a copy so we have a legal operand and hope the register coalescer
+ // can clean it up.
if (isSGPRReg(MRI, BaseReg)) {
Register BaseRegVGPR =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
@@ -1980,13 +1981,15 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
SB.EltSize, Alignment);
if (IsLoad) {
- unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
- : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
+ unsigned Opc = ST.hasFlatScratchEnabled()
+ ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
+ : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
} else {
- unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
- : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
+ unsigned Opc = ST.hasFlatScratchEnabled()
+ ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
+ : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
// This only ever adds one VGPR spill
@@ -2442,13 +2445,13 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
unsigned Opc;
if (MI->getOpcode() == AMDGPU::SI_SPILL_V16_SAVE) {
- assert(ST.enableFlatScratch() && "Flat Scratch is not enabled!");
+ assert(ST.hasFlatScratchEnabled() && "Flat Scratch is not enabled!");
Opc = AMDGPU::SCRATCH_STORE_SHORT_SADDR_t16;
} else {
Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_SAVE
? AMDGPU::SCRATCH_STORE_BLOCK_SADDR
- : ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
- : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
+ : ST.hasFlatScratchEnabled() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
+ : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
}
auto *MBB = MI->getParent();
@@ -2527,15 +2530,15 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
unsigned Opc;
if (MI->getOpcode() == AMDGPU::SI_SPILL_V16_RESTORE) {
- assert(ST.enableFlatScratch() && "Flat Scratch is not enabled!");
+ assert(ST.hasFlatScratchEnabled() && "Flat Scratch is not enabled!");
Opc = ST.d16PreservesUnusedBits()
? AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_t16
: AMDGPU::SCRATCH_LOAD_USHORT_SADDR;
} else {
Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE
? AMDGPU::SCRATCH_LOAD_BLOCK_SADDR
- : ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
- : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
+ : ST.hasFlatScratchEnabled() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
+ : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
}
auto *MBB = MI->getParent();
@@ -2614,7 +2617,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
Offset = 0;
}
- if (FrameReg && !ST.enableFlatScratch()) {
+ if (FrameReg && !ST.hasFlatScratchEnabled()) {
// We should just do an in-place update of the result register. However,
// the value there may also be used by the add, in which case we need a
// temporary register.
@@ -2635,7 +2638,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
}
if ((!OtherOp->isImm() || OtherOp->getImm() != 0) && MaterializedReg) {
- if (ST.enableFlatScratch() &&
+ if (ST.hasFlatScratchEnabled() &&
!TII->isOperandLegal(*MI, Src1Idx, OtherOp)) {
// We didn't need the shift above, so we have an SGPR for the frame
// register, but may have a VGPR only operand.
@@ -2796,7 +2799,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (OtherOp.isReg() && OtherOp.getReg() != DstOp.getReg())
TmpReg = DstOp.getReg();
- if (FrameReg && !ST.enableFlatScratch()) {
+ if (FrameReg && !ST.hasFlatScratchEnabled()) {
// FIXME: In the common case where the add does not also read its result
// (i.e. this isn't a reg += fi), it's not finding the dest reg as
// available.
@@ -2881,7 +2884,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
}
int64_t Offset = FrameInfo.getObjectOffset(Index);
- if (ST.enableFlatScratch()) {
+ if (ST.hasFlatScratchEnabled()) {
if (TII->isFLATScratch(*MI)) {
assert(
(int16_t)FIOperandNum ==
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